Digital Systems Design Lab (DSDL) - Lab 2::Adders

DIGITAL SYSTEMS DEIGN LAB

M. Sc. NGUYỄN VÕ THẤT THUYẾT

ECE Program | Faculty of Engineering | Vietnamese-German University
[email protected]

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

Revision
Version Modified date Modified by Description
v0r0 03/02/2023 Thuyet N. New creation

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Contents
Revision .................................................................................................................................................. ii
Lab Introduction ..................................................................................................................................... 1
Description .......................................................................................................................................... 1
Hardware ............................................................................................................................................. 1
Software ...............................................................................................................................................2
Lab documents .................................................................................................................................... 5
Lab content .......................................................................................................................................... 5
Assessment .......................................................................................................................................... 6
LAB 2: Adders ........................................................................................................................................7
Goal ......................................................................................................................................................7
Prerequisite .......................................................................................................................................... 7
Required hardware and software .........................................................................................................7
Theory ..................................................................................................................................................8
One-bit full adder (FA) .................................................................................................................... 8
Four-bit adder ...................................................................................................................................9
Tasks ..................................................................................................................................................10
Planning .............................................................................................................................................11
Step-by-step instructions ...................................................................................................................12
Task 1: 1-bit full adder (FA) ..........................................................................................................12
Create an empty Quartus project (refer to lab1) ............................................................................12
Write Verilog HDL code ............................................................................................................... 12
[Simulation] ................................................................................................................................... 12
[Emulation] .................................................................................................................................... 14
Task 2: 4-bit adder ......................................................................................................................... 16
Create an empty Quartus project (refer to lab1) ............................................................................16
Write Verilog HDL code ............................................................................................................... 16
[Simulation] ................................................................................................................................... 17
[Emulation] .................................................................................................................................... 19
Checklist ............................................................................................................................................ 21

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Lab Introduction

Description

This lab is to design and implement the basic digital circuits (parity circuit, adders, counters etc.) on
an FPGA board by Verilog HDL (hardware description language).

Hardware

It is Terasic DE10-Nano with an Intel FPGA

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Software
Quartus Lite Edition and ModelSim Starter Edition are tools used in this lab for FPGA
programming as well as simulation.

Download and installation

1) Create an account on Intel.com
2) Search for ‘Quartus download' and download Quartus Lite Edition + ModelSim-Intel
FPGA Edition (Starter Edition)
Please choose VERSION 20.1.1
3) Select files as below and download

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

Files: Quartus lite + ModelSim-IntelFPGA setup files, Cyclone IV and Cyclone V device files
Note: Put all files in the same folder and then run Quartus set-up file.

Follow set-up instruction, and select installed components as below

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Lab documents

LabDocs:Lab guidelines
Preparation:It has to be finished before each lab session
RefDocs:References
1) 00_fpgas_for_dummies_ebook.pdf: an book for beginners
2) 01_VGU_ECE_BasicsofFPGAandVerilog.pdf: basics of FPGA and Verilog HDL
3) 02_VGU_ECE_DigitalSystemsDesignLab_slides.pdf : introduction slides
4) 04_DE10-Nano_User_manual.pdf: hardware manual

Lab content

Lab 1 – Fundamentals of Logic Gates

Lab 2 - Adders
Lab 3 - Counters
Lab 4 – Simple Code

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Assessment

The assessment criteria are followed the below table

Lab Estimated Item Points Note
Preparation 10 No preparation for first lab
Lab 1 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 2 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 3 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 4 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Total points 100

Important note:

AM session starting from 09:00

PM session starting from 13:00
PASS: If the total points >=75 AND
FAIL: If the total points <75 OR miss an attendance check

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
LAB 2: Adders
Goal

In this lab exercise, students learn how to design and implement 1-bit full adder (FA) and 4-bit
adders (combination of 4 FAs) on an FPGA with Verilog HDL.

Prerequisite

This requires knowledge of adder logics.

Finished lab 1.

Required hardware and software

1) Intel Quartus Lite 20.1.1

2) ModelSim IntelFPGA Starter 20.1.1
3) 01 x FPGA board, DE10-Nano
4) 01 x micro USB cable + 01 x AC to DC adapter (5 VDC, 2A output)

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Theory

One-bit full adder (FA)

C = xy + xz + yz
S=x^y^z

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Four-bit adder

The implementation of 4-bit adder by connecting four of 1-bit adder as below circuit.

cout=1 when the result is overflow.

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Tasks

1) Task 1: Implementing a 1-bit full adder (FA)

2) Task 2: Implementing a 4-bit adder

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Planning

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Step-by-step instructions

Task 1: 1-bit full adder (FA)

Create an empty Quartus project (refer to lab1)

Write Verilog HDL code

Create Verilog file(s) as below

[Simulation]

fa.v
module lab2(
x,
y,
z,

c,
s

);

input x; //in 1
input y; //in 2
input z; //carry in

output c; //carry out

output s; //sum

assign c = (x&y) | (x&z) | (y&z);

assign s = x ^ y ^ z;

endmodule

Compile to check the syntax errors

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
[Emulation]

fa.v
module lab2(
x,
y,
z,

c,
s

);

input x; //in 1
input y; //in 2
input z; //carry in

output c; //carry out

output s; //sum

assign c = (x&y) | (x&z) | (y&z);

assign s = x ^ y ^ z;

endmodule

Compile to check the syntax errors

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

Pin assignments

Compile again to generate the bit stream file

Load bit stream file to FPGA

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Task 2: 4-bit adder

Create an empty Quartus project (refer to lab1)

Write Verilog HDL code

Create Verilog file(s) as below
Reuse 1-bit full adder
Connect 4 x 1-bit fa to create 4-bit adder

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
[Simulation]

fourbitadder.v
module lab2(
a,
b,

cout,
s

);

input [3:0] a; // 4-bit in 1

input [3:0] b; // 4-bit in 2

output [3:0] s; // sum

output cout; // carry out
wire c1,c2,c3;

// connecting 4 x 1-bit fa → 4-bit adder

fa fa_00(
.x(a[0]),
.y(b[0]),
.z(1'b0),

.c(c1),
.s(s[0])
);

fa fa_01(
.x(a[1]),
.y(b[1]),
.z(c1),

.c(c2),
.s(s[1])
);

fa fa_02(
.x(a[2]), //a2
.y(b[2]), //b2
.z(c2),

.c(c3),
.s(s[2])
);

fa fa_03(
.x(a[3]), //a3
.y(b[3]), //b3
.z(c3),

.c(cout),
.s(s[3])
);

endmodule

Compile to check syntax errors

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Digital Systems Design Lab (DSDL) - Lab 2::Adders

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
[Emulation]

fourbitadder.v
module lab2(
a,
b,

cout,
s

);

input [3:0] a; // 4-bit in 1

input [3:0] b; // 4-bit in 2

output [3:0] s; // sum

output cout; // carry out
wire c1,c2,c3;

// connecting 4 x 1-bit fa → 4-bit adder

fa fa_00(
.x(a[0]),
.y(b[0]),
.z(1'b0),

.c(c1),
.s(s[0])
);

fa fa_01(
.x(a[1]),
.y(b[1]),
.z(c1),

.c(c2),
.s(s[1])
);

fa fa_02(
.x(1'b0), //a2
.y(1’b0), //b2
.z(c2),

.c(c3),
.s(s[2])
);

fa fa_03(
.x(1'b0), //a3
.y(1’b0), //b3
.z(c3),

.c(cout),
.s(s[3])
);

endmodule

Compile to check syntax errors

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Pin assignments

Compile again to generate the bit stream file

Load bit stream file to FPGA

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Digital Systems Design Lab (DSDL) - Lab 2::Adders
Checklist

No Description Completed
1 Create an empty Quartus project for task 1
2 Implement task 1
3 Simulate task 1
4 Test logic of task 1 on FPGA board (board test)
5 Create an empty Quartus project for task 2
6 Implement task 2
7 Simulate task 2
8 Test logic of task 2 on FPGA board (board test)

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