11/12/24, 8:43 PM

Finite state machines

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Problem 1. (Katz, problem 8.13) A finite state machine has one input and one output. The output becomes 1
and remains 1 thereafter when at least two 0's and two 1's have occurred as inputs, regardless of the order of
appearance.

A. Assuming this is to be implemented as a Moore machine, draw a state transition diagram for the
machine. Hint: You can do this in nine states.
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B. Write a Verilog module that implements the machine. Your module should have the following
inputs/outputs.

CLK
used to clock the FSM
RESET
asserted high to reset the FSM to its initial state
ONE
asserted high to input a "1". Note that this signal may stay high for many cycles (eg, it's
generated by a button press) before returning low. Each high period should count as a
single "1" input, ie, to inputs two "1"s in series, the signal must return low inbetween the
first and second "1".
ZERO
asserted high to input a "0". This signal has the same timing protcol as ONE above.
OUT

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asserted high when at least two "0"s and two "1"s have occurred as inputs.

Assume that all inputs have been externally synchronized with clk.

module fsm01(clk,reset,one,zero,out);
// state assignments
parameter STATE_0_0 = 0; // 0 zeroes, 0 ones
parameter STATE_0_1 = 1; // 1 zero, 0 ones
parameter STATE_0_2 = 2; // 2 zeroes, 0 ones
parameter STATE_1_0 = 3; // 0 zeroes, 1 one
parameter STATE_1_1 = 4; // 1 zero, 1 one
parameter STATE_1_2 = 5; // 2 zeroes, 1 one
parameter STATE_2_0 = 6; // 0 zeroes, 2 ones
parameter STATE_2_1 = 7; // 1 zero, 2 ones
parameter STATE_2_2 = 8; // 2 zeroes, 2 ones

input clk,reset,one,zero;
output out;

// level-to-pulse converters for ZERO and ONE inputs

// fsm
reg [3:0] state;
always @ (posedge clk)
begin
if (reset) state <= STATE_0_0;
else case (state)
STATE_0_0: state <= input_one ? STATE_1_0 : input_zero ? STATE_0_1 : state;
STATE_0_1: state <= input_one ? STATE_1_1 : input_zero ? STATE_0_2 : state;
STATE_0_2: state <= input_one ? STATE_1_2 : state;
STATE_1_0: state <= input_one ? STATE_2_0 : input_zero ? STATE_1_1 : state;
STATE_1_1: state <= input_one ? STATE_2_1 : input_zero ? STATE_1_2 : state;
STATE_1_2: state <= input_one ? STATE_2_2 : state;
STATE_2_0: state <= input_zero ? STATE_2_1 : state;
STATE_2_1: state <= input_zero ? STATE_2_2 : state;
STATE_2_2: state <= state;
default: state <= STATE_0_0; // transition out of unused states
endcase
end

// it's a Moore machine so output only depends on current state.

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The lock makes a transition from its current state to a new state whenever one of the three buttons is pressed
and released. It ignores its inputs if more than one button is pressed. Pressing "reset" returns the lock to the
state marked "R" in the diagram (arcs showing the transitions to the reset state have been omitted from the
diagram to make it easier to read). Pressing "0" or "1" will cause the lock to follow the appropriately labeled
transition from its current state. The lock opens if it reaches the state marked "U".

A. After pressing the "reset" button what is the length of the shortest sequence of button presses that will
open the lock?

3 button presses will open the lock: 0, 0, 1.

B. After pressing the "reset" button what is the length of the longest sequence of button presses that will
cause the lock to open after the last button in the sequence is pressed but not open any earlier in the
sequence?

The longest such sequence is unbounded: any number of 0's followed by 111 or 1111 will cause the
lock to open for the first time.

C. After much use, the "reset" button breaks. Is it still possible to open the lock using only the "0" and "1"
buttons assuming you know nothing about the lock's state (except that its locked!) when you start?

Yes. A sequence of 1's will open the lock. You have to try the lock after each press of "1" since a
different number of 1's is required depending on the starting state.

D. Suppose Ben wanted to design a lock that required exactly 10 button presses to open after pressing
"reset". Not counting the "reset" and "unlock" states, what is the minimum number of state his FSM
would need need?

His FSM would need 9 states in addition to "reset" and "unlock".

Problem 6. Stimulated by the idea of FSMs, you have decided to cover MIT's steep tuition costs by selling
simple digital locks based on the following six-state FSM:
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