PUEC3TL02- DIGITAL SYSTEM DESIGN

2 MARKS QUESTION AND ANSWER

UNIT-1
PART A
1. Convert gray code 101011 into its binary equivalent.
Gray Code: 1 0 1 0 1 1 Binary Code: 1 1 0 0 1 0

2. State De Morgan's theorem.

De Morgan suggested two theorems that form important part of Boolean algebra. They are,

1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'

3. Define duality property.

Duality property states that every algebraic expression deducible from the postulates Of Boolean algebra
remains valid if the operators and identity elements are interchanged. If the dual of an algebraic
expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.

4. State the limitations of karnaugh map.

i) Generally it is limited to six variable map (i.e) more then six variable involving expression are not
reduced.

ii) The map method is restricted in its capability since they are useful for simplifying only Boolean
expression represented in standard form

5. What is a prime implicant?

A prime implicant is a product term obtained by combining the maximum possible number of adjacent
squares in the map.? Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical
function.

PART B

1.i) Minimize the term using the Quine-Mc Cluskey method and verify the result using K-
map:πM(0,1,4,11,13,15)+d(5,7,8). (10)

ii) Prove by perfect induction:

o A+AB=AA + AB = AA+AB=A

o A(A+B)=AA(A + B) = AA(A+B)=A

o A+A′B=A+BA + A'B = A + BA+A′B=A+B

2.Simplify the following using tabulation method F (A, B, C, D) = Σm (1, 2, 3, 5, 9, 12, 14, 15) + Σd (4,
8, 11)

3.Given Y=(A,B,C,D) = π M (0,1,3,5,6,7,10,14,15) draw the K-map & obtain the simplified expression.
Realize the minimum expression using gates.

4.Determine the prime implicants of the following function and verify using K map. F(A,B,C,D)= Ʃ
(3,4,5,7,9,13,14,15)

5.Using tabulation method simplify

F (A, B, C, D, E) = ∑(0,1,4,5,16,17,21,25,29)

6.Simplify the following function using tabulation method Y=(A,B,C,D)=∑m〖(0,1,2,5,6,7,8,9,10,14)〗

and implement using only NAND gates

Unit-II

PARTA

1. Define combinational logic

When logic gates are connected together to produce a specified output for certain specified combinations
of input variables, with no storage involved, the resulting circuit is called combinational logic. .

2.Which gates are called as the universal gates?

What are its advantages? The NAND and NOR gates are called as the universal gates. These gates are
used to perform any type of logic application

3.Implement full adder using two half adder.

4. Define half adder and full adder

The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the
addition of three bits is a full adder

5.Mention the Application Of Decoder

1. They can be used to implement combinational logic circuits.

2. It can be used to convert BCD into 7-segment code.

PART B

1.i) Implement a 4 bit binary to gray code converter.

(ii) With truth table and logic diagram, explain the operation of 4 bit priority encoder.

2.Using D flip flops design a synchronous counter which counts in the sequence
000,001,010,011,100,101,110,111,000

3(i)Implement full adder using decoder.

(ii)Realize F(w, x, y, z)= Σ (1,4,6,7,8,9,10,11,15) using 8 to 1 Mux

4.(i). Draw and explain the BCD adder circuit. (10)

(ii). Design a seven segment decoder circuit to display the numbers from 0 to 3. (6)

5.Explain the operation of carry look ahead adder with neat diagram

UNIT-III

PART A

1. Define Flip flop and its types

The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until
directed by an input signal to change its stateThere are various types of flip flops. Some of them are
mentioned below they are, _RS flip-flop _SR flip-flop _D flip-flop _JK flip-flop _T flip-flop

2. What is the operation of SR flip-flop?

When R input is low and S input is high the Q output of flip-flop is set. When R input is high and S input
is low the Q output of flip-flop is reset. When both the inputs R and S are low the output does not
change. When both the inputs R and S are high the output is unpredictable.

.3. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input.
Due to this in the positive half of the clock pulse if both J and K are high then output toggles
continuously. This condition is called ‘race around condition’.

4. What is edge-triggered flip-flop?

The problem of race around condition can solved by edge triggering flip flop. The term edge triggering
means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it
is sensitive to its inputs only at this transition of the clock.

5.Derive the characteristic equation for all flip flops.

Q(t+1) = T'(t)Q(t) + T(t)Q'(t) = T(t) ⊕ Q(t)

Q(t+1) = D(t)

Q(t+1) = K'(t)Q(t) + J(t)Q'(t)

Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0

PART B

1.i)Design a counter for a sequence 1-3-6-5-7 .

ii)Design a Mod 5 Asynchronous counter.

2Design a 4-bit SISO SIPO, PIPO and PISO shift register and draw its wave forms

3.Sequential circuit has three flip flops A, B, and C; one input x_in ; and one output y_out. The state
diagram is shown in below figure. The circuit is to be designed by treating the unused states as don’t care
conditions. Analyze the circuit obtain from the design to determine the effect of the unused states. Use D
flip flops in the design.
4.Explain R-S Flip Flop and Clocked R-S Flip Flop

5.a.Convert it JK Flip Flop in to T Flip Flop b.Convert it JK Flip Flop in to D Flip Flop.

b.Realize a SR flip flop using NAND gates and explain its operation.Realize JK Flip Flop using SR Flip
Flop

UNIT-IV

PART A

1. What are races?

When 2 or more binary state variables change their value in response to a change in an input variable,
race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition
may cause the state variables to change in an unpredictable manner.

2. Define critical race & non critical race.

Final stable state depends on the order in which the state variable changes -race condition is harmful it is
called critical race.If the final stable state that the circuit reaches does not depend on the order in which
the state variable changes, the race condition is not harmful and it is called a non critical race.

3. Write short note on shared row state assignment.

Races can be avoided by making a proper binary assignment to the state variables. Here, the state
variables are assigned with binary numbers in such a way that only one state variable can change at any
one state variable can change at any one time when a state transition occurs. To accomplish this, it is
necessary that states between which transitions occur be given adjacent assignments. Two binary are said
to be adjacent if they differ in only one variable.

4. What is pulse mode asynchronous machine?

A pulse mode asynchronous machine has two inputs. If produces an output whenever two consecutive
pulses occur on one input line only. The output remains at 1 until a pulse has occurred on the other input
line. Write down the state table for the machine

5. What is fundamental mode?

A transition from one stable state to another occurs only in response to a change in the input state. After a
change in one input has occurred, no other change in any input occurs until the circuit enters a stable
state. Such a mode of operation is referred to as a fundamental mode.
PART B

1.Design a clocked synchronous sequential logic circuit using JK flip flops for the following state
diagram. Use state reduction if possible.

2.i.What are static and dynamic hazards? Give static – 0 hazard free realizations for

the following Boolean function. F(A, B, C, D) = ΠM(3, 4, 5, 7, 9, 13, 14, 15).

(ii). Write the design procedure for Asynchronous sequential logic circuits

3.Design an asynchronous sequential circuit with two inputs X & Y and with one output Z. Whenever Y
is 1, input X is transferred to Z. When Y is 0, the output does not change for any change in X.

4.Design an Asynchronous sequential circuit which has 2 inputs x1 and x2 and one output Z . The circuit
is required to give an output whenever the input sequence (0,0) (0,1) and ( 1,1) received but only in that
order.Design it using T flipflops

5.For a given Boolean function obtain the hazard free circuit

F1 ( A,B,C,D ) = ∑m ( 1,3,5,7,8,9,14,15) and

F2 ( A,B,C,D) = ∑m( 0,2,6,7,8,10,12)

6.For a given Boolean function obtain the hazard free circuit

F ( A,B,C,D ) = ∑m ( 1,3,6,7,13,15)
 UNIT-V

PART A

1. Explain PROM.

PROM (Programmable Read Only Memory) It allows user to store data or program. PROMs use the
fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20
to 50 mA of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The
PROMs are one time programmable. Once programmed, the information is stored permanent.

2. What is programmable logic array?

How it differs from ROM? In some cases the number of don’t care conditions is excessive, it is more
economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept;
however it does not provide full decoding of the variables and does not generates all the minterms as in
the ROM.

3.Define power dissipation and propogation delay

The process in which an electric or electronic device produces heat (or other waste energy) as an
unwanted byproduct of its primary action.

Propagation delay is the amount of time required for a signal to be received after it has been sent; it is
caused by the time it takes for the signal to travel through a medium.

4. What is field programmable logic array?

The second type of PLA is called a field programmmable logic array. The user by means of certain
recommended procedures can program the EPLA.

5. List the major differences between PLA and PAL

PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL PAL AND arrays are
programmable OR arrays are fixed Cheaper and Simpler

PART B

1.Implement a PAL using the following Boolean functions.

W(ABCD)=Σ(2,12,13)

X(ABCD)=Σ(7,8,9,10,11,12,13,14,15)

Y(ABCD)=Σ(0,2,3,4,5,6,7,8,10,11,15)

Z(ABCD)=Σ(1,2,8,12,13)
2.Implement the totem pole TTL output configuration circuit and also compare the characteristics of
RTL,TTL,ECL,CMOS LOGIC

3.A combinational circuit is defined by the functions

F1 = Σm(1,3,5) F2 = Σm(5,6,7)

Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs

4.Draw a PLA circuit to implement the function F1 = A’B + AC’,F2 = (AC + AB + BC)’ (8)

ii). Write short notes on EPROM and EEPROM

5.Implement the following Boolean functions using 4 × 3 × 4 PAL

i. W(A, B, C, D) = ∑ (0, 2, 6, 7, 8, 9, 12, 13)

ii. X (A, B, C, D) = ∑ (0, 2, 6, 7, 8, 9, 12, 13, 14).

iii. Y(A, B, C, D) = ∑ ( 2, 3, 8, 9, 10, 12, 13)

iv. Z(A, B, C, D) = ∑ (1, 3, 4, 6, 9, 12, 14)

6.a.Draw a PLA circuit to implement the functions F1=A’B+AC’+A’BC ; F2= (AC+AB+BC)’

b.write a note on FPGA.