EC3058D- VLSI Circuits & Systems

Dhanaraj K. J.
Associate Professor
ECED, NIT Calicut

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 WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

 Replaces pMOS with high resistance resistors.

 Slightly smaller than 6T cell
 Requires an extra high resistance process layer
 Role of resistive load is to replenish the charge lost by leakage.
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 WL
V DD

Q Q
M3 M4

BL M1 M2 BL

 If the loads are eliminated and charge loss is compensated by

periodic rewriting the cell contents, then also it will work.

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 WWL RWL

Q Q
M3 M4

BL1 M2 BL2

 The redundancy due to data complement is removed by removing

one more transistor.

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 No constraints on device ratios
 Reads are non-destructive
 Value stored at node X when writing a “1” = VDD-VTn
 No special process steps needed. Storage capacitance is the gate
capacitance. 5
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 VPRE .C BL + VBIT .CS = (CS + C BL ).VBL

V = VBL − VPRE
= (VBIT − VPRE )
 Write: Cs is charged or discharged by CS
asserting WL and BL CS + C BL
 Read: Charge redistribution takes places Voltage swing is small;
between bit line and storage capacitance typically around 250 mV.
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 1T DRAM requires a sense amplifier for each bit line, due to charge
redistribution read-out.
 DRAM memory cells are single ended in contrast to SRAM cells.
 The read-out of the 1T DRAM cell is destructive; read and refresh
operations are necessary for correct operation.
 Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
 When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the word
lines to a higher value than VDD

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 Latch-up is a problem inherent in the CMOS structure.
 A latch-up is a type of short circuit which can occur in an integrated
circuit (IC).
 It is the creation of a low-impedance path between the power supply
rails of a MOSFET circuit.
 The CMOS structure contains parasitic bipolar junction transistors
that have the potential to destroy the CMOS circuitry.
 Normally these bipolar devices are inactive. However once the chip
go to latch up, in order to restore the chip to unlatched state, power
down is normally required.
 The chip may even be destroyed by heat.
 CMOS designers worry about latch up.

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 The 4 layer structure blocks current flow from the VDD to ground due to
the presence of reverse biased p-n junctions
 If, one of the internal regions (n well or p epi) is electrically shorted,
then we would be left with a forward biased pn junction from the top to
the bottom, indicating a large current flow(exponential)
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  The collector of the pnp is same as
the base of the npn bjt The base of
the pnp is same as the collector of the
npn.
 This leads to coupling providing a
feedback path. The two cross-coupled
common emitter amplifiers forms
positive feedback loop.

 If due to some reason the BJTs turn on and the loop gain is greater
than unity, then a large current flows through these transistors from
VDD to GND (Pull down VDD to approx. 0.9V).
 Then the current flow is through the p+npn+ structure (SCR structure
(Silicon Controlled Rectifier)), not through the intended channels.
Then the expected working of the circuit will not occur.
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 The latched state is sustained as long as the current through SCR is
greater than IH, the holding current value which is determined by the
parasitic resistance in the current path RT.

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 Slewing of VDD: It causes enough current displacement in the
substrate to bias the SCR. Coupling from output side through Cdb.
 Signal swings beyond VDD: Such disturbances happen due to
impedance mismatches in transmission lines.
 Electro Static Discharge (ESD): Injection of minority carriers from
the clamping device.
 Sudden Supply Transients: Simultaneous switching of many drivers
may turn on a BJT in SCR.
 Radiation: It may generate electron-hole pairs and thus trigger the
SCR
 Leakage currents of well junctions can cause large enough lateral
currents.

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 Reduce the beta of either or both parasitic devices. In practice this
can be achieved by increasing the spacing between the devices,
which increases the width of the lateral device. However, such
increased spacing reduces packing density.
 Use p+ guardband rings connected to ground around nMOS
transistors and n+ guard rings connected to VDD around pMOS
transistors to reduce Rwell and Rsub and to capture injected minority
carriers before they reach the base of the parasitic BJTs.

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 Layout n- and p-channel transistors such that substrate and well
contacts as close as possible to the source connections of MOS
transistors to reduce the values of Rwell and Rsub*
 Use minimum area p-wells (in case of twin-tub technology or n-type
substrate) so that the p-well photocurrent can be minimized during
transient pulses.
 Avoid the forward biasing of source/drain junctions so as not to
inject high currents; the use of a lightly doped epitaxial layer on top
of a heavily doped substrate has the effect of shunting lateral
currents from the vertical transistor through the low resistance
substrate.
 The process with VDD less than 0.7volts is immune to Latchup
because BJT never has a large Base to Emitter Vbe to turn ON.

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 SOI (Silicon on Insulator) avoids Latchup entirely because they
have no parasitic bipolar structures.

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 MOSFET scaling is the reduction in dimensions of transistors that
comes with the advancement of technology. This in turn causes
reduction in operational parameters (voltage, current etc)
 Moore's Law states that the number of transistors on a microchip
doubles about every two years
 For what?
◦ To increase packing density of transistors
◦ To get improved performance
◦ Extend of scaling is determined by fabrication technology
◦ Reduction in supply voltage
◦ Scaling factor S>1 (1.2 to 1.5) from one generation to the next

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 Types of scaling
◦ Constant field scaling
◦ Constant voltage scaling
 Scaling Factors
◦ Primary Scaling Factors:
 Channel length (L)
 Oxide layer thickness (tox)
 Width of the transistor (W)
 Doping concentration (NA, ND)
 Supply voltage (VDD)
 Derived Scaling behavior of transistor
◦ Electric field (E))
◦ Drain current (ID)
◦ Capacitance (C)
 Derived Scaling behavior of circuit
◦ Delay (CV/I)
◦ Power (VI)

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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA
ND
Electric field E
Oxide Capacitance Cox=ox/tox
Drain Current ID=(nCox/2)(VGS-Vth)2
Power Dissipation P=VI
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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA S. NA S2NA
ND S.ND S2.ND
Electric field E
Oxide Capacitance Cox=ox/tox
Drain Current ID=(nCox/2)(VGS-Vth)2
Power Dissipation P=VI
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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA S. NA S2NA
ND S.ND S2.ND
Electric field E E S.E
Oxide Capacitance Cox=ox/tox
Drain Current ID=(nCox/2)(VGS-Vth)2
Power Dissipation P=VI
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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA S. NA S2NA
ND S.ND S2.ND
Electric field E E S.E
Oxide Capacitance Cox=ox/tox S.Cox S.Cox
Drain Current ID=(nCox/2)(VGS-Vth)2
Power Dissipation P=VI
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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA S. NA S2NA
ND S.ND S2.ND
Electric field E E S.E
Oxide Capacitance Cox=ox/tox S.Cox S.Cox
Drain Current ID=(nCox/2)(VGS-Vth)2 ID/S S.ID
Power Dissipation P=VI
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Quantity Before Scaling Constant Constant
Field Voltage
scaling Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Gate oxide thickness tox tox/S tox/S

Supply Voltage VDD VDD/S VDD

Threshold Voltage Vth Vth/S Vth
Doping densities NA S. NA S2NA
ND S.ND S2.ND
Electric field E E S.E
Oxide Capacitance Cox=ox/tox S.Cox S.Cox
Drain Current ID=(nCox/2)(VGS-Vth)2 ID/S S.ID
Power Dissipation P=VI P/S2 S.P
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 Many issues may arise if S is chosen to be very large
 Short channel device –if the channel length is of the same order of
depletion region thickness of source and drain junctions.
 Major effects:
◦ Velocity saturation
◦ Mobility degradation
◦ Threshold voltage variation
◦ Drain induced barrier lowering(DIBL)
◦ Subthreshold conduction
◦ Punch through
◦ Hot carrier effects

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 Occurs under constant-voltage scaling
 As channel length decreases the channel electric field increases

 We had already discussed its effects in the performance of

MOSFETs

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 In short-channel MOSFETs, the normal component of electric field
will be also very large.
 The normal field influences the scattering of carrier in the surface
region.
 Surface mobility reduced with respect to bulk mobility.
 Scattering due to :
◦ surface roughness
◦ columbic interaction with fixed charges in gate oxide
 Estimate of surface mobility:

 As 𝑉𝐺𝑆 increases, the surface mobility decreases ⇒channel current

decreases.
 Degradation in the overall performance of digital circuits.
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 In long-channel MOSFETs:
◦ source and drain pn junction depletion regions are neglected
◦ channel is assumed to be rectangular
 In short-channel MOSFETs:
◦ channel has trapezoidal shape, so bulk depletion charge is reduced
◦ threshold voltage is less than that calculated by long channel equation
 𝑉𝑇0(short channel) = 𝑉𝑇0−Δ𝑉𝑇0

 Effects of threshold voltage reduction in digital circuits:

◦ increased static power dissipation
◦ decreased propagation delay
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 In Long Channel devices,
◦ If 𝑉𝐺𝑆< 𝑉𝑇0, the carriers in the channel faces a potential barrier
◦ Increasing 𝑉𝐺𝑆 reduces the barrier
 In short-channel devices,
◦ this barrier is reduced as 𝑉𝐷𝑆 is increased since increasing 𝑉𝐷𝑆 decreases
𝑉𝑇0.

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 The reduction of the potential barrier eventually allows electron flow
between the source and the drain, even if the gate-to-source voltage
is lower than the threshold voltage.
 The channel current that flows under these conditions (𝑉𝐺𝑆<𝑉𝑇) is
called the sub threshold current.
 Sub threshold conduction is very important for circuit applications
where small amounts of current flow may significantly disturb the
circuit operation.
 We had already discussed its effects in the performance of
MOSFETs

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 In small geometry MOSFETs
◦ channel length (order) ≈ source & drain depletion region thickness
 For large drain-bias voltages, the depletion region surrounding the
drain can extends farther toward the source, and the two depletion
regions eventually merges.

 Gate loses control over 𝐼𝐷and current rises sharply

 Cause permanent damage to transistor.

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 Decrease in critical device dimensions to submicron ranges and
increase substrate doping densities, results in a significant increase
of the horizontal and vertical electric fields in the channel region.

 In high electric fields carriers gains high kinetic energies (hot

carriers)
 these normally appear close to the drain, where they have the most
energy.

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 Hot carriers traveling through a Silicon lattice
◦ possibility that they collide with an atom of the structure
◦ the energy passed to the atom upon collision originates an electron-hole
pair
◦ the hole is attracted to the bulk while the generated electron moves on to
the drain
 The substrate current is a good way to measure the impact
ionization effect.

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1. Jan M Rabaey, Digital Integrated Circuits - A Design Perspective,
Prentice Hall, 2nd Edition, 2005
2. Kang, S.M. and Leblebici, Y., 2003. CMOS digital integrated
circuits. Tata McGraw-Hill Education.

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 Thank You
Wish You All The Best

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