EC3058D- VLSI Circuits & Systems

Dhanaraj K. J.
Associate Professor
ECED, NIT Calicut

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 R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

 The contamination (minimum) delay tc-q,cd, and maximum

propagation delay of the register tc-q.
 The set-up (tsu) and hold time (thold) for the registers
 The contamination delay tlogic,cd and maximum delay tlogic of the
combinational logic.
 tclk1 and tclk2, corresponding to the position of the rising edge of the
clock relative to a global reference.

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 R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
Under ideal conditions tclk1 = tclk2, tsu, thold

T > tc – q + tlogic + tsu

The period must be long enough for the data to propagate through the registers
and logic and be set-up at the destination register before the next rising edge of
the clock.

thold < tc – q, cd + tlogic, cd

The hold time of the destination register must be shorter than the minimum
propagation delay through the logic network.

However, as a result of process and environmental variations, the clock signal

can have spatial and temporal variations

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 tc-q,cd, tc-q, tsu and thold of R1are 200ps,
In
R1
Combinational
R2 220ps, 400ps and 80ps respectively. For
D Q D Q R2 the corresponding values are 100ps,
Logic

tCLK1 tCLK2 120ps, 180ps and 50ps. If the tlogic,cd and

CLK
tlogic of the combinational logic are 50ps
tc - q tlogic
tc - q, cd tlogic, cd and 100ps, check whether the circuit will
tsu, thold work properly? What is the maximum
operating frequency of the CLK?
t hold R 2 = 50 ps
tc − q ,cd R1 + tlogic ,cd = 200 ps + 50 ps
Tmin = tc − qR1 + tlogic + t su R 2
= 250 ps
t hold R 2 < tc − q ,cd R1 + tlogic ,cd = 220 ps + 100 ps + 180 ps
= 500 ps
f max = 2GHz
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 The spatial variation in arrival time of a clock transition on an
integrated circuit is commonly referred to as clock skew.
 The clock skew between two points i and j on a IC is given by δ (i,j)
= ti- tj, where ti and tj are the position of the rising edge of the clock
with respect to a reference.

R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

Clock skew is caused by static path-length mismatches in the clock load and
by definition skew is constant from cycle to cycle. That is, if in one cycle
CLK2 lagged CLK1 by δ, then on the next cycle it will lag it by the same
amount. It is important to note that clock skew does not result in clock period
variation, but rather phase shift.
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 R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold
T+T >> tc – q + tlogic + tsu

T > tc – q + tlogic + tsu -

 < tc – q, cd + tlogic, cd
thold t+hold

 < tc – q, cd + tlogic, cd - thold

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 Clock jitter refers to the temporal variation of the clock period at a
given point — that is, the clock period can reduce or expand on a
cycle-by-cycle basis
 It is strictly a temporal uncertainty measure and is often specified at
a given point on the chip. Jitter can be measured and cited in one of
many ways.
 Cycle-to-cycle jitter refers to time varying deviation of a single clock
period and for a given spatial location i is given as Tjitter,i(n) = Ti, n+1 -
Ti,n - TCLK, where Ti,n is the clock period for period n, Ti, n+1 is clock
period for period n+1, and TCLK is the nominal clock period.

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 T -2tjitter > tc – q + tlogic + tsu

T > tc – q + tlogic + tsu + 2tjitter

Jitter directly reduces the performance of a sequential circuit.

Care must be taken to reduce jitter in the clock network to maximize
performance
t hold < tc − q ,cd + tlogic.cd

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 T +  − t jitter1 − t jitter 2  tc − q + tlogic + t su
T  tc − q + tlogic + t su −  + t jitter1 + t jitter 2
jitter has a negative impact on the minimum clock period

 + t hold + t jitter1 + t jitter 2 < tc − q ,cd + tlogic.cd

 < tc − q ,cd + tlogic.cd − t hold − t jitter1 − t jitter 2

The acceptable skew is reduced by the jitter of the two signals.

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1. Jan M Rabaey, Digital Integrated Circuits - A Design Perspective,
Prentice Hall, 2nd Edition, 2005
2. Kang, S.M. and Leblebici, Y., 2003. CMOS digital integrated
circuits. Tata McGraw-Hill Education.

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Thank You

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