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ch2 Notes

The document explains the concepts of Half Adder and Full Adder circuits, detailing their components, logical expressions, and truth tables. It also introduces multiplexers and demultiplexers, highlighting their functions, structures, and operational principles, particularly focusing on the 4×1 multiplexer and 1×4 demultiplexer. Each component is defined with its respective logical operations and truth tables to illustrate their functionality in digital circuits.

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5 views7 pages

ch2 Notes

The document explains the concepts of Half Adder and Full Adder circuits, detailing their components, logical expressions, and truth tables. It also introduces multiplexers and demultiplexers, highlighting their functions, structures, and operational principles, particularly focusing on the 4×1 multiplexer and 1×4 demultiplexer. Each component is defined with its respective logical operations and truth tables to illustrate their functionality in digital circuits.

Uploaded by

sarthakmhatre21m
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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What is Half Adder?

Half Adder is a combinational logic circuit that is designed by connecting


one EX-OR gate and one AND gate. The half-adder circuit has two inputs: A and
B, which add two input digits and generate a carry and a sum.

The output obtained from the EX-OR gate is the sum of the two numbers while
that obtained by AND gate is the carry. There will be no forwarding of carry
addition because there is no logic gate to process that. Thus, this is called the Half
Adder circuit.
Logical Expression of Half Adder
The Logical Expression for half added is given as
Sum = A ⊕ B
Carry = A AND B
Truth Table of Half Adder
The Truth Table for Half Added is Given as
What is Full Adder ?
Full Adder is the circuit that consists of two EX-OR gates, two AND gates, and
one OR gate. Full Adder is the adder that adds three inputs and produces two
outputs which consist of two EX-OR gates, two AND gates, and one OR gate.
The first two inputs are A and B and the third input is an input carry as C-IN. The
output carry is designated as C-OUT and the normal output is designated as S
which is SUM.

The equation obtained by the EX-OR gate is the sum of the binary digits. While
the output obtained by AND gate is the carry obtained by addition.
Logical Expression of Full Adder
Given Below is the Logical Expression of Full Adder
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
Truth Table of Full Adder Given Below is the truth Table of Full Adder

Sum and Carry Operation


In both Half Adders and Full Adders, Sum is the output of the addition of the two
inputs and Carry is the output which is an overflow of the output position and needs
to be shifted to the next higher position while adding successive bit inputs.
 Sum (S) : It results from the XOR gate, which is a logic gate that adds two or
more bits together in the same way that you add in base 2 with no
acknowledgement of carry from the previous bit.
 Carry (C or Cout): It is the output of the AND operation in the case of the
Half Adder or both AND and OR Operations in the case of the Full Adder to
indicate that a ‘1’ has to be carried over to the next bit position.

What Are Multiplexers?


A multiplexer is a combinational circuit that has many data inputs and a single
output, depending on control or select inputs. For N input lines, log2(N) selection
lines are required, or equivalently, for 2n2n input lines, n selection lines are
needed. Multiplexers are also known as “N-to-1 selectors,” parallel-to-serial
converters, many-to-one circuits, and universal logic circuits. They are mainly
used to increase the amount of data that can be sent over a network within a
certain amount of time and bandwidth .

4×1 Multiplexer
The 4×1 Multiplexer which is also known as the 4-to-1 multiplexer. It is a
multiplexer that has 4 inputs and a single output. The Output is selected as one of
the 4 inputs which is based on the selection inputs. The number of the Selection
lines will depend on the number of the input which is determined by the
equation log2nlog2n ,In 4×1 Mux the selection lines can be determined
as log4=2log4=2 ,slo two selections are needed.

Block Diagram of 4×1 Multiplexer


In the Given Block Diagram I0, I1, I2, and I3 are the 4 inputs and Y is the Single
output which is based on Select lines S0 and S1.

The output of the multiplexer is determined by the binary value of the selection
lines
 When S1S0=00, the input I0 is selected.
 When S1S0=01, the input I1 is selected.
 When S1S0=10, the input I2 is selected.
 When S1S0=11, the input I3 is selected.
Truth Table of 4×1 Multiplexer
Given Below is the Truth Table of 4×1 Multiplexer
Circuit Diagram of 4×1 Multiplexers
Using truth table the circuit diagram can be given as

What is a Demultiplexer?

A Demultiplexer is a combinational logic circuit that accepts a single input and


distributes it over several output lines. Demultiplexer is also termed as DEMUX in
short. As Demultiplexer is used to transmit the same data to different destinations,
hence it is also known as data distributor.

There is another combinational logic circuit named multiplexer which performs


opposite operation of the Demultiplexer, i.e. accepts several inputs and transmits
one of them at time to the output line.

From the definition, we can state that a Demultiplexer is a 1-to-2n device. The
functional block diagram of a typical 1×2n Demultiplexer is shown in Figure-1.
It can be seen that the Demultiplexer has only one data input line, 2n output lines,
and n select lines. The logic level applied to select lines of the Demultiplexer
determines the output channel to which the input data will be transmitted.

Demultiplexer circuit are the combinational logic circuit widely used in digital
decoders and Boolean function generator circuits.

1×4 Demultiplexer

The functional block diagram of 1×4 Demultiplexer is shown in Figure-3.

The 1×4 Demultiplexer has 1 input line (I), 2 select line (S0 and S1), and 4 output
lines (Y0, Y1, Y2, and Y3). The logic level applied to the select lines determines the
output line to which the input data (I) will be transmitted.

The operation of the 1×4 Demultiplexer can be understood with the help of its
function table given below.

Select Line Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0
From this truth table of 1×4 Demultiplexer, we can directly write the Boolean
expression for each output as follow.

Y0=S1¯S0¯IY0=S1¯S0¯I
Y1=S1¯S0IY1=S1¯S0I
Y2=S1S0¯IY2=S1S0¯I
Y3=S1S0IY3=S1S0I

We can easily understand the operation of the above circuit.

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