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AM26LV31E
SLLS848B – APRIL 2008 – REVISED SEPTEMBER 2016

AM26LV31E Low-Voltage High-Speed Quadruple Differential Line Driver

With ±15-kV IEC ESD Protection
1 Features 3 Description
1• Meets or Exceeds Standards TIA/EIA-422-B and The AM26LV31E is a quadruple differential line driver
ITU Recommendation V.11 with 3-state outputs. This driver has ±15-kV ESD
(HBM and IEC61000-4-2, Air-Gap Discharge) and
• Operates From a Single 3.3-V Power Supply ±8-kV ESD (IEC61000-4-2, Contact Discharge)
• ESD Protection for RS422 Bus Pins protection. This device is designed to meet
– ±15-kV Human-Body Model (HBM) TIA/EIA-422-B and ITU Recommendation V.11
drivers with reduced supply voltage.
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge The device is optimized for balanced-bus
transmission at switching rates up to 32 MHz. The
• Switching Rates Up to 32 MHz outputs have high current capability for driving
• Propagation Delay Time: 8 ns Typical balanced lines, such as twisted-pair transmission
• Pulse Skew Time: 500 ps Typical lines, and provide a high impedance in the power-off
condition.
• High Output-Drive Current: ±30 mA
• Controlled Rise and Fall Times: 5 ns Typical The AM26LV31EI is characterized for operation from
–40°C to +85°C.
• Differential Output Voltage With 100-Ω
Load: 2.6 V Typical Device Information(1)
• Accepts 5-V Logic Inputs With 3.3-V Supply PART NUMBER PACKAGE BODY SIZE (NOM)
• Ioff Supports Partial-Power-Down Mode Operation AM26LV31EID SOIC (16) 9.90 mm × 3.91 mm
• Driver Output Short-Protection Circuit AM26LV31EINS SO (16) 10.30 mm × 5.30 mm
• Glitch-Free Power-Up and Power-Down Protection AM26LV31EIPW TSSOP (16) 5.00 mm × 4.40 mm
• Package Options: SO, SOIC, TSSOP, VQFN AM26LV31EIRGY VQFN (16) 4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.

• Motor Drives
• Space Avionics and Defense
• Medical Healthcare and Fitness
• Wireless Infrastructure
• Factory Automation and Control
Logic Diagram
4
G
12
G 2
1 1Y
1A 3
1Z
6
7 2Y
2A 5
2Z
10
9 3Y
3A 11
3Z
14
15 4Y
4A 13
4Z
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26LV31E
SLLS848B – APRIL 2008 – REVISED SEPTEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 10
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 9 Application and Implementation ........................ 12
4 Revision History..................................................... 2 9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 14
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 14
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 14
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 14
6.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 15
6.5 Electrical Characteristics........................................... 5 12.1 Documentation Support ........................................ 15
6.6 Switching Characteristics .......................................... 6 12.2 Receiving Notification of Documentation Updates 15
6.7 Typical Characteristics .............................................. 6 12.3 Community Resource............................................ 15
7 Parameter Measurement Information .................. 7 12.4 Trademarks ........................................................... 15
12.5 Electrostatic Discharge Caution ............................ 15
8 Detailed Description ............................................ 10
12.6 Glossary ................................................................ 15
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10 13 Mechanical, Packaging, and Orderable
Information ........................................................... 15

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2008) to Revision B Page

• Added Applications section, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the datasheet.. 1
• Changed ESD PROTECTION to ESD Ratings table ............................................................................................................. 4
• Changed RθJA for PW package from 108°C/W: to 99.5°C/W ................................................................................................. 5
• Changed RθJA for NS package from 64°C/W: to 74.5°C/W .................................................................................................... 5
• Changed RθJA for RGY package from 39°C/W: to 39.3°C/W ................................................................................................. 5

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5 Pin Configuration and Functions

D, NS, or PW Package
16-Pin SOIC, SO, TSSOP RGY Package
Top View 16-Pin VQFN With Thermal Pad
Top View

VCC
1A
1A 1 16 VCC

1Y 2 15 4A

16
1Z 3 14 4Y
1Y 2 15 4A
G 4 13 4Z
1Z 3 14 4Y
2Z 5 12 G
G 4 Thermal 13 4Z
2Y 6 11 3Z Pad
2Z 5 12 G
2A 7 10 3Y
2Y 6 11 3Z
GND 8 9 3A
2A 7 10 3Y

9
Not to scale

Not to scale

GND

3A
Pin Functions
PIN
SOIC, SO, I/O DESCRIPTION
NAME
TSSOP, VQFN
1A 1 I Logic data input to RS422 driver 1
1Y 2 O RS-422 data line for driver 1
1Z 3 O RS-422 data line for driver 1
2A 7 I Logic data input to RS422 driver 2
2Y 6 O RS-422 data line for driver 2
2Z 5 O RS-422 data line for driver 2
3A 9 I Logic data input to RS422 driver 3
3Y 10 O RS-422 data line for driver 3
3Z 11 O RS-422 data line for driver 3
4A 15 I Logic data input to RS422 driver 4
4Y 14 O RS-422 data line for driver 4
4Z 13 O RS-422 data line for driver 4
G 4 I Driver enable (active high)
G 12 I Driver enable (active low)
GND 8 — Device ground pin
VCC 16 — Power input (5 V)

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) –0.5 6 V
VI Input voltage –0.5 6 V
VO Output voltage –0.5 6 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
lO Continuous output current ±150 mA
Continuous current through VCC or GND ±200 mA
TJ Operating virtual junction temperature 150 °C
TA Operating free-air temperature –40 85 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential input voltage are with respect to the network GND.

6.2 ESD Ratings

VALUE UNIT
Bus pins 2, 3, 5, 6, 10, 11, 13, and 14 ±15000
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
All pins except 2, 3, 5, 6, 10, 11, 13, and 14 ±2000
Electrostatic
V(ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
discharge
IEC 61000-4-2 contact discharge Bus pins 2, 3, 5, 6, 10, 11, 13, and 14 ±8000
IEC 61000-4-2 air-gap discharge Bus pins 2, 3, 5, 6, 10, 11, 13, and 14 ±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VI Input voltage 0 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –30 mA
IOL Low-level output current 30 mA
TA Operating free-air temperature –40 85 °C

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6.4 Thermal Information

AM26LV31E
THERMAL METRIC (1) D (SOIC) PW (TSSOP) NS (SO) RGY (VQFN) UNIT
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 73.0 99.5 74.5 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.8 34.9 31.6 31.9 °C/W
RθJB Junction-to-board thermal resistance 31.0 44.4 35.3 14.8 °C/W
ψJT Junction-to-top characterization parameter 5.1 2.4 5.3 0.4 °C/W
ψJB Junction-to-board characterization parameter 30.7 43.8 35.0 14.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a 3.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VOH High-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = –20 mA 2.4 3 V
VOL Low-level output voltage VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.2 0.4 V
|VOD1| Differential output voltage IO = 0 mA 2 4 V
|VOD2| Differential output voltage RL = 100 Ω (see Figure 3) 2 2.6 V
Change in magnitude of
Δ|VOD| RL = 100 Ω (see Figure 3) ±0.4 V
differential output voltage
VOC Common-mode output voltage RL = 100 Ω (see Figure 3) 1.5 2 V
Change in magnitude of
Δ|VOC| RL = 100 Ω (see Figure 3) ±0.4 V
common-mode output voltage
IO(OFF) Output current with power off VCC = 0, VO = –0.25 V or 5.5 V ±100 μA
IOZ High-impedance state output current VO = –0.25 V or 5.5 V, G = 0.8 V or G = 2 V ±100 μA
II Input current VCC = 0 or 3.6 V, VI = 0 or 5.5 V ±10 μA
IOS Short-circuit output current VO = VCC or GND (2) –30 –150 mA
ICC Supply current (total package) VI = VCC or GND, No load, enable 100 μA
Cpd Power dissipation capacitance No load (3) 160 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
(3) Cpd determines the no-load dynamic current consumption. IS = Cpd × VCC × f + ICC

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6.6 Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
tPHL Propagation delay time, high- to low-level output 4 8 12 ns
See Figure 4
tPLH Propagation delay time, low- to high-level output 4 8 12 ns
tt Transition time (tr or tf) See Figure 4 5 10 ns
tPZH Output-enable time to high level See Figure 5 10 20 ns
tPZL Output-enable time to low level See Figure 6 10 20 ns
tPHZ Output-disable time from high level See Figure 5 10 20 ns
tPLZ Output-disable time from low level See Figure 6 10 20 ns
tsk(p) Pulse skew 0.5 1.5 ns
tsk(o) Skew limit (pin to pin) See Figure 4 (2) (3) 1.5 ns
tsk(lim) Skew limit (device to device) 3 ns
f(max) Maximum operating frequency See Figure 4 32 MHz

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
(3) Skew limit (device to device) is the maximum difference in propagation delay times between any two channels of any two devices.

6.7 Typical Characteristics

Figure 1 and Figure 2 below show typical ICC values at various frequencies/data rates for various termination
conditions.

300 300
100 Ohms 1000pF 100 Ohms 1000pF
100 Ohms 100pF 100 Ohms 100pF
250 100 Ohms 250 100 Ohms
No termination No termination
200 200
ICC (mA)

ICC (mA)

150 150

100 100

50 50

0 0
0.0001 0.001 0.01 0.1 1 10 50 0.0001 0.001 0.01 0.1 0.5 2 3 5 10 20 100
Frequency (MHz) D001
Data Rate (Mbps) D001
Figure 1. ICC vs. Frequency Figure 2. ICC vs. Data Rate

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7 Parameter Measurement Information

RL/2

VOD

VOC
RL/2

Figure 3. Test Circuit, VOD and VOC

C2 = 40 pF
Y
Input C1 = 40 pF RL = 100 Ω
C3 = 40 pF
Z

See Note A

VCC
Input 50% 50%
A 0V

tPLH tPHL
Z
Output, V O
Y

PROPAGATION DELAY TIMES

VOH
90% 90%
10% 10% VOL
Y
tr tf
Output, V O
tf tr
Z VOH
90% 90%
10% 10%
VOL
RISE AND FALL TIMES

NOTES: A. CL includes probe and jig capacitance.

B.
tr and tf ≤ 2 ns.

Figure 4. Test Circuit and Voltage Waveforms, tPHL and tPLH

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Parameter Measurement Information (continued)

S1
Y
A
VCC Z Output

CL = 40 pF RL = 110 Ω
(see Note A)

G
Generator G
(see Note B) 50 Ω

VCC
(see Note C)
TEST CIRCUIT

VCC
Input 50% 50%
0V

tPHZ
tPZH

0.3 V

VOH
Output 50%
Voff ≈ 0
VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. r and tf ≤ 2 ns.
C. To test the active-low enable G, ground G and apply an inverted waveform to G.

Figure 5. Test Circuit and Voltage Waveforms, tPZH and tPHZ

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Parameter Measurement Information (continued)

VCC

S1 RL = 110 Ω
Y
A
VCC Z Output

CL = 40 pF
(see Note A)

G
Generator G
(see Note B) 50 Ω

VCC
(see Note C)
TEST CIRCUIT

VCC
Input 50% 50%
0V

tPLZ
tPZL

Voff ≈ VCC
Output 50%
VOL

VOLTAGE WAVEFORMS 0.3 V

NOTES: A. CL includes probe and jig capacitance.

B. r and tf ≤ 2 ns.
C. To test the active-low enable G, ground G and apply an inverted waveform to G.

Figure 6. Test Circuit and Voltage Waveforms, tPZL and tPLZ

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8 Detailed Description

8.1 Overview
The AM26LV31E is a quadruple differential line driver with 3-state outputs. The device is designed to meet
TIA/EIA-422-B and ITU Recommendation V.11 drivers with reduced supply voltage. The high current capability of
the outputs allow for driving balanced lines, such as twisted-pair transmission lines, and proved a high
impedance in the power-off condition. The AM26LV31E is optimized for balanced-bus transmission line at
switching rates up to 32 MHz.
From a single 3.3-V power supply, the device operates four 3-state differential line drivers with integrated active
high and active low enables for precise control. The device is capable of accepting 5-V logic inputs with a 3.3-V
supply. The driver is designed to handle loads of a minimum of ±30 mA of sink or source current.

8.2 Functional Block Diagram

4
G
12
G 2
1 1Y
1A 3
1Z
6
7 2Y
2A 5
2Z
10
9 3Y
3A 11
3Z
14
15 4Y
4A 13
4Z
Copyright © 2016, Texas Instruments Incorporated

Figure 7. Logic Diagram

8.3 Feature Description

8.3.1 Complementary Out-Enable Inputs
The AM26LV31E transmitter outputs can be configured using the G and G logic inputs. The transmitter outputs
are enabled when either G is set to logic HIGH or G is set to logic LOW. The reverse disables the outputs
(G = LOW, G = HIGH). See Table 1 for the complete truth table.

8.3.2 High Output Impedance for Specific Driver Enable Inputs

When the AM26LV31E transmitter outputs are disabled using G and G logic inputs, the outputs are set to a high
impedance state.

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8.4 Device Functional Modes

Table 1 lists the functional modes of the AM26LV31E.

Table 1. Function Table (1)

INPUT ENABLES OUTPUTS
A G G Y Z
H H X H L
L H X L H
H X L H L
L X L L H
X L H Z Z

(1) H = high level, L = low level, X = irrelevant,

Z = high impedance (off)

SPACE
SPACE
VCC VCC

Output

Input

GND

GND

Figure 8. Equivalent of Each Input (A, G, or G) Figure 9. Typical of Each Driver Output Schematic
Schematic

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of the
cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors to
consider when determining the type of termination usually are performance requirements of the application and
the ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,
parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and indirectly, RS-
xxxxxxxxxxxxxx
485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26LV31E and AM26LV32E, respectively, were tested at room temperature with a 3.3-V supply
voltage. To show voltage waveforms related to transmission-line reflections, the first plot shows output
xx
waveforms from the driver at the start of the cable (A/B); the second plot shows input waveforms to the receiver
at the far end of the cable (Y).
x
x
x
9.2 Typical Application
x xx
x x x x xx
x

x x
x
x

Servo Drive Motion Controller

A
Encoder D R Encoder Phase A
B
Interpolation
Electronics Z
D R Encoder Phase B

D R Encoder Index

Status
D R Status

AM26LV31E AM26LV32E

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Figure 10. Encoder Application

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Typical Application (continued)

9.2.1 Design Requirements
This example requires the following:
• 3.3-V power source
• RS-485 bus operating at speed compatible with cable length
• Connector that ensures the correct polarity for port pins

9.2.2 Detailed Design Procedure

Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus
line. If desired, add external fail-safe biasing to ensure 200 mV on the A-B port, if the drive is in high
impedance state (see Failsafe in RS-485 data buses, SLYT080).

9.2.3 Application Curve

5

2
Voltage (V)

±1

±2
Y A/B
±3
0 0.1 0.2 0.3 0.4 0.5
Time ( s) C001

Figure 11. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)

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10 Power Supply Recommendations

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can often propagate into analog circuitry through the power supply of the circuit. Bypass capacitors are
used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.

11.2 Layout Example

For all Y and Z outputs, make sure the traces are impedance matched to cable used.
Differential
Output 1
Input 1 0.1 PF

VCC

1 1A VCC 16

2 1Y 4A 15

3 1Z 4Y 14

4 G 4Z 13
AM26LV31E
Active Low
5 2Z G 12
Differential Enable
Output 2
6 2Y 3Z 11

Input 2 7 2A 3Y 10

8 GND 3A 9

Figure 12. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
Failsafe in RS-485 data buses, SLYT080

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AM26LV31EIDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26LV31EI

AM26LV31EIDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26LV31EI

AM26LV31EINSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26LV31EI

AM26LV31EIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB31

AM26LV31EIPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB31

AM26LV31EIRGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SB31

AM26LV31EIRGYRG4 ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SB31

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AM26LV31E :

• Enhanced Product : AM26LV31E-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM26LV31EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV31EINSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26LV31EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26LV31EIRGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26LV31EIDR SOIC D 16 2500 356.0 356.0 35.0
AM26LV31EINSR SO NS 16 2000 367.0 367.0 38.0
AM26LV31EIPWR TSSOP PW 16 2000 367.0 367.0 35.0
AM26LV31EIRGYR VQFN RGY 16 3000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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