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ASIC (Application Specific Integrated Circuit)

These circuits are application specific .i.e. tailored made ICs for a particular application.
These are usually designed from root level based on the requirement of the particular
application. Some of the basic application-specific integrated circuit examples are chips used
in toys, the chip used for interfacing of memory and microprocessor etc…These chips can be
used only for that one application for which these are designed. Presumably, these types of
ICs are preferred only for those products which have a large production run. As ASICs are
designed from the root level they have high cost and are recommended only for high volume
productions.

The main advantage of ASIC is reduced chip size as a large number of functional units of a
circuit are constructed over a single chip. Modern ASIC generally includes a 32-
bit microprocessor, memory blocks, network circuits etc…Such type of ASICs is known
as System on Chip. With the development in manufacturing technology and increased
research in design methods, ASICs with different levels of customization are developed.

1.Types of ASIC
ASICs are categorized based on the amount of customization a programmer is allowed to do
on a chip.

Figure.1. Types of ASICs

1.1. FULL CUSTOM
In this type of design all the logic cells are tailored made for specific application .i.e. designer
has to specially make the logic cells for the circuits. All the mask layers for interconnection
are customized. So programmer can’t change interconnections of the chip and while
programming he has to be aware of the circuit layout.

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One of the best examples of Full custom ASIC is a microprocessor. This type of
customization allows designers to built various analog circuits, optimized memory cells, or
mechanical structures on a single IC. This ASIC is costly and very time consuming to
manufacture and design. The time is taken to design these ICs is around eight weeks.

These are usually intended for high-level applications. Maximum performance, minimized
area and highest degree of flexibility are major features of Full custom design. Eventually,
the risk is high in design as the logic cells, resistor etc… circuit elements used are not
pretested.

1.2.SEMI-CUSTOM
In this type of design logic cells are taken from standard libraries .i.e. they are not
handcrafted as in Full custom design. Some masks are customized while some are taken from
the predesigned library. Based on the type of logic cells taken from the library and amount of
customization allowed for interconnects these ASICs are divided into two types- Standard
cell-based ASIC and Gate Array-based ASIC.

1.2.1 Standard cell-based ASIC

To know these IC first let us understand what a standard cell library stands for. Some of the
logic cells such as AND gates, OR gates, multiplexers, flip-flops are predesigned by
designers using different configurations, standardized and stored in the form of a library. This
collection is known as standard cell library.

Figure.2. Standard Cell-based ASIC

In standard cell-based, ASIC logic cells from these standard libraries are used. On the ASIC
chip standard cell area or flexible block are made up of standard cells arranged in the form of
rows. Along with these flexible blocks mega cells like microcontrollers or even
microprocessors are used on-chip. These mega cells are also known as Mega functions,
system level macros, fixed blocks, Functional standard blocks.

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Above figure represents a standard cell ASIC with a single standard cell area and four fixed
blocks. Mask layers are customized. Here designer can place standard cells anywhere on the
die. These are also known as C-BIC.

1.2.2 Gate Array Based ASIC

This type of semi-custom ASIC have predefined transistors on the silicon wafer .i.e. the
designer cannot change the placement of the transistors present on the die. Base array is the
predefined pattern of the gate array and the base cell is the smallest repetitive cell of the base
array.
The designer only has liability to change interconnection between transistors using the first
few metal layers of the die. The designer chooses from the gate array library. These are often
called as Masked Gate Array. Gate Array Based ASIC are of three types. They are Channeled
Gate Array, Channel less gate array and a structured gate array.

1.2.2.1. Channeled Gate Array

In this type of gate array, wiring space is left between rows of transistors. These are similar to
CBIC as space is left for interconnection between blocks but in channeled gate array cell
rows are fixed in height whereas in CBIC this space can be adjusted.

Channelled Gate Array

Some of the main features of this gate array are- this gate array uses predefined spaces
between rows for interconnection. Manufacturing time is two days to two weeks.

1.2.2.2. Channel Less Gate Array

There is no free space left for routing between rows of cells as seen in the channeled gate
array. Here routing is done from above the gate array cells as we can customize the
connection between the metal 1 and transistors. For routing, we leave the transistors lying in
the path of routing unused. The manufacturing lead time is about two weeks.

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 Channel Less Gate Array
1.2.2.3. Structured Gate Array
This type of gate array has an embedded block along with gate array rows as seen above.
Structured gate array has a higher area efficiency of CBIC. Like Masked gate array these
have lower cost and faster turnaround. Here the fixed size of the embedded function poses a
limitation on the structured gate array. For example, is this gate array contains an area
reserved for 32k bit controller but if in an application we only require an area for 16k bit
controller the remaining area gets wasted.All the gate array have a turnaround time of two
days to two weeks and all have customized interconnect.

Structured Gate Array

1.3. PROGRAMMABLE ASIC

There are two types of programmable ASICs. They are PLD and FPGA

1.3.1. PLDs (Programmable Logic Devices)

These are the standard cells readily available. We can program a PLD to customized a part of
the application, so they are considered as ASIC. We can use different methods and software

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to program a PLD. These contain a regular matrix of logic cells usually programmable array
logic along with flip-flops or latches. Here interconnects are present as a single large block.
PROM is a common example of this IC. EPROM uses MOS transistors as interconnect so by
applying high voltage we can program it. PLDs have no customized logic cells or
interconnect. These have a fast design turnaround.

Programmable Logic
Devices

1.3.1. FPGAs (Field Programmable Gate Array)

Where PLDs have programmable array logic as logic cells FPGA has gate array-like
arrangement. PLDs are smaller and less complex than FPGAs. Due to its flexibility and
characteristics, FPGA is replacing TTL in microelectronic systems. Design turnaround is
only a few hours.

Field Programmable Gate Array

The core consists of programmable basic logic cells which can perform both combinational
and sequential logic. We can program logic cells and interconnect using some methods. Basic
logic cells are surrounded by the matrix of programmable interconnects and the core is
surrounded by programmable I/O cells.
FPGA usually comprises of configurable logic blocks, configurable I/O blocks,
programmable interconnects, clock circuitry, ALU, memory, decoders.

2.Application Specific Integrated Circuit (ASIC) Design Flow

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Designing an ASIC is carried out in step by step manner. This order of steps is known
as ASIC Design Flow. Steps of design flow are given in below flow chart.

ASIC Design Flow

 Design Entry: At this step, the micro architecture of the design is implemented using
hardware description languages such as VHDL, Verilog and System Verilog.
 Logic Synthesis: At this step a netlist of logic cells to be used, types of
interconnections and all other parts required for the application is prepared using
HDL.
 System Partitioning: At this step, we divide the largely sized die into ASIC sized
pieces.
 Pre-Layout Simulation: At this step, a simulation test is done to check whether the
design contains any errors.
 Floor Planning: At this step blocks of netlist are arranged on the chip.
 Placement: At this step location of cells inside the block is decided.
 Routing: At this step, connections are drawn between blocks and cells.
 Extraction: At this step, we determine the electrical properties like resistance value
and the capacitance value of interconnect.
 Post-Layout Simulation: Before the submission of the model for manufacturing this
simulation is done to check whether the system functions properly along with a load
of interconnect.
3.Examples of ASIC
 .Standard cell-based ASIC: LCB 300k, 500k from LSI Logic Company, SIG1, 2, 3
families from ABB Hafo Inc., GCS90K of GCS Plessey.
 Gate Array Products: AUA20K from Harris Semiconductor, SCX6Bxx from National
Semiconductors, TGC/TEC families from Texas Instruments.

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 
PLD Products: PAL family of Advanced Micro Devices, GAL family from Philips
Semiconductors, XC7300 and EPLD from XILINX.

FPGA Products: XC2000, XC3000, XC4000, XC5000 series from XILINX, pASIC1
of QuickLogic, MAX5000 from Altera.

4.Advantages & Disadvantages of ASIC

The advantages of ASIC include the following.

 The small size of ASIC makes it a high choice for sophisticated larger systems.

 As a large number of circuits built over a single chip, this causes high-speed
applications.

 ASIC has low power consumption.

 As they are the system on the chip, circuits are present side by side. So, very minimal
routing is needed to connect various circuits.
 ASIC has no timing issues and post-production configuration.
The disadvantages of ASIC include the following.

 As these are customized chips they provide low flexibility for programming.

 As these chips have to be designed from the root level they are of high cost per unit.
 ASIC have larger time to market margin.

5. ASIC vs FPGA
ASIC FPGA

 Not reprogrammable  Reprogrammable

 Preferred for High volume productions  Preferred for low volume productions

 These are Application Specific  Used as prototypes of a system

 Energy Efficient requires less power  Less energy efficient requires more power

 These are permanent circuitry that can’t be  Highly suitable for applications where the
upgraded from time to time. circuit has to be upgraded time to time such
as cell phone chips, Base stations etc

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4 .FPGA Design Flow

 Architecture design: This step involves analysis of the design requirements and
functional simulation. The output of this step is a document which describes the
design architecture, structural blocks, their functions and interfaces. Design engineer
design the architecture according to system specification.

 Design entry: The design is described in a formal hardware description language

(HDL). The most common HDLs are VHDL and Verilog. Test environment design.
This step involves writing of test environments and behavioral models. They are later
used to ensure that the HDL description of a device is correct.

 Behavioral simulation: This is an important step that check HDL correctness by

comparing output of the HDL model and the behavioral model.RTL description is
used for simulation to test the functionality with the help of EDA tools.

 Design Synthesis: In this step RTL code is converted to gate level netlist using
synthesis tool. Netlist is a description of the circuit in terms of gates and connections
between them. Synthesis is performed by a synthesis tool. For an HDL code that is
correctly written and simulated, synthesis shouldn't be any problem. However,

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 synthesis can reveal some problems and potential errors that can not be found using
behavioral simulation so an FPGA engineer should pay attention to warnings
produced by the synthesis tool. Functional verification is performed to ensure the
RTL design is done according to the specifications.

 Design Implementation: A synthesis tool generate netlist is mapped onto particular

device's internal structure. The main phase of the implementation step is place and
route which allocates FPGA resources such as logic cells and connection wires. Then
these configuration data are written to a special file by a program called bitstream
generator.

 Timing analysis: During the timing analysis timing tool checks whether the
implemented design satisfies timing constraints such as clock frequency, setup
violation and hold violation specified by the user.

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 Study of FPGA Development Boards
ZYNQ 7000 series
1. OVERVIEW

 Before the invention of the Zynq, processors were coupled with a Field
Programmable Gate Array (FPGA) which made communication between the
Programmable Logic (PL) and Processing System (PS) complicated.

 The Zynq architecture, as the latest generation of Xilix’s all-programmable System-

on-Chip (SoC) families, combines a dual-core ARM Cortex-A9 with a traditional
(FPGA).

 The interface between the different elements within the Zynq architecture is based on
the Advanced eXtensible Interface (AXI) standard, which provides for high
bandwidth and low latency connections.

Figure1. Over view of ZYNQ

 Before implementing the ARM processor inside the Zynq device, users were using a
soft core processor such as Xilinx’s Microblaze.
 The main advantage of using Microblaze was, and remains, the flexibility of the
processor instances within a design.
 On the other hand, the inclusion of hard processor in Zynq delivers significant
performance improvements.
 Also, by simplifying the system to a single chip, the overall cost and physical size of
the device are reduced.

2. ARCHITECTURE OF ZYNQ 7000

Figure.2. shows the Zynq-7000 architecture.
It consists of two main parts,
1. Processing system (PS) and
2. Programmable logic (PL), connected through high-throughput data paths

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 Figure.2. Zynq-7000 architecture.

The PS consists of an
 Application Processor Unit (APU),
 Synchronous Dynamic RAM Controller (SDRAMC),
 Booting ROM
 Peripherals Such As Timers And Transceivers.

2.1. Application Processing Unit (APU)

The APU contains two ARM cortex-A9 processor units each of which generally includes
NEON unit, floating point unit (FPU), memory management unit (MMU) and L1 caches. In
addition, the APU also consists of snoop control and L2 caches. Fig. 3, shows the structure of
the APU.

 NEON: The Single Instruction Multiple Data (SIMD) is provided by this unit which
brings major acceleration of DSP and media algorithms to the main ARM processor.
 FPU: This unit provides the acceleration for the floating point operations.
 Level 1 cache: Each processor has its own instruction and data caches for storing the
instructions and data.
 MMU: It is responsible for translation of the virtual memory addresses to the physical
memory addresses.
 Snoop control Unit (SCU): The interfacing task among processors, L1 and L2 caches
is one of the main tasks of the SCU.
 L2 cache: It is shared between the two processors that enables them to access the
newest update of a variable.

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 Figure .3.Application Processing Unit Structure

2.2. Programmable Logic (PL) Structure

PL is the configurable part of the chip. In addition to standard configurable logic blocks it
includes specialized resources such as RAM, fixed-point arithmetic operators, serial
transceivers and two analog-to-digital converters.

Just like other FPGAs, the programmable logic portion of the Zynq SoC consists of
configurable logic blocks (CLBs) which contains two slices. Each slice contains four look-up
tables (LUTs), eight Flip-flops (FFs), and an accompanying switch matrix. Moreover, there
are Block RAMs and DSP slices as well. Fig. 4, shows the structure of the PL.
• Slice: Each slice consists of resources to implement the combinatorial and sequential
circuits.
• Look-up Table (LUT): To implement a logic function of up to six inputs, RAM, ROM
or shift registers, the LUTs are used.

• Flip-flop (FF): For implementation of 1-bit register with reset functionality, this
sequential element is used.

• Switch Matrix: It provides the connections among the different parts within and
between the CLBs, as well as other parts of the PL.

Figure 4: Structure of the PL

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3. Features Zynq 7000

The Zynq 7000 family offers the flexibility and scalability of an FPGA, while providing
performance, power, and ease of use typically associated with ASIC and ASSPs.
The range of devices in the Zynq 7000 SoC family enables designers to target cost-sensitive
as well as high-performance applications from a single platform using industry-standard
tools.

3.1. Features of APU

 2.5 DMIPS/MHz per CPU
 CPU frequency: Up to 1 GHz
 Coherent multiprocessor support
 Caches
 32 KB Level 1 4-way set-associative instruction and data caches (independent for
each CPU)
 512 KB 8-way set-associative Level 2 cache(shared between the CPUs)
 1GB
 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memorie
 8-bit SRAM data bus with up to 64 MB support
 8-Channel DMA Controller
 Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE
Std 1588 revision 2.0 support
 High-bandwidth connectivity within PS and between PS and PL

3.2. Features of PL
Programmable Logic (PL)Configurable Logic Blocks (CLB)
• Look-up tables (LUT)
• Flip-flops
• Cascadeable adders
36 Kb Block RAM
• True Dual-Port
• Up to 72 bits wide
• Configurable as dual 18 Kb block RAM
DSP Blocks
• 18 x 25 signed multiply• 48-bit adder/accumulator
• 25-bit pre-adder
Programmable I/O Blocks
• Supports LVCMOS, LVDS, and SSTL
• 1.2V to 3.3V I/O
JTAG Boundary-Scan
• IEEE Std 1149.1 Compatible Test Interface
Serial Transceivers
• Up to 16 receivers and transmitters
• Supports up to 12.5 Gb/s data rates
Two 12-Bit Analog-to-Digital Converters
• On-chip voltage and temperature sensing
• Up to 17 external differential input channels
• One million samples per second maximum conversion rate

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4. Zynq Design Flow

 The design flow for the Zynq architecture has some steps in common with a regular
FPGA. Fig. 2 shows the Zynq SoC design flow.

 The first stage is to define the specifications and requirements of the system.

 Next, during the system design stage, the different tasks (functions) are assigned to
implementation in either PL or PS which is called task partitioning. This stage is
important because the performance of the overall system will depend on
tasks/functions being assigned for implementation in the most appropriate technology:
hardware or software.

 Next, the hardware and software development and testing should be done. Regarding
the PL, the task is to identify the required functional blocks to achieve the design
characteristics and also assemble them as IPs and make the appropriate connections
between them.

 Likewise, the software activity is to develop code to run on the PS. Consequently,
system integration and testing is required to wrap up the design.

Figure 2: Zynq Design Flow Steps

5. Implementation and Testing of Xilinx Zynq in the design process

Various procedures are involved while implementing and testing designs on the Xilinx Zynq
platform. Following is the summary of the procedure:
Simulation: The first stage uses a hardware description language such as VHDL or Verilog
to design and simulate the system. This stage entails thoroughly describing the system’s
functioning and behavior and simulating it to ensure it fits the design specifications.

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Synthesis: The design is then synthesized into a gate-level netlist using a tool like Xilinx
Vivado. The high-level RTL description translates into a low-level gate-level implementation
that we can write onto the Zynq platform.
Implementation: The next step is to use the Vivado implementation tool to implement the
idea on the Zynq platform. This stage entails inserting and routing the design onto the target
device and creating programming files for the Zynq platform.
Testing: Once the design is implemented on the Zynq platform, one must test it to ensure it
satisfies the specifications. This process entails executing a series of tests to ensure the
system’s operation and identify any flaws or mistakes to address.
Debugging: one must debug the design if any faults or defects are discovered during testing.
This stage entails employing debugging tools and techniques to discover and resolve faults
preventing the system from working correctly.
Deployment: After extensively testing and debugging the design, it may eventually go to the
target environment. The final design files help program the Zynq platform, which integrates
into the target system.

6. Applications
Due to its adaptability and flexibility, the Xilinx Zynq SoC is appropriate for various
applications across numerous industries. Here are some of the uses for the Xilinx Zynq SoC:
 Aerospace and Defense:
The aerospace and defense industries use Xilinx technology extensively because of its high
performance, low power consumption, and capacity for challenging data processing tasks.
Avionics, radar and electronic warfare, satellite communications, cyber security, unmanned
systems, and decision-making processes are a few examples.

 Automotive:
Because of its excellent performance capabilities, low power consumption, and capacity to
handle complicated data processing tasks, Xilinx technology is frequently helpful in the
automotive industry. ADAS, autonomous vehicles, infotainment systems, vehicle
networking, power train control, and more are a few examples.

 Consumer Electronics:
A strong and adaptable platform, the Xilinx Zynq system-on-chip (SoC) can be helpful in
various applications, including consumer electronics.
The following are some possible uses of the Zynq in consumer electronics:
Zynq is available in smart home appliances like security cameras, smart speakers, and home
automation systems. The SoC is perfect for various applications thanks to its processing
capability and low power consumption.

 Gaming Consoles: Because of Zynq’s powerful processing capabilities and capacity

for handling graphics-intensive programs, gaming consoles can also utilize it.
 Set-Top Boxes: Zynq’s processing power and capacity to support numerous
streaming protocols can also be helpful by set-top boxes, which access TV streaming
services.
 Wearable Technology: The Zynq is perfect for wearable technology, such as smart
watches and fitness trackers, because of its tiny form factor and low power
consumption.
 Drones: The Zynq is ideal for use in drones and other unmanned aerial vehicles
because it can simultaneously analyze data from several sensors (UAVs).

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  Custom hardware accelerators can be implemented in each application using Zynq’s
programmable logic, boosting performance and consuming less power. Overall, the
Xilinx Zynq is a robust and adaptable platform. It may be helpful in a variety of
applications for consumer electronics.

 Industrial automation
The Xilinx Zynq system-on-chip (SoC) is a versatile and powerful platform suitable for
various industrial automation applications. These are some applications for Xilinx Zynq in
industrial automation:
 Control systems for industry: The Zynq SoC can operate various industrial
processes, including motion control, machine vision, and process control. It can
handle real-time control jobs while processing data from sensors and other devices
because of its high-performance processing capabilities and configurable logic.
 Industrial communication systems: The Zynq SoC may implement numerous
industrial communication protocols such as Ethernet, CAN, and Modbus. Thanks to
its inbuilt CPU and programmable logic, it can perform data processing, protocol
translation, and other communication-related duties.
 Industrial IoT systems: The Zynq SoC may be a gateway device in industrial
IoT systems. It allows communication between the system’s sensors and devices.
Thanks to its processing power and programmable logic, it can interpret and analyse
data from sensors and communicate with other devices in the system.
 Robotics and automation systems: The Zynq SoC suits many robotics and
automation systems, including robot control, vision systems, and motion control.
Thanks to its processing power and programmable logic, it can handle complex
control tasks and real-time data processing.
 The Zynq SoC may be helpful in various test and measurement devices, including
oscilloscopes, signal generators, and data-collecting systems. Thanks to its processing
capability and programmable logic, it can handle real-time data collecting and
processing and execute numerous signal processing methods.

 Communications
Zynq is used to construct wireless communication systems such as LTE, Wi-Fi, Zigbee, and
other protocols. Designers may leverage the customizable FPGA fabric to construct bespoke
wireless protocols or algorithms. On the other hand, the high-performance ARM Cortex-A9
CPU can execute communication software stacks.
Overall, Xilinx Zynq is an adaptable platform that may be helpful in various communication
applications. Because of its high-performance CPU and programmable FPGA, it is an
excellent candidate for creating unique communication services or supporting established
communication protocols.

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 PYNQ DEVELOPMENT BOARDS
PYNQ stands for “Python Productivity for Zynq” an open-source software framework
supporting Xilinx Zynq devices. The framework is a combination of Ubuntu and Python,
which is very much useful by the development community.

PYNQ allows both the FPGA and the ARM part to interact using Python and Jupyter
notebooks running on the chip directly. Because of Python, PYNQ is very popular amongst
Embedded Developers.

PYNQ provides a Python interface to allow overlays in the PL to be controlled from Python
running in the PS. FPGA design is a specialized task which requires hardware engineering
knowledge and expertise. PYNQ overlays are created by hardware designers, and wrapped
with this PYNQ Python API.

TYPES
1. PYNQ-Z1 and
2. PYNQ-Z2

1. PYNQ-Z1

 The PYNQ-Z1 board is designed to be used with PYNQ, a new open-source

framework that enables embedded programmers to exploit the capabilities of Xilinx
Zynq.
 All Programmable SoCs (APSoCs) without having to design programmable logic
circuits. Instead, the APSoC is programmed using Python and the code is developed
and tested directly on the PYNQ-Z1.
 The programmable logic circuits are imported as hardware libraries and programmed
through their APIs in essentially the same way that the software libraries are imported
and programmed.

The PYNQ-Z1 board is the hardware platform for the PYNQ open-source framework. The
software running on the ARM A9 CPUs includes:

 Web server hosting the Jupyter Notebooks design environment

 The IPython kernel and packages
 Linux
 Base hardware library and API for the FPGA

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 Figure 1.1. Block Diagram Of PYNQ-Z1
The base overlay on PYNQ-Z1 includes the following hardware:

 HDMI (Input and Output)

 Microphone in
 Audio out
 User LEDs, Switches, Pushbuttons
 2x Pmod PYNQ MicroBlaze
 Arduino PYNQ MicroBlaze
 3x Trace Analyzer (PMODA, PMODB, ARDUINO)

 HDMI

The PYNQ-Z1 has HDMI in and HDMI out ports. The HDMI interfaces are connected
directly to PL pins. i.e. There is no external HDMI circuitry on the board. The HDMI
interfaces are controlled by HDMI IP in the programmable logic.

The HDMI IP is connected to PS DRAM. Video can be streamed from the HDMI in to
memory, and from memory to HDMI out. This allows processing of video data from python,
or writing an image or Video stream from Python to the HDMI out.

 HDMI In

The HDMI in IP can capture standard HDMI resolutions. After a HDMI source has been
connected, and the HDMI controller for the IP is started, it will automatically detect the
incoming data. The resolution can be read from the HDMI Python class, and the image data
can be streamed to the PS DRAM.

 HDMI Out

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The HDMI out IP supports the following resolutions:

 640x480

 800x600

 1280x720 (720p)

 1280x1024

 1920x1080 (1080p)*

Data can be streamed from the PS DRAM to the HDMI output. The HDMI Out controller
contains framebuffers to allow for smooth display of video data.

 Microphone In

The PYNQ-Z1 board has an integrated microphone on the board and is connected directly to
the Zynq PL pins, and does not have an external audio codec. The microphone generates
audio data in PDM format.

 Audio Out

The audio out IP is connected to a standard 3.5mm audio jack on the board. The audio output
is PWM driven mono.

 User IO

The PYNQ-Z1 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4
individual LEDs. These IO are connected directly to Zynq PL pins. In the PYNQ-Z1 base
overlay, these IO are routed to the PS GPIO, and can be controlled directly from Python.

 PYNQ MicroBlaze

PYNQ MicroBlazes are dedicated MicroBlaze soft-processor subsystems that allow

peripherals with different IO standards to be connected to the system on demand. This allows
a software programmer to use a wide range of peripherals with different interfaces and
protocols. By using a PYNQ MicroBlaze, the same overlay can be used to support different
peripheral without requiring a different overlay for each peripheral. he PYNQ-Z1 has two
types of PYNQ MicroBlaze: Pmod and Arduino, connecting to each type of corresponding
interface.

 Trace Analyzer

Trace analyzer blocks are connected to the interface pins for the two Pmod PYNQ
MicroBlazes, and the Arduino PYNQ MicroBlaze. The trace analyzer can capture IO signals
and stream the data to the PS DRAM for analysis in the Python environment.

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2. Detail Specification of PYNQ-Z1 Board
These specifications have been taken from Digilent Website and are as follows:

 SoC: ZYNQ XC7Z020–1CLG400C

 ARM Processor: 650MHz dual-core Cortex-A9 processor

 Memory Controller: DDR3 memory controller with 8 DMA channels and 4 high-

performance AXI3 slave ports

 High-Bandwidth Peripheral Controllers: 1G Ethernet, USB 2.0, SDIO

 Low-Bandwidth Peripheral Controllers: SPI, UART, CAN, I2C

 Programming Interfaces: JTAG, Quad-SPI flash, MicroSD Card

 Programming Logic Details:

- Logic Slices: 13,300 — Each slice is with four 6-input LUTs and 8 flip-flops

- Block Ram: 630KB (Fast)

- DSP Slices: 220

 Memory:
- DDR3: 512MB with 16-bit bus @ 1050Mbps

- Quad-SPI Flash: 16MB with factory programmed globally unique identifier

 Power: Powered from USB or any 7V-15V source

 USB and Ethernet:

- USB-JTAG Programming circuitry

- USB-UART bridge

- USB OTG PHY (supports host only)

- Gigabit Ethernet PHY

 Audio and Video:

- Microphone: Electret microphone with pulse density modulated (PDM) output

- Audio Jack: 3.5mm mono audio output jack, pulse-width modulated (PWM) format

- HDMI: HDMI sink port (input), HDMI source port (output)

 Switches, push-buttons, and LEDs:

- 4x push-buttons

- 2x slide switches

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 - 4x LEDs

- 2x RGB LEDs

 Expansion Connectors:
- 2x Pmod ports

- 16x FPGA I/O

 Arduino/chipKIT Shield connector:

- 49x FPGA I/O

- 6x Single-ended 0–3.3V Analog inputs to XADC

- 4x Differential 0–1.0V Analog inputs to XADC

3. PYNQ-Z2
The PYNQ-Z2 board is a development board designed for the Xilinx Zynq System-on-Chip
(SoC).

It is part of the PYNQ project, which aims to bring the benefits of programmable logic and
accelerated computing to the Python programming language and ecosystem.

The PYNQ-Z2 board features the Xilinx Zynq-7000 SoC, which combines dual-core Arm
Cortex-A9 processors with a field-programmable gate array (FPGA).
This combination allows developers to leverage the processing capabilities of the Arm cores
to run software applications while utilizing the FPGA's programmable logic structure to
implement custom hardware accelerators.

One of the critical features of the PYNQ-Z2 board is its support for the PYNQ framework.
PYNQ allows developers to interact with the board using Python and Jupyter notebooks,
design and program custom hardware accelerators, and create integrated software and
hardware systems.

The primary purpose of the PYNQ-Z2 board is to provide a platform for prototyping and
implementing custom hardware accelerators and software algorithms. It allows developers to
leverage programmable logic and processor cores to create complex high-performance
applications.

Through the PYNQ framework, users can harness the power of programmable logic by
creating custom hardware overlays and integrating them with software-defined processors.
This enables accelerated computation and hardware acceleration for various applications,
including machine learning, image processing, signal processing, robotics, and more.

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 Figure 1.1. Block Diagram Of PYNQ-Z1
The base overlay on PYNQ-Z2 includes the following hardware:

 HDMI (Input and Output)

 Audio codec
 User LEDs, Switches, Pushbuttons
 2x Pmod PYNQ MicroBlaze
 Arduino PYNQ MicroBlaze
 RPi (Raspberry Pi) PYNQ MicroBlaze
 4x Trace Analyzer (PMODA, PMODB, ARDUINO, RASPBERRYPI)

 HDMI

The PYNQ-Z2 has HDMI in and HDMI out ports. The HDMI interfaces are connected
directly to PL pins.

The HDMI IP is connected to PS DRAM. Video can be streamed from the HDMI in to
memory, and from memory to HDMI out. This allows processing of video data from python,
or writing an image or Video stream from Python to the HDMI out.

 HDMI In

The HDMI in IP can capture standard HDMI resolutions. After a HDMI source has been
connected, and the HDMI controller for the IP is started, it will automatically detect the
incoming data. The resolution can be read from the HDMI Python class, and the image data
can be streamed to the PS DRAM.

 HDMI Out

The HDMI out IP supports the following resolutions:

 640x480
 800x600

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  1280x720 (720p)
 1280x1024
 1920x1080 (1080p)*

Data can be streamed from the PS DRAM to the HDMI output. The HDMI Out controller
contains framebuffers to allow for smooth display of video data.

 Audio

The PYNQ-Z2 base overlay supports line in, and Headphones out/Mic. The audio source can
be selected, either line-in or Mic, and the audio in to the board can be either recorded to file,
or played out on the headphone output.

 User IO

The PYNQ-Z2 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4
individual LEDs. These IO are connected directly to Zynq PL pins. In the PYNQ-Z2 base
overlay, these IO are routed to the PS GPIO, and can be controlled directly from Python.

 PYNQ MicroBlaze

PYNQ MicroBlazes are dedicated MicroBlaze soft-processor subsystems that allow

peripherals with different IO standards to be connected to the system on demand. This allows
a software programmer to use a wide range of peripherals with different interfaces and
protocols. By using a PYNQ MicroBlaze, the same overlay can be used to support different
peripheral without requiring a different overlay for each peripheral.

The PYNQ-Z2 has three types of PYNQ MicroBlaze: Pmod, Arduino, and RPi (Raspberry
Pi), connecting to each type of corresponding interface

Each PYNQ MicroBlaze has the same core architecture, but can have different IP
configurations to support the different sets of peripheral and interface pins.

Trace Analyzer

Trace analyzer blocks are connected to the interface pins for the two Pmod PYNQ
MicroBlazes, the Arduino and RPi PYNQ MicroBlazes. The trace analyzer can capture IO
signals and stream the data to the PS DRAM for analysis in the Python environment.

4. Detail Specification of PYNQ-Z2 Board

These specifications have been taken from TUL Website and are as follows:
 SoC: ZYNQ XC7Z020–1CLG400C
 ARM Processor: 650MHz dual-core Cortex-A9 processor
 Memory Controller: DDR3 memory controller with 8 DMA channels and 4 high-
performance AXI3 slave ports

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 High-Bandwidth Peripheral Controllers: 1G Ethernet, USB 2.0, SDIO
 Low-Bandwidth Peripheral Controllers: SPI, UART, CAN, I2C
 Programming Interfaces: JTAG, Quad-SPI flash, MicroSD Card
 Programming Logic Details:
- Logic Slices: 13,300 — Each slice is with four 6-input LUTs and 8 flip-flops
- Block Ram: 630KB (Fast)
- DSP Slices: 220
 Memory:
- DDR3: 512MB with 16-bit bus @ 1050Mbps
- Quad-SPI Flash: 16MB with factory programmed globally unique identifier
 Power: Powered from USB or any 7V-15V source
 USB and Ethernet:
- USB-JTAG Programming circuitry
- USB-UART bridge
- USB OTG PHY (supports host only)
- Gigabit Ethernet PHY
 Audio and Video:
- Microphone: Electret microphone with pulse density modulated (PDM) output
- Audio Jack: Line-in with 3.5mm jack
- HDMI: HDMI sink port (input), HDMI source port (output)
- I2S interface with 24bit DAC with 3.5mm TRRS jack (Different than Z1)
 Switches, push-buttons, and LEDs:
- 4x push-buttons
- 2x slide switches
- 4x LEDs
- 2x RGB LEDs
 Expansion Connectors:
- 2x Pmod ports
- 16x FPGA I/O
 Arduino/chipKIT Shield connector:
- 49x FPGA I/O
- 6x Single-ended 0–3.3V Analog inputs to XADC
- 4x Differential 0–1.0V Analog inputs to XADC

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  Raspberry Pi connector
- 28x Total FPGA I/O (8 shared pins with Pmod
A port) (Different than Z1)
5. Conclusion
The main difference is the additional Raspberry Pi connector and the Audio Codec. Z1 has
integrated MIC and mono audio out. Z2, on the other hand, has Headphones out, Mic, and
Line In, providing you with more control. Since the SoC is the same, thus both boards have
mostly the same features.
What are the differences between the PYNQ-Z1 and PYNQ-Z2 boards?

The PYNQ-Z1 and PYNQ-Z2 boards share a number of similarities.

They both have a Zynq 7020, 512MB DDR, 10/100/1000 Ethernet, USB, SD card boot.
The main differences are the expansion headers, and the audio systems.

 The PYNQ-Z1 has 2 Pmods, an Arduino header, and ChipKit header. The PYNQ-Z2
also has 2 Pmods, and an Arduino header, but replaces the ChipKit header with a 40-
pin Raspberry Pi header. (Note the Raspberry Pi header has 26 data pins connected to
the PL. 8 of these pins are shared with Pmod A).

 The PYNQ-Z1 has an integrated MIC with PWM input, and mono PDM audio out.
The PYNQ-Z2 has a full ADI audio codec with Headphones out, Mic, and line in.

6. Applications

 Computer vision
 Industrial control
 The Internet of things (IoT)
 Drones
 Encryption
 Embedded computing acceleration
 Real-time processing and many more...

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