8086 Microprocessor

By
Irfan Rasool
Introduction
Intel 8086
○ Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was designed by Intel in 1976.
○ The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the HMOS is used for "High-speed
Metal Oxide Semiconductor".
○ Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type of package is DIP
(Dual Inline Package).
○ Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1 Mbyte of memory.
○ It consists of a powerful instruction set, which provides operation like division and multiplication very quickly.
○ 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode. Maximum mode is suitable for system
having multiple processors and Minimum mode is suitable for system having a single processor.
Difference between 8085 and 8086 Microprocessor
8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor varies between

5, 8 and 10 MHz for different versions.

It has five flags. It has nine flags.

8085 microprocessor does not support memory 8086 microprocessor supports memory segmentation.

segmentation.
Difference between 8085 and 8086 Microprocessor

8085 Microprocessor 8086 Microprocessor

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used. An additional

external processor can also be employed.

It contains less number of transistors compare to 8086 It contains more number of transistors compare to 8085

microprocessor. It contains about 6500 transistor. microprocessor. It contains about 29000 in size.

The cost of 8085 is low. The cost of 8086 is high.

Features of 8086
The most prominent features of a 8086 microprocessor are as follows −

○ It has an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster
processing.
○ It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus
resulting in faster processing.
○ It is available in 3 versions based on the frequency of operation −
a. 8086 → 5MHz
b. 8086-2 → 8MHz
c. 8086-1 → 10 MHz
○ It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
○ Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
○ Execute stage executes these instructions.
○ It has 256 vectored interrupts.
○ It consists of 29,000 transistors.
Architecture /
Block Diagram/
Functional Units
of 8086

The architecture of 8086

microprocessor is
composed of 2 major units
● BIU (Bus Interface Unit)
● EU (Execution Unit)
Architecture of 8086
Bus Interface Unit (BIU)
The segment registers, instruction pointer and 6-byte instruction queue are associated with the bus interface unit (BIU).

The BIU:

○ Handles transfer of data and addresses,

○ Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set called a queue,
○ Reads data from memory and I/O devices,
○ Writes data to memory and I/O devices,
○ It relocates addresses of operands since it gets un-relocated operand addresses from EU. The EU tells the BIU from
where to fetch instructions or where to read data.
Architecture of 8086
BIU has the following functional parts:

○ Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and stores them in the
instruction queue and this process is known as instruction prefetch. This process increases the speed of the processor.
○ Segment Registers: A segment register contains the addresses of instructions and data in memory which are used by the
processor to access memory locations. It points to the starting address of a memory segment currently being used.
There are 4 segment registers in 8086 as given below:
○ Code Segment Register (CS): Code segment of the memory holds instruction codes of a program.
○ Data Segment Register (DS): The data, variables and constants given in the program are held in the data segment of
the memory.
○ Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It also holds the contents of
registers and memory locations given in PUSH instruction.
○ Extra Segment Register (ES): Extra segment holds the destination addresses of some data of certain string
instructions.
○ Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program counter. It indicates to the
address of the next instruction to be executed.
Architecture of 8086
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those
instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct
connection with system buses as shown in the above figure, it performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Architecture of 8086
Flag Register

It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the accumulator. It
has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags

It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional flags −

● Carry flag − This flag indicates an overflow condition for arithmetic operations.
● Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 –
D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses
this flag to perform binary to BCD conversion.
● Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result
contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
● Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.
● Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag
is set to 1 else set to 0.
● Overflow flag − This flag represents the result when the system capacity is exceeded.
Architecture of 8086
Control Flags
Control flags controls the operations of the execution unit. Following is the list of control flags −

Trap flag − It is used for single step control and allows the user to execute one instruction at a time for
debugging. If it is set, then the program can be run in a single step mode.
Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. It
is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are accessed
from the higher memory address to the lower memory address and vice-a-versa.
Architecture of 8086
General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually to
store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL,
and DH and DL. It is referred to the AX, BX, CX, and DX respectively.

● AX register − It is also known as accumulator register. It is used to store operands for arithmetic operations.
● BX register − It is used as a base register. It is used to store the starting base address of the memory area within the
data segment.
● CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
● DX register − This register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a word was most
recently stored on the stack.
Working of 8086 Microprocessor
the overall processing cycle of the 8086 microprocessors

when an instruction is to be fetched from the memory, then firstly its physical address must be calculated and this is done at
the BIU.

The physical address of an instruction is given as:

PA = Segment address Χ 10 + Offset

For example: Suppose the segment address is 2000 H and the offset address is 4356 H. So, the generated physical address
is 24356 H. Here, the code segment register provides the base address of the code segment which is combined with the
offset address.
 Working of 8086 Microprocessor
The code segment contains the instructions.

Each time an instruction is fetched the offset address inside the code
segment gets incremented. So, once the physical address of an
instruction is calculated by the BIU of the processor, it sends the
memory location by the address bus to the memory.

Further, the desired instruction at that memory location which is

present in the form of the opcode is fetched by the microprocessor
through the data bus.

Suppose the instruction is

ADD BL, CL.

But, inside the memory, it will be in the form of an opcode. So, this
opcode is sent to the control unit.

The control unit decodes the opcode and generates control signals
that inform the BL and CL register to release the value stored in it.

Also, it signals the ALU to perform the ADD operation on that

particular data
Working of 8086 Microprocessor
ADD BL, CL. BL denotes the destination of the result of the add operation.

This clearly shows that whatever, the operation is performed its result must be stored in the first register i.e., BL for this
particular example.

Let us take another example: Consider an instruction, ADD CL, 05H.

This means that the operand which is 05H is to be added with the data present in the CL register and is stored in that
particular register i.e., CL. In such conditions, the operand is not provided to the control unit as only the opcode is required to
be decoded by the CU. Hence the operand is directly provided to the ALU. Also, the status of this result is stored in the flag
register. So, whenever, ALU carries out an operation, it simultaneously generates the result as well as its status.

It is to be noteworthy that in BIU, pipelining fails whenever there is branching in the instruction. This is because generally
instructions are present in a sequential manner. But, sometimes the instructions are required to be executed unsequentially.
However, in the queue, the instructions are stored sequentially. So, in case there exist a need for any random instruction to
be decoded. The opcode stored in the queue will become invalid and must be cleared at that particular time.
Pin Diagram
8086
Pin Diagram Explained
● Power supply and frequency signals
○ It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.
● Clock signal
○ Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
● Address/data bus
○ AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
● Address/status bus
○ A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.
Pin Diagram Explained
● S7/BHE
○ BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it
is active.
● Read
○ It is available at pin 32 and is used to read signal for Read operation.
● Ready
○ It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.
● RESET
○ It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
Pin Diagram Explained
● INTR
○ It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.
● NMI
○ It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.
● TEST
○ This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
● MN/MX
○ It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor
is to operate in; when it is high, it works in the minimum mode and vice-aversa.
● INTA
○ It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
Pin Diagram Explained
● ALE
○ It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a
valid address on the address/data lines.
● DEN
○ It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.
● DT/R
○ It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.
● M/IO
○ This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available
at pin 28.
Pin Diagram Explained
● WR
○ It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
● HLDA
○ It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
● HOLD
○ This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
● QS1 and QS0
○ These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue.
Pin Diagram Explained

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the

queue

1 0 Empty the queue

1 1 Subsequent byte from the

queue
Pin Diagram Explained
S2 S1 S0 Status

0 0 0 Interrupt
acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
Pin Diagram Explained
LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus. It is
activated using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to release the system bus.
When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
Memory Segmentation
Register Organization of 8086
Segment Registers
8086 Flag Register
Memory Segmentation
● Segmentation is the process in which the main memory of the computer is logically divided into
different segments.
● Need for Segmentation –
○ The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment
Registers.
○ Code segment register (CS): is used for addressing memory location in the code segment of the memory, where
the executable program is stored.
○ Data segment register (DS): points to the data segment of the memory where the data is stored.
○ Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the
memory.
○ Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that
segment of memory which is used to store stack data.
● 8086 BIU will send 20bit address, so as to access one of the 1MB memory locations.
● The four segment registers actually contain the upper 16 bits of the starting addresses of the four
memory segments of 64 KB each
● A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up
of contiguous memory locations. It is an independent, separately addressable unit.
● Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only
with four 64KB segments within the whole 1MB memory.
Memory Segmentation
Memory Segmentation
2 types of memory organisations are commonly used

● Linear addressing
● Segmented addressing

Types Of Segmentation

Overlapping Segment – A segment starts at a particular address and its maximum size can go up
to 64kilobytes. But if another segment starts along with this 64kilobytes location of the first
segment, then the two are said to be Overlapping Segment.

Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go
up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first
segment, then the two segments are said to be Non-Overlapped Segment.
Memory Segmentation
Rules of Segmentation:

● The starting address of a segment should be such that it can be evenly divided by 16.
● Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.
Advantages of the Segmentation
● It provides a powerful memory management mechanism.
● Data related or stack related operations can be performed in different
segments.
● Code related operation can be done in separate code segments.
● It allows to processes to easily share data.
● It allows to extend the address ability of the processor, i.e. segmentation allows
the use of 16 bit registers to give an addressing capability of 1 Megabytes.
Without segmentation, it would require 20 bit registers.
● It is possible to enhance the memory size of code data or stack segments
beyond 64 KB by allotting more than one segment for each area.
Addressing modes in 8086
Microprocessor
Addressing Modes
The different ways that a processor can access data are referred to as addressing

modes.

The addressing modes of any processor can be broadly classified as :

● Data addressing modes.

● Program memory addressing modes.
● Stack memory addressing modes.
Addressing modes in 8086 Microprocessor
The way of specifying data to be operated by an instruction is known as addressing
modes. This specifies that the given data is an immediate data or an address. It also
specifies whether the given operand is register or register pair.

Types of addressing modes:

1. Register mode – In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
Addressing modes in 8086 Microprocessor
2. Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit
data. Destination operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
Note that to initialize the value of segment register, an register is required.
MOV AX, 2000
MOV CS, AX
Addressing modes in 8086 Microprocessor
3. Displacement or direct mode – In this type of addressing mode the effective address is
directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]

4. Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.
Example: Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
Addressing modes in 8086 Microprocessor
5. Based indexed mode – In this the effective address is sum of base register and index
register.

Base register: BX, BP

Index register: SI, DI

The physical memory address is calculated according to the base register.

Example:

MOV AL, [BP+SI]

MOV AX, [BX+DI]

Addressing modes in 8086 Microprocessor
6. Indexed mode – In this type of addressing mode the effective address is sum of index
register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
7. Based mode – In this the effective address is the sum of base register and
displacement.
Example:
MOV AL, [BP+ 0100]
Addressing modes in 8086 Microprocessor
8. Based indexed displacement mode – In this type of addressing mode the effective address
is the sum of index register, base register and displacement.

Example:

MOV AL, [SI+BP+2000]

9. String mode – This addressing mode is related to string instructions. In this the value of SI and
DI are auto incremented and decremented depending upon the value of directional flag.

Example:

MOVS B

MOVS W
Addressing modes in 8086 Microprocessor
10. Input/Output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
11. Relative mode – In this the effective address is calculated with reference to instruction
pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address
Maximum and Minimum Mode
Pin Description
8086 Microprocessor Characteristics
● It contains 20 bit address bus.
● It contains 16-bit data bus, therefore 8086 is called as 16-bit microprocessor.
● It is 2-stage pipelined processor. It can prefetch 6 bytes from memory and
store into queue to increase the speed of the execution.
● It’s control bus carries signals for executing operations such as read ,write etc.
● It has Memory Banks. 2 banks of 512KB each. These banks are called as lower
Bank (even) and higher Bank (odd).
● In 8086 the entire memory is divided into four memory segments which are
code ,stack, data and extra segment.
● 8086 has 16 bit IO address.
● It has 256 interrupts.
Modes of Operation
8086 has two operating Modes:

● Minimum mode
● Maximum mode
Modes of Operation
Maximum mode
● In this we can connect more processors to 8086 (8087/8089).
● 8086 max mode is basically for implementation of allocation of global
resources and passing bus control to other coprocessor(i.e. second processor
in the system), because two processors can not access system bus at same
instant.
● All processors execute their own program.
● The resources which are common to all processors are known as global
resources.
● The resources which are allocated to a particular processor are known as local
or private resources.
Maximum
Mode Circuit
Circuit Explanation
● When MN/ MX’ = 0 , 8086 works in max mode.
● Clock is provided by 8284 clock generator.
● 8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three
such latches are required because address bus is 20 bit. The ALE(Address latch enable) is
connected to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller.
● The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction
of data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to
T. Both DEN and DT/ R’ are given by 8288 bus controller.
Circuit Explanation
Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus
controller.
Circuit Explanation
Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more
priority than RQ1/GT1.

INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.

In max mode, the advanced write signals get enabled one T-state in advance as
compared to normal write signals. This gives slower devices more time to get ready
to accept the data, therefore it reduces the number of cycles.
Advantages and Disadvantages of Max Mode
Advantages of max mode of 8086:
● It helps to interface more devices like 8087.This interface is also called a
closely coupled co-Processor configuration. In this 8086 is called as the host
and 8087 as Co-processor.
● It supports multiprocessing, Therefore it helps to increase the efficiency.
● The 8087 was the first floating-point coprocessor for the 8086 series of
microprocessors. The purpose of the 8087 was to increase calculations for
floating point operations, such as add, sub, multiply, divide, and square root.
Disadvantages of max mode over min mode :
● It has more complex circuit than min mode.
Minimum Mode
● The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
● In minimum mode,8086 is the only processor in the system which provides all
the control signals which are needed for memory operations and I/O
interfacing.
● Here the circuit is simple but it does not support multiprocessing.
● The other components which are transceivers, latches, 8284 clock generator,
74138 decoder, memory and i/o devices are also present in the system.
● The address bus of 8086 is 20 bits long. By this we can access 220 byte
memory i.e. 1MB . Out of 20 bits, 16 bits A0 to A15(or 16 lines) are multiplexed
with a data bus. By multiplexing, it means they will act as address lines during
the first T state of the machine cycle and in the rest, they act as data lines. A16
to A19 are multiplexed S3 to S6 and BHE’ is multiplexed with S7.
Min mode circuit
Control signals provided by 8086 for memory operations
and i/o interfacing
They are used to identifying whether the bus is carrying a valid address or
not , in which direction data is needed to be transferred over the bus, when
there is valid write data on the data bus and when to put read data on the
system bus. Therefore, their sequence pattern makes all the operations
successful in a particular machine cycle.
Control Signals
8282 (8 bits) latch :

● The latches are buffered D FF. They are used to separate the valid address from the multiplexed Address/data bus by using
the control signal ALE, which is connected to strobe(STB) of 8282. The ALE is active high signal. Here three such latches are
required because the address is 20 bits.

8286 (8 bits) transceivers :

● They are bidirectional buffers and also known as data amplifiers. They are used to separate the valid data from multiplexed
add/data bus. Two such transceivers are needed because the data bus is 16 bits long. 8286 is connected to DT/R’ and DEN’
signals. They are enabled through the DEN signal .The direction of data on the data bus is controlled by the DT/R’ signal. DT/R’
is connected to T and DEN’ is connected to OE’.
Control Signals
● 8284 clock generator is used to provide the clock.
● M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0, then
I/O operation is performed.
● The signals RD’ and write WR’ are used to identify whether a read bus cycle or
a write bus cycle is performing. When WR’ = 0 ,then it indicates that valid
output data on the data bus.
● RD’ indicates that the 8086 is performing a read data or instruction fetch
process is occurring .During read operations, one other control signal is also
used, which is DEN ( data enable) and it indicates the external devices when
they should put data on the bus.
● Control signals for all operations are generated by decoding M/IO’, RD’, WR’.
They are decoded by 74138 3:8 decoder.
Control Signals
INTR and INTA :

When INTR = 1,then there is an interrupt to 8086 by other devices for their service. When INTA’= 0,then it
indicates that the processor is ready to service them.

The bus request is made by other devices using the HOLD signal and the processor acknowledges them
using the HLDA output signal.
Thank You