MICROPROCESSOR AND ASSEMBLY LANGUAGE INDIVIDUAL ASSIGNMENT

JIMMA UNIVERSITY
AGARO CAMPUS
COMPUTER SCIENCE DEPARTMENT

Microprocessor and Assembly Language

Individual Assignment
NAME : DANIEL BIRHANU
ID RU0585/15

Submitted Date Jan 20/2025

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1)Definition of Interrupts
What is an interrupt?

 An interrupt is a signal emitted by a device attached to a computer or from

a program within the computer. It requires the operating system (OS) to stop and
figure out what to do next.
 An interrupt temporarily stops or terminates a service or a current process.
Most I/O devices have a bus control line called Interrupt Service Routine (ISR)
for this purpose.
 An interrupt is a signal sent to a microprocessor by hardware or software
indicating an event that requires immediate attention.
 Interrupts are a crucial part of microprocessor systems, enabling efficient
handling of events and improving responsiveness.
 An interrupt signal might be planned (i.e., specifically requested by a program) or
it may be unplanned (i.e., caused by an event that may not be related to a program
that's currently running on the system).

Main Purposes of Interrupts

 Efficient Handling of Events: Interrupts allow the processor to respond to critical

events immediately rather than constantly checking for them through polling,
saving CPU time.
 Multitasking:- In operating systems, interrupts facilitate multitasking by allowing
the CPU to switch between multiple processes or threads efficiently, ensuring that
high-priority tasks receive CPU time as needed.
 Error Handling: Help manage errors, such as hardware malfunctions or software
bugs.
 Resource Management: Interrupts help manage system resources effectively by
allowing the processor to perform other tasks while waiting for events or data
transfers to complete.

Examples of Scenarios Where Interrupts Are Beneficial

 Keyboard Input:- When a key is pressed, an interrupt signals the processor to

read the key input without constantly checking the keyboard.
 Timer Interrupts:- Used in operating systems for task scheduling, where a timer
interrupt signals a switch between tasks.
 Network Communication:- A network interface card (NIC) can generate an
interrupt when a data packet arrives, prompting the CPU to process it.
 I/O Operations:- When a peripheral device (like a printer or network card)
completes a data transfer, it can send an interrupt to the CPU.

2)Types of Interrupts
Interrupts can be broadly classified into hardware interrupts and software
interrupts, each serving distinct roles in a microprocessor system.

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I) Hardware interrupt

 A hardware interrupt is an electronic signal from an external hardware device that

indicates it needs attention from the OS.
 A hardware interrupt is generated externally by hardware devices to signal the
processor about an event requiring immediate attention.
 When a hardware device needs service (e.g., data transfer completion), it sends a
signal to the processor through a dedicated interrupt request (IRQ) line.

Examples:

 Keyboard Input: Pressing a key generates an interrupt for the processor to read
the key code.
 Printer: A printer might send an interrupt when it runs out of paper.
 Timer Interrupt: A periodic timer interrupt can trigger task switching in an
operating system.

Significance:

 Enables asynchronous event handling.

 Reduces the need for constant polling of devices, improving system efficiency.
 Essential for real-time systems where timely responses are critical.

II) Software Interrupts

 A software interrupt is triggered by a program or software instruction, often used

to request system services or perform specific tasks.
 A software interrupt occurs when an application program terminates or requests
certain services from the OS.
 Software interrupts are commonly used when the system interacts with device
drivers or when a program requests OS services.
 Software interrupts are invoked by executing specific instructions in the code
(like the INT instruction in x86 architecture).

Examples:

 System Calls: The INT 80h instruction in Linux is used for system calls like
reading or writing data.
 Exception Handling: Division by zero can generate a software interrupt for
error handling.
 Debugging Tools: Breakpoints in debuggers use software interrupts to halt
program execution.

Significance:

 Allows user programs to access system resources securely.

 Simplifies error handling and debugging.

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 Facilitates communication between applications and the operating system.

Difference Between Hardware Interrupts and Software Interrupts

Feature Hardware Interrupts Software Interrupts

Source External hardware devices Program instructions

Triggering method Hardware signal via Instruction within software

IRQline code
Examples Keyboard, printer, Timer System calls, Exceptions
Use Case Prioirtized via interrupt System services, Error handling
controllers
Priority management Prioritized via interrupt Manged by OS and CPU modes
controllers

3) Interrupt Instructions
Interrupt instructions in assembly language are used to handle events and exceptions
in a microprocessor system. Below are the functions of the INT, INTO, INT 3, and
IRET instructions, along with simple code examples for each.

 INT (Interrupt Call)

Function:
The INT instruction generates a software interrupt. It allows a program to request
services from the operating system or handle specific tasks defined by the interrupt
vector table.
Usage Example: (Using INT 21h for DOS system call)
assembly code:
MOV AH, 09h ; DOS service for printing string
MOV DX, OFFSET msg ; Load message address
INT 21h ; Call DOS interrupt to print message
RET
msg DB "Hello, World!$"

 INTO (Interrupt on Overflow)

Function:
The INTO instruction triggers an interrupt if the overflow flag (OF) is set, indicating
an arithmetic overflow.

Usage Example: (Overflow detection)

MOV AL, 127 ; Load AL with the maximum positive value for a signed byte
MOV AL, 1 ; Cause overflow

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INTO ; Trigger interrupt if overflow occurs

RET

 INT 3 (Breakpoints Interrupt)

Function:
The INT 3 instruction is a special single-byte opcode interrupt primarily used for
debugging. It triggers a breakpoints in the debugger.

Usage Example: (Debugging)

MOV AX, 1234h ; Load a value into AX register

INT 3 ; Trigger a breakpoints for debugging
MOV BX, AX ; This will execute after continuing from the breakpoints
RET

 IRET (Interrupt Return)

Function:
The IRET instruction is used to return from an interrupt service routine (ISR). It
restores the flags, code segment (CS), and instruction pointer (IP) from the stack.

Usage Example: (Returning from an ISR)

Org 100h
MOV AX, 0 ; Clear AX
MOV BX, 0 ; Clear BX
CALL misery ;call the interrupt service routine
MOV CX, AX ; Verify result after return
RET

myISR:
MOV AX, 1234h ;Load a value into AX
IRET ;Return from interrupt

Summary
Instruction Purpose Typical Use Case

INT Generate software System calls, service

interrupt requests
INTO Trigger interrupt on Arithmetic overflow
overflow detection
INT 3 Debugging break point Debugging and code
inspection
IRET Return from interrupt End of an ISR(Interrupt
service Service Routine)

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4) Real Mode vs. Protected Mode

Interrupts operate differently in real mode and protected mode of x86 processors
due to their architectural design. Each mode determines how memory and interrupts
are handled by the CPU.

 Real Mode
Real mode is the basic operating mode of x86 processors, used at system startup
and in legacy systems. It provides direct access to memory and hardware with
minimal protection mechanisms.

Interrupt Handling in Real Mode:

 Interrupt Vector Table (IVT): Located at memory address 0000:0000. Each

entry is 4 bytes:
o 2 bytes for the Instruction Pointer (IP).
o 2 bytes for the Code Segment (CS).
 16-bit Segment Offset: CS:IP pair used to address memory (1 MB
addressable).
 No Privilege Levels: All code runs with full access to memory and hardware.
 No Memory Protection: Programs can overwrite critical areas, leading to
instability.

Limitations:

 Limited Memory (1 MB): Addressing is limited to 1 MB with 20-bit

addressing.
 No Segmentation Protection: Programs can overwrite each other's memory.
 Single Privilege Level: No separation between user and kernel modes.
 Inefficient Multitasking: Lack of hardware-level multitasking support

 Protected Mode
Protected mode is an advanced mode introduced with the Intel 80286 processor,
providing enhanced memory protection, multitasking, and support for virtual
memory.

Interrupt Handling in Protected Mode:

 Interrupt Descriptor Table (IDT):

o The IDT holds up to 256 interrupt vectors.
o Each entry can point to an interrupt service routine (ISR) with more
security control.
 32-bit Segment Offset: 32-bit addressing with segment selectors.
 Privilege Levels (Rings):

o Ring 0 (kernel) has full access.

o Ring 3 (user) has restricted access.

 Memory Protection:

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o Memory segmentation with descriptors defining access rights.

o Virtual memory support through paging.

Advantages Over Real Mode:

 Extended Memory Access: Up to 4 GB of addressable memory using 32-bit

addressing.
 Memory Protection: Prevents programs from accessing unauthorized memory
areas.
 Multitasking Support: Hardware-level task switching and task states.
 Ring Privilege Levels: Separates kernel and user space for security

5) Interrupt Flag Bits

The Interrupt Flag (IF) is a specific control bit in the flag register of a processor that
plays a crucial role in interrupt handling and control.

It is used to enable or disable mask-able hardware interrupts. The IF bit is a part of

the EFLAGS register in x86 architecture and similar registers in other processor
architectures.

Role and Function: The primary role of the IF bit is to control whether the processor
will respond to mask-able interrupts. Mistakable interrupts are those that can be
ignored or delayed by the processor depending on the state of the IF bit.

 IF = 1 (Enabled): When the IF bit is set to 1, mask able interrupts are enabled.
The processor will recognize and process incoming hardware interrupts,
transferring control to the corresponding interrupt service routine (ISR).
 IF = 0 (Disabled): When the IF bit is cleared to 0, mask able interrupts are
disabled. The processor will ignore mask able interrupts, even if they occur, until
the IF bit is set back to 1.

Impact on Interrupt Processing:

The state of the IF flag directly affects interrupt handling:

Interrupt Handling Enabled: If the IF bit is set (1), the processor will
acknowledge and handle external hardware interrupts. Upon receiving an
interrupt request, the current instruction execution completes, and the control
is transferred to the appropriate ISR.

Interrupt Handling Disabled: If the IF bit is cleared (0), the processor will not
acknowledge mask able interrupts. This is useful in critical code sections
where the processor must not be interrupted, ensuring data integrity and
synchronization.

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Manipulation of the IF Bit

 The IF bit can be modified using assembly instructions like CLI (Clear Interrupt
Flag) to disable interrupts and STI (Set Interrupt Flag) to enable them.
 The PUSHF and POPF instructions can also be used to save and restore the entire
flag register, including the IF bit.

6)Interrupt Vector Table

 The Interrupt Vector Table (IVT) is a data structure used in computer systems to
manage hardware interrupts.
 It helps the processor locate the appropriate Interrupt Service Routine (ISR) when
an interrupt occurs.
 Typically, the IVT is located at a fixed memory address, such as 0x0000 in x86
architectures.
 Each entry in the IVT holds the address of a specific ISR responsible for handling
a particular interrupt.
 The table is essential for interrupt-driven systems, where hardware and software
interrupts need systematic handling.

Structure of the IVT

 The IVT consists of multiple entries, each corresponding to a specific interrupt.

 Each entry contains the memory address (pointer) of the ISR associated with that
interrupt. The size and number of entries vary by processor architecture.
 For example, in x86 systems, each entry is 4 bytes long, with 256 total entries
available.

The structure of the IVT depends on the processor architecture, but generally, it is
organized as follows:

 Fixed Memory Location:

· The IVT is located at a predefined memory address.

· For example, in the x86 architecture, it starts at address 0x0000.

 Entries:

 The table consists of multiple entries, each associated with a unique interrupt
number.
 Each entry stores a pointer (or vector) to the ISR handling the respective
interrupt.

 Size and Layout:

 · In x86 architecture:

o Each entry is 4 bytes (2 bytes for segment and 2 bytes for offset).
o A total of 256 entries are available, allowing for 256 unique interrupts.

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 ARM and other architectures may have different sizes and layouts based on
the design.

How an Interrupt Vector is Stored

 Each entry in the IVT stores a memory address (pointer) pointing to the ISR.
 The memory address typically includes:
o Segment Address: Identifies the memory segment where the ISR
resides.
o Offset Address: Specifies the exact location within that segment.

How the IVT is Used During Interrupt Processing

 Interrupt Request (IRQ):

A hardware device or software generates an interrupt request.

 Interrupt Identification:

The processor receives the interrupt and identifies the interrupt number.

 Lookup in IVT:

The processor uses the interrupt number as an index to locate the

corresponding ISR address in the IVT.

 Fetch and Execute:

The ISR address stored in the IVT entry is fetched.

The processor transfers control to the ISR, executing the routine to handle
the interrupt event.

 Return from Interrupt:

Once the ISR completes, control returns to the previously interrupted

code.

7) Steps in Interrupt Processing

The processing of an interrupt involves several key steps that enable the CPU to
handle the interrupt efficiently while maintaining system stability.

Here's an outline of the basic steps involved in interrupt processing, along with what
happens to the CPU state and registers when an interrupt is triggered:

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Steps in Interrupt Processing

 Interrupt Request (IRQ): A hardware device sends an interrupt request to the

interrupt controller.
 Interrupt Acknowledgment: The interrupt controller acknowledges the IRQ and
sends an interrupt vector to the CPU.
 Save CPU State: The CPU saves its current state, including the program counter
(PC), registers, and flags, to the stack. This process is called context saving.
 Disable Further Interrupts: The CPU may disable further interrupts to prevent
nested interrupts during ISR execution.
 Execute ISR: The CPU jumps to the address specified by the interrupt vector and
executes the ISR. The ISR handles the specific interrupt, such as reading data
from a device.
 Restore CPU State: After the ISR completes, the CPU restores its state from the
stack, including the program counter, registers, and flags. This process is called
context restoring.
 Re-enable Interrupts: The CPU re-enables interrupts if they were previously
disabled.
 Resume Execution: The CPU resumes executing the interrupted program from
the point where it left off.

· Impact on CPU State and Registers

• Program Counter (PC): The current value of the PC is saved so that execution can
resume correctly after handling the interrupt.

• Registers: The contents of various registers (general-purpose, status registers, etc.)

are saved to preserve their state before entering the ISR. This ensures that any
computations or data manipulations performed by the interrupted process are not lost.

• Flags/Status Information: Any condition flags or status information that could affect
program execution are also saved and restored after the ISR execution.

• Interrupt Masking: Depending on system design, certain interrupts may be masked

(disabled) during ISR execution to prevent nested interrupts or conflicts.

8) Handling Hardware Interrupts

Hardware interrupts are essential in computer systems to handle asynchronous events
like I/O operations, allowing the CPU to be efficiently utilized. Here's how the
mechanism works:

Mechanism of Handling Hardware Interrupts

Interrupt Request: When a hardware device (like a keyboard or a network

card) needs the CPU's attention, it sends an interrupt request (IRQ) to the
interrupt controller.

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Interrupt Controller: The interrupt controller (often an Advanced

Programmable Interrupt Controller, or APIC) receives the IRQ and prioritizes
it. It manages multiple interrupt lines and decides which interrupt to send to
the CPU if multiple requests occur simultaneously.

Interrupt Vector: The interrupt controller sends an interrupt vector to the

CPU. This vector is an identifier that points to the specific interrupt service
routine (ISR) that should handle the interrupt.

CPU Acknowledgment: The CPU acknowledges the interrupt controller and

begins executing the ISR associated with the interrupt vector.

Interrupt Service Routine (ISR): The ISR is a special function in the

operating system or firmware designed to handle the specific interrupt. It
processes the interrupt, performs necessary actions (like reading data from a
device), and then signals the interrupt controller that the interrupt has been
handled.

Return to Normal Execution: After the ISR has finished, the CPU resumes
its previous tasks. Depending on the operating system, it may re-enable
interrupts and handle other pending interrupts.

Roles of the Interrupt Controller and CPU

 Interrupt Controller:

Prioritization: Manages and prioritizes interrupt requests to ensure the

most critical interrupts are handled first.

Vectoring: Sends the correct interrupt vector to the CPU to identify the
appropriate ISR.

Masking and Unmasking: Can enable or disable specific interrupts to

prevent them from being processed when not needed.

 CPU:

Acknowledgment: Recognizes and acknowledges the interrupt request

sent by the interrupt controller.

Execution: Pauses its current tasks to execute the ISR for the interrupt.

Context Switching: Saves the current state of the CPU before

handling the interrupt and restores it afterward, ensuring seamless
continuation of processes.

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9) Nested Interrupts
 Nested interrupts occur when an interrupt is triggered while another interrupt is
already being processed.
 This means that the CPU must handle multiple interrupts simultaneously, which
can affect system performance and complexity
 This requires the CPU to pause the current interrupt service routine (ISR) and
handle the higher-priority interrupt before resuming the initial ISR.

Impact on System Performance

 Efficiency: Properly managed nested interrupts can increase system efficiency by

allowing high-priority tasks to interrupt lower-priority ones. This ensures that
critical tasks are addressed promptly.
 Latency: If not managed well, nested interrupts can increase the overall latency
of lower-priority tasks, as they may be preempted by higher-priority tasks.
 Complexity: Handling nested interrupts increases the complexity of the interrupt
handling process, requiring more sophisticated interrupt controllers and operating
system support.

How the CPU Manages Nested Interrupts

 Interrupt Prioritization: The interrupt controller assigns priorities to interrupts.

Higher-priority interrupts can preempt lower-priority ones, ensuring that the most
critical tasks are handled first.
 Context Saving: When a new interrupt occurs, the CPU saves the current state of
the ongoing interrupt service routine (ISR) to the stack. This includes the program
counter, registers, and flags.
 Disable Further Interrupts (Optional): The CPU may temporarily disable
further interrupts while processing the nested interrupt to prevent overwhelming
the system.
 Execute Higher-Priority ISR: The CPU executes the ISR for the higher-priority
interrupt.
 Restore Previous ISR State: After the higher-priority ISR is completed, the
CPU restores the state of the previous ISR from the stack and continues its
execution.
 Resume Execution: Once all nested interrupts are handled, the CPU resumes
normal execution of the interrupted program.

10) Practical Application

To demonstrate the use of an interrupt in an assembly program, we'll use a simple
example where the program reads a character from the keyboard using a keyboard
interrupt (INT 16h) on an x86 architecture.

We will explain how the interrupt is set up and processed.

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Simple Assembly Program Example (x86)

.model small

.stack 100h

.data

msg db 'Press a key: $'

key db 0

.code

main:

; Initialize data segment

mov ax, @data

mov ds, ax

; Display prompt message

mov ah, 09h

lea dx, msg

int 21h

; Wait for a key press (using INT 16h)

mov ah, 00h ; Function 00h: Read key from keyboard buffer

int 16h ; Keyboard interrupt

; Store the character in 'key' variable

mov [key], al

; Display the character back to the screen

mov ah, 09h

lea dx, key

int 21h

; Exit the program

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mov ah, 4Ch

int 21h

end main

Explanation:

Data Segment Setup:

 .model small specifies a small memory model, which means the code and data fit
within one segment.
 .stack 100h reserves 256 bytes for the stack.
 The message "Press a key: " is stored in the .data section, and a variable key is
declared to store the key pressed by the user.

Program Initialization:

 The program begins by setting up the data segment (mov ax, @data and mov ds,
ax).
 It then displays the prompt message to the user by calling interrupt int 21h with
function 09h.

Handling the Keyboard Interrupt:

The program waits for the user to press a key by invoking int 16h, which is
the keyboard interrupt.

1. ah = 00h specifies the function to read a key from the keyboard.

2. The result of the key press is stored in the AL register (lower 8
bits of ax), which contains the ASCII code of the pressed key.

Displaying the Key:

 After reading the key, the program stores the value of the AL register in the key
variable and displays it back on the screen using int 21h with function 09h.

Exiting the Program:

 The program exits by calling interrupt int 21h with function 4Ch, which
terminates the program and returns control to the operating system.

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References:
 Stallings, W. (2015). Computer Organization and Architecture. Pearson.
 Mazidi, M.A., & Mazidi, J.G. (2010). The 8086 Microprocessor: Programming
and Interfacing the PC. Pearson.
 Tanenbaum, A. S. (2013). Structured Computer Organization. Pearson.
 Irvine, K. (2003). Assembly Language for Intel-Based Computers. Pearson.
 John L. Hennessy and David A. Patterson.Computer Architecture: A Quantitative
Approach
 "Assembly Language for x86 Processors" by Kip R. Irvine:

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