MODULE 4: ARITHMETIC

NUMBERS, ARITHMETIC OPERATIONS AND CHARACTERS

NUMBER REPRESENTATION
• Numbers can be represented in 3 formats:
1) Sign and magnitude
2) 1's complement
3) 2's complement
• In all three formats, MSB=0 for +ve numbers & MSB=1 for -ve numbers.
• In sign-and-magnitude system,
negative value is obtained by changing the MSB from 0 to 1 of the corresponding positive value.
For ex, +5 is represented by 0101 &
-5 is represented by 1101.
• In 1's complement system,
negative values are obtained by complementing each bit of the corresponding positive number.
For ex, -5 is obtained by complementing each bit in 0101 to yield 1010.
(In other words, the operation of forming the 1's complement of a given number is equivalent
to subtracting that number from 2n-1).
• In 2's complement system,
Forming the 2's complement of a number is done by subtracting that number from 2n.
For ex, -5 is obtained by complementing each bit in 0101 & then adding 1 to yield 1011. (In other
words, the 2's complement of a number is obtained by adding 1 to the 1's complement of that
number).
• 2's complement system yields the most efficient way to carry out addition/subtraction operations.
ADDITION OF POSITIVE NUMBERS
• Consider adding two 1-bit numbers.
• The sum of 1 & 1 requires the 2-bit vector 10 to represent the value 2. We say that sum is 0 and the
carry-out is 1.

ADDITION & SUBTRACTION OF SIGNED NUMBERS

• Following are the two rules for addition and subtraction of n-bit signed numbers using the
2's complement representation system (Figure 1.6).
Rule 1:
 To Add two numbers, add their n-bits and ignore the carry-out signal from the MSB position.

 Result will be algebraically correct, if it lies in the range -2n-1 to +2n-1-1.

Rule 2:
 To Subtract two numbers X and Y (that is to perform X-Y), take the 2's complement of Y and
then add it to X as in rule 1.
 Result will be algebraically correct, if it lies in the range (2n-1) to +(2n-1-1).
• When the result of an arithmetic operation is outside the representable-range, an arithmetic
overflow is said to occur.
• To represent a signed in 2's complement form using a larger number of bits, repeat the sign bit as
many times as needed to the left. This operation is called sign extension.
• In 1's complement representation, the result obtained after an addition operation is not always
correct. The carry-out (cn) cannot be ignored. If cn=0, the result obtained is correct. If cn=1, then a 1
must be added to the result to make it correct.

OVERFLOW IN INTEGER ARITHMETIC

• When result of an arithmetic operation is outside the representable-range, an arithmetic overflow
is said to occur.
• For example: If we add two numbers +7 and +4, then the output sum S is
1011(←0111+0100), which is the code for -5, an incorrect result.
• An overflow occurs in following 2 cases
1) Overflow can occur only when adding two numbers that have the same sign.
2) The carry-out signal from the sign-bit position is not a sufficient indicator of overflow
when adding signed numbers.
ADDITION & SUBTRACTION OF SIGNED NUMBERS
n-BIT RIPPLE CARRY ADDER
• A cascaded connection of n full-adder blocks can be used to add 2-bit numbers.
• Since carries must propagate (or ripple) through cascade, the configuration is called an n-bit
ripple carry adder (Figure 9.1).
ADDITION/SUBTRACTION LOGIC UNIT
• The n-bit adder can be used to add 2's complement numbers X and Y (Figure 9.3).
• Overflow can only occur when the signs of the 2 operands are the same.
• In order to perform the subtraction operation X-Y on 2's complement numbers X and Y; we form

the 2's complement of Y and add it to X.

• Addition or subtraction operation is done based on value applied to the Add/Sub input control-line.
• Control-line=0 for addition, applying the Y vector unchanged to one of the adder
inputs. Control-line=1 for subtraction, the Y vector is 2's complemented.
DESIGN OF FAST ADDERS
• Drawback of ripple carry adder: If the adder is used to implement the addition/subtraction,
all sum bits are available in 2n gate delays.
• Two approaches can be used to reduce delay in adders:
1) Use the fastest possible electronic-technology in implementing the ripple-carry design.
2) Use an augmented logic-gate network structure.

CARRY-LOOKAHEAD ADDITIONS
• The logic expression for si(sum) and ci+1(carry-out) of stage i are
si = xi+yi+ci ------(1) ci+1=xiyi+xici+yici-------(2)
• Factoring (2) into
ci+1=xiyi+(xi+yi)ci
we can write
ci+1=Gi+PiCi where Gi=xiyi and Pi=xi+yi
• The expressions Gi and Pi are called generate and propagate functions (Figure 9.4).
• If Gi=1, then ci+1=1, independent of the input carry ci. This occurs when both xi and yi are 1.
Propagate function means that an input-carry will produce an output-carry when either x i=1 or
yi=1.
• All Gi and Pi functions can be formed independently and in parallel in one logic-gate delay.
• Expanding ci terms of i-1 subscripted variables and substituting into the c i+1 expression, we
obtain ci+1=Gi+PiGi-1+PiPi-1Gi-2. . . . . .+P1G0+PiPi-1 . . . . . .P0c0
• Conclusion: Delay through the adder is 3 gate delays for all carry-bits
& 4 gate delays for all sum-bits.
• Consider the design of a 4-bit adder. The carries can be implemented as
c1=G0+P0c0
c2=G1+P1G0+P1P0c0
c3=G2+P2G1+P2P1G0+P2P1P0c0
c4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P
1P0c0
• The carries are implemented in the block labeled carry-lookahead logic. An adder implemented in
this form is called a Carry-Lookahead Adder.
• Limitation: If we try to extend the carry-lookahead adder for longer operands, we run into a
problem of gate fan-in constraints.
HIGHER-LEVEL GENERATE & PROPAGATE FUNCTIONS
• 16-bit adder can be built from four 4-bit adder blocks (Figure 9.5).
• These blocks provide new output functions defined as G k and Pk,
where k=0 for the first 4-bit block,
k=1 for the second 4-bit block and so on.
• In the first block,
P0=P3P2P1P0
&
G0=G3+P3G2+P3P2G1+P3P2P
1G 0
• The first-level Gi and Pi functions determine whether bit stage i generates or propagates a carry,
and the second level Gk and Pk functions determine whether block k generates or propagates a carry.
• Carry c16 is formed by one of the carry-look ahead circuits
as c16=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0
• Conclusion: All carries are available 5 gate delays after X, Y and c0 are applied as inputs.

MULTIPLICATION OF POSITIVE NUMBERS

ARRAY MULTIPLICATION

• The main component in each cell is a full adder (FA)..

• The AND gate in each cell determines whether a multiplicand bit m j, is added to the incoming
partial- product bit, based on the value of the multiplier bit qi (Figure 9.6).
SEQUENTIAL CIRCUIT BINARY MULTIPLIER
• Registers A and Q combined hold PPi(partial product)
while the multiplier bit qi generates the signal Add/Noadd.
• The carry-out from the adder is stored in flip-flop C (Figure 9.7).
• Procedure for multiplication:
1) Multiplier is loaded into register Q, Multiplicand is loaded into register M and C & A are
cleared to 0.
2) If q0=1, add M to A and store sum in A. Then C, A and Q are shifted right one bit-position.
If q0=0, no addition performed and C, A & Q are shifted right one bit-position.
3) After n cycles, the high-order half of the product is held in register A
and the low-order half is held in register Q.
SIGNED OPERAND MULTIPLICATION
BOOTH ALGORITHM
• This algorithm
→ generates a 2n-bit product
→ treats both positive & negative 2's-complement n-bit operands uniformly (Figure 9.9-9.12).
• Attractive feature: This algorithm achieves some efficiency in the number of addition required
when the multiplier has a few large blocks of 1s.
• This algorithm suggests that we can reduce the number of operations required for multiplication
by representing multiplier as a difference between 2 numbers.
For e.g. multiplier(Q) 14(001110) can be represented as
010000 (16)
-000010 (2)
001110 (14)
• Therefore, product P=M*Q can be computed by adding 2 4 times the M to the 2's complement of

21 times the M.
FAST MULTIPLICATION
BIT-PAIR RECODING OF MULTIPLIERS
• This method
→ derived from the booth algorithm
→ reduces the number of summands by a factor of 2
• Group the Booth-recoded multiplier bits in pairs. (Figure 9.14 & 9.15).
• The pair (+1 -1) is equivalent to the pair (0 +1).
CARRY-SAVE ADDITION OF SUMMANDS
• Consider the array for 4*4 multiplication. (Figure 9.16 & 9.18).
• Instead of letting the carries ripple along the rows, they can be "saved" and introduced into the next
row, at the correct weighted positions.
• The full adder is input with three partial bit products in the first row.
• Multiplication requires the addition of several summands.
• CSA speeds up the addition process.
• Consider the array for 4x4 multiplication shown in fig 9.16.
• First row consisting of just the AND gates that implement the bit products m 3q0, m2q0, m1q0 and
m0q0.
• The delay through the carry-save array is somewhat less than delay through the ripple-carry array.
This is because the S and C vector outputs from each row are produced in parallel in one full-adder
delay.
• Consider the addition of many summands in fig 9.18.
• Group the summands in threes and perform carry-save addition on each of these groups in parallel
to generate a set of S and C vectors in one full-adder delay
• Group all of the S and C vectors into threes, and perform carry-save addition on them, generating a
further set of S and C vectors in one more full-adder delay
• Continue with this process until there are only two vectors remaining
• They can be added in a RCA or CLA to produce the desired product.
• When the number of summands is large, the time saved is proportionally much greater.
• Delay: AND gate + 2 gate/CSA level + CLA gate delay, Eg., 6 bit number require 15 gate delay,
array 6x6 require 6(n-1)-1 = 29 gate Delay.
• In general, CSA takes 1.7 log2k-1.7 levels of CSA to reduce k summands.

INTEGER DIVISION
• An n-bit positive-divisor is loaded into register M.
An n-bit positive-dividend is loaded into register Q at the start of the operation.
Register A is set to 0 (Figure 9.21).
• After division operation, the n-bit quotient is in register Q, and the remainder is in register A.
NON-RESTORING DIVISION
• Procedure:
Step 1: Do the following n times
i) If the sign of A is 0, shift A and Q left one bit position and subtract M from A;
otherwise, shift A and Q left and add M to A (Figure 9.23).
ii) Now, if the sign of A is 0, set q0 to 1; otherwise set q0 to 0.
Step 2: If the sign of A is 1, add M to A (restore).
RESTORING DIVISION
• Procedure: Do the following n times
1) Shift A and Q left one binary position (Figure 9.22).
2) Subtract M from A, and place the answer back in A
3) If the sign of A is 1, set q0 to 0 and add M back to A(restore A).
If the sign of A is 0, set q0 to 1 and no restoring done.

FLOATING-POINT NUMBERS & OPERATIONS

IEEE STANDARD FOR FLOATING POINT NUMBERS
• Single precision representation occupies a single 32-bit word.

The scale factor has a range of 2-126 to 2+127 (which is approximately equal to 10+38).
• The 32 bit word is divided into 3 fields: sign(1 bit), exponent(8 bits) and mantissa(23 bits).
• Signed exponent=E.
Unsigned exponent E'=E+127. Thus, E' is in the range 0<E'<255.
• The last 23 bits represent the mantissa. Since binary normalization is used, the MSB of the mantissa
is always equal to 1. (M represents fractional-part).
• The 24-bit mantissa provides a precision equivalent to about 7 decimal-digits (Figure 9.24).
• Double precision representation occupies a single 64-bit word. And E' is in the range 1<E'<2046.
• The 53-bit mantissa provides a precision equivalent to about 16 decimal-digits.

NORMALIZATION
• When the decimal point is placed to the right of the first (non zero) significant digit, the number
is said to be normalized.
• If a number is not normalized, it can always be put in normalized form by shifting the fraction and
adjusting the exponent. As computations proceed, a number that does not fall in the representable
range of normal numbers might be generated.
• In single precision, it requires an exponent less than -126 (underflow) or greater than +127
(overflow). Both are exceptions that need to be considered.
SPECIAL VALUES
• The end values 0 and 255 of the excess-127 exponent E’ are used to represent special values.
• When E’=0 and the mantissa fraction m is zero, the value exact 0 is represented.
• When E’=255 and M=0, the value ∞ is represented, where ∞ is the result of dividing a normal
number by zero.
• when E’=0 and M!=-, denormal numbers are represented. Their value is ±0.M X 2-126
• When E’=255 and M!=0, the value represented is called not a number(NaN). A NaN is the result of
performing an invalid operation such as 0/0 or√ 0 .

ARITHMETIC OPERATIONS ON FLOATING-POINT NUMBERS

Multiply Rule
1) Add the exponents & subtract 127.
2) Multiply the mantissas & determine sign of the result.
3) Normalize the resulting value if necessary.
Divide Rule
1) Subtract the exponents & add 127.
2) Divide the mantissas & determine sign of the result.
3) Normalize the resulting value if necessary.
Add/Subtract Rule
1) Choose the number with the smaller exponent & shift its mantissa right a number of
steps equal to the difference in exponents (n).
2) Set exponent of the result equal to larger exponent.
3) Perform addition/subtraction on the mantissas & determine sign of the result.
4) Normalize the resulting value if necessary.

IMPLEMENTING FLOATING-POINT OPERATIONS

• First compare exponents to determine how far to shift the mantissa of the number with the
smaller exponent.
• The shift-count value n
→ is determined by 8 bit subtractor &
→ is sent to SHIFTER unit.
• In step 1, sign is sent to SWAP network (Figure 9.26).
If sign=0, then EA>EB and mantissas MA & MB are sent straight through SWAP network.
If sign=1, then EA<EB and the mantissas are swapped before they are sent to SHIFTER.
• In step 2, 2:! MUX is used. The exponent of result E is tentatively determined as EA if EA>EB or
EB if EA<EB
• In step 3, CONTROL logic
→ determines whether mantissas are to be added or subtracted.
→ determines sign of the result.
• In step 4, result of step 3 is normalized. The number of leading zeros in M determines number of
bit shifts(X) to be applied to M.
Problem 1:
Represent the decimal values 5, -2, 14, -10, 26, -19, 51 and -43 as signed 7-bit numbers in the
following binary formats:
(a) sign-and-magnitude
(b) 1’s-complement
(c) 2’s-complement
Solution:
The three binary representations are given as:
 Problem 2:
(a) Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then add
them. State whether or not overflow occurs in each case.
a) 5 and 10 b) 7 and 13
c) –14 and 11 d) –5 and 7
e) –3 and –8
(b) Repeat Problem 1.7 for the subtract operation, where the second number of each pair is to
be subtracted from the first number. State whether or not overflow occurs in each case.
Solution:

(a)

(b) To subtract the second number, form its 2's-complement and add it to the first number.
Problem 3:
Perform following operations on the 6-bit signed numbers using 2's complement
representation system. Also indicate whether overflow has occurred.
Solution:

Problem 4:
Perform signed multiplication of following 2’s complement numbers using Booth’s
algorithm.
(a) A=010111 and B=110110 (b) A=110011 and B=101100
(c) A=110101 and B=011011 (d) A=001111 and B=001111
(e) A=10100 and B=10101 (f) A=01110 and B=11000
Solution:
Problem 5:
Perform signed multiplication of following 2’s complement numbers using bit-pair recoding
method.
(a) A=010111 and B=110110 (b) A=110011 and B=101100
(c) A=110101 and B=011011 (d) A=001111 and B=001111

Solution:
Problem 6:
Given A=10101 and B=00100, perform A/B using restoring division algorithm.

Solution:
Problem 7:
Given A=10101 and B=00101, perform A/B using non-restoring division algorithm.

Solution:
Problem 8:
Represent 1259.12510 in single precision and double precision formats

Solution:
Step 1: Convert decimal number to binary format
1259(10) =10011101011(2)
Fractional Part
0.125(10) =0.001
Binary number = 10011101011+0.001
= 10011101011.001
Step 2: Normalize the number
10011101011.001=1.0011101011001 x 210
Step 3: Single precision format:
For a given number S=0, E=10 and M=0011101011001
Bias for single precision format is = 127
E’= E+127 = 10+127 = 137(10)
= 10001001(2)
Number in single precision format is given as

Step 4: Double precision format:

For a given number S=0, E=10 and M=0011101011001
Bias for double precision format is = 1023
E’=E+1023=10+1023=1033(10)
=10000001001(2)
Number in double precision format is given as