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RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based
on FemtoRV32

Conference Paper · October 2023

DOI: 10.1109/ETCM58927.2023.10309011

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 RISC-V SoC Physical Implementation in 180 nm
CMOS with a Quark Core Based on FemtoRV32
Felipe F. Nascimento Rodrigo N. Wuerdig André F. Ponchet
Electronic Engineer Division IEEA Graduate Program on Microelectronics Electronic Engineer Division IEEA
2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM) | 979-8-3503-3823-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/ETCM58927.2023.10309011

Aeronautics Institute of Technology UFRGS Aeronautics Institute of Technology

São José dos Campos, Brazil Porto Alegre, Brazil São José dos Campos, Brazil
[email protected] [email protected] [email protected]

Bruno Sanches Denis S. Loubach Roberto d’Amore

Department of Electronic Systems Department of Computer Systems Electronic Engineer Division IEEA
University of São Paulo Aeronautics Institute of Technology Aeronautics Institute of Technology
São Paulo, Brazil São José dos Campos, Brazil São José dos Campos, Brazil
[email protected] [email protected] [email protected]

Marcus H. Victor Junior Walter S. Oliveira Vitor O. Kuribara

Electronic Engineer Division IEEA Electronic Engineer Division IEEA Electronic Engineer Division IEEA
Aeronautics Institute of Technology Aeronautics Institute of Technology Aeronautics Institute of Technology
São José dos Campos, Brazil São José dos Campos, Brazil São José dos Campos, Brazil
[email protected] [email protected] [email protected]

Luiz C. Moreira
Electronic Engineer Division IEEA
Aeronautics Institute of Technology
São José dos Campos, Brazil
[email protected]

Abstract—This article presents the first known physical imple- applications [3]. After the release of the RISC-V ISA, many
mentation of a RISC-V core based on the FemtoRV32 project, processor implementations were developed in both industry
using the Quark core to implement the RV32I instruction set. and academia. One example is the Raven processor [4], which
Our primary goal is to validate the micro-architecture for ASIC
development. Implemented using 180 nm CMOS technology, utilizes the PicoRV32 [5] core, a very popular 32-bit RISC-V
the core demonstrates functionality at frequencies as high as core developed by Clifford Wolf, one of the major contributors
120 MHz, which represents a 150% improvement over FPGA to the open-hardware community. Another example is the
implementations. Power dissipation tests estimate a range of 68 PolarFire SoC [6], developed by Microchip. Both of them are
to 108 mW, under different PVT corners, and slack margins of 0.5 available for sale on the market. On the academic side, we
and 2 ps, respectively. The core also passed standard regression
tests for RISC-V ISA compliance, executed within an automated have the example of the Steel ASIC [7] developed by UFRGS
verification environment. Additionally, our paper outlines the and the PreDrac [8] processor, the first developed by a Spanish
ASIC implementation tools and methodologies employed, adding institution. Both followed the development process to obtain a
to its viability as a foundation for developing low-cost micropro- physical implementation in silicon, listing the methodologies
cessors or custom ASICs for specific applications. used in their works.
Keywords—SoC, RISC-V, VLSI, CMOS, ASIC
Don et al. [9] proposed an automated validation framework
while addressing the development of a RISC-V processor.
I. I NTRODUCTION
However, their work focuses on an FPGA implementation
RISC-V architecture [1] and Open ISA allow the imple- rather than an ASIC implementation, which prevents the
mentation of micro-architectures suitable for specific applica- evaluation of the micro-architecture for its suitability for this
tions [2]. Large manufacturers use the architecture to develop type of project. On the other hand, the work of Roberto et
their products, protecting intellectual property rights under al. [10] presents the post-silicon validation process for RISC-
their implementation and non-standard instruction subsets, V microcontroller-based projects, although their work only
which encourages investment in research and development, focuses on the testing stages.
such as the creation of FireSim focused on high-performance Our paper brings the design flow of a RISC-V SoC in 180

979-8-3503-3823-2/23/$31.00 ©2023 IEEE

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nm CMOS technology, starting from prototyping on an FPGA,
using a valid and functional test environment for all stages of
the project.
The project underwent initial validation on an FPGA, utiliz-
ing a 1,280 logic elements and 64K bits of RAM. The subse-
quent physical implementation, fabricated in 180 nm CMOS
technology, achieves a clock frequency of 120 MHz—marking
a 150% performance improvement over the FPGA prototype.
To secure reliable operation throughout the prototyping and
physical implementation phases, a specialized test-bench is de-
ployed. That environment features a unique test-bench module
that supports automated regression testing during both front- Fig. 1. Block diagram. Peripherals attached to the processor and I/O pins.
end and post-layout stages. Moreover, the module enables the
generation and execution of test scripts in C or assembly
languages, thereby ensuring a comprehensive verification of The FemtoRV32 SoC is an adaptation of the PicoRV32 SoC,
the core. featuring SPI peripherals capable of reading from external
flash and a UART for processor communication. The project
II. R ELATED W ORKS also integrates an adapted PWM module, making it suitable for
small embedded systems. Physical chip development is carried
The Steel ASIC project employed Cadence EDA tools to
out using Cadence EDA tools. A simplified block diagram of
develop a RISC-V microprocessor, achieving a maximum
the adapted project is shown in Fig. 1.
frequency of 19.1 MHz with a 10.09 mW power consump-
The development of digital chips has multiple stages, start-
tion [7]. Compatible with both Harvard and von Neumann
ing with the definition of architecture requirements, progress-
architectures, their processor was built using 180 nm Silicon
ing through micro-architecture development, RTL design, and
Foundries technology and underwent stages of register-transfer
functional versification. The design is then synthesized to
level (RTL), logical synthesis, and physical synthesis. RTL
create a netlist, which is passed on to a team handling the
validation was conducted using NcLaunch and SimVision,
back-end flow, where the circuit connectivity is optimized
although specific validation methods were not disclosed.
and undergoes various modifications. Tests are performed to
The PreDrac processor, implementing the RV64IMA scalar validate the design after changes, but this is not always feasible
ISA, aims to serve as a foundation for next-generation high- due to project complexity. Under such circumstances, the
performance processors [8]. Built on Rocket and Lagarto design undergoes logical equivalence checks (LEC), where a
RISC-V cores, the chip comprises five stages and has un- tool validates that the modified design remains functionally
dergone FPGA testing prior to its 65 nm TSMC Foundry identical to the original, or golden model.
implementation. The design was rigorously verified through
To validate the functionality of the chosen RTL core,
three abstractions, employing RTL and gate-level simulations
compliance tests are performed according to the specifications
with 395 ISA tests.
of RISC-V International to ensure that basic operations meet
Another project presents a RISC-V processor designed for the RV32I specification. To create a practical and configurable
frequencies up to 32 MHz using the RV32I ISA [9]. That work test environment for the selected core, an automated system
outlines front-end development phases for small embedded is developed capable of configuring and generating the test
systems and offers a framework for core verification, sharing environment automatically, following an approach similar to
similarities in verification methods and architecture with our that described in [13].
work.
For simulations, a test-bench file was developed and the
The research in [10] underlines the often-overlooked im- tools Icarus Verilog and Gtkwave were used. On the Cadence
portance of post-silicon verification, detailing its challenges side, the Xcelium software is available, thus allowing the
and advocating for a functional verification environment that validation of test instructions based on the chosen algorithm.
leverages earlier stages of the digital design flow. A coverage test is also performed using the Integrated Met-
rics Center tool. The code coverage analysis evaluates how
III. M ETHODOLOGY
well tests exercise the design code, pointing to areas that
Our goal is to validate a micro-architecture using 180 did not meet the desired coverage criteria. Next, the RTL
nm CMOS technology.. Our design employs the Quark core is implemented on the FPGA board to test the ability to
from the FemtoRV32 project [11], a single-cycle architecture execute an algorithm written in assembly and C languages
comprising fetch, decode, register-read, execute, and write- and compiled with the RISC-V tool-chain, to test the SPI and
back stages. Optimized for minimalism and compactness, the UART processor’s communication interfaces , as well as the
core is synthesizable on a low-cost iCESugar-nano FPGA [12] PWM peripheral.
using open-source tools (YOSYS, nextpnr, and icestorm), The previous steps describes the main initial front-end
achieving a top frequency of 48 MHz. phases. Notice that reliable and functional correct RTL de-

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 Fig. 2. Compliance verification of RISC-V. XOR instruction simulation.

scription is necessary for the specified project, which will later 100, considering 4-byte addresses. This value can be seen in
be used in the back-end process, avoiding any problems that the last waveform, “RAM[25]”, in Fig. 3, which shows the
may arise in this cycle. value in hexadecimal (0x19) written at address 100.
In the back-end process, the Genus tool with a cell library in To validate the correct operation of the SPI, UART, and
the 180 nm CMOS technology from Foundry UMC is used for PWM peripherals in the project, a test-bench is developed. It
synthesis. In that stage, the presence of latches were detected is capable of simulating the behavior of FLASH memory and
by the synthesis tool, and with some small modifications in communicating with the processor through the SPI protocol.
the RTL, the inferred latches were fixed. After that stage, logic This test-bench is able to verify if the system is operating
equivalence tests (LEC) is performed. as expected and can be used to validate test algorithms in C
For the implementation phase, the Innovus tool is used, or assembly, both in the simulation environment and in the
going through the floor-planning, placement, routing, and FPGA.
verification analysis processes. Gate-level simulation is a step Simulations are carried out for gate-level simulation to
in the project flow to ensure that the design meets function- validate the core and mentioned peripherals. Fig. 4 shows
ality after synthesis or after placement and routing activities. the test performed for the PWM peripheral, illustrating the
Through simulation, expected results were obtained for the simulation at five distinct time stages and the clk and D1
core used. signals. It is possible to observe the pulse width variation over
time in the D1 output signal. Fig. 5 shows the simulation of
IV. R ESULTS & D ISCUSSION the UART peripheral, displaying the transmission of the “a”
The Icarus Verilog software operates as a compiler for the character in the TXD output signal, using the RS-232 protocol,
RTL written in Verilog (IEEE-1364). For batch simulation, the for a baud rate of 115200 bps and a sampling time close to
compiler generates an intermediate form called vvp assembly. 8.63 us.
It is also possible to generate an executable file “.vcd”, Fig. 6 shows a diagram with the previously described
naturally interpreted by the Gtkwave software, thus obtaining phases. The testing environment for our project unfolds across
waveforms for circuit analysis. seven stages. Initially, it identifies and manages test files
Fig. 2 shows the result of a compliance test simulation for distributed across five distinct repositories, two for RISC-
the xor instruction. Four waveforms are displayed: the first V [15] and lowRISC [16] compliance tests, and the others
refers to the executed instruction; the second indicates the for peripheral and communication tests, unit tests, and general
program counter value; the third displays the accessed memory programs.
address; and the fourth shows the value written to the address.
In that test, the characters “xor” are written to the specified
address in the test file, observed approximately between 1
us and 5 us intervals. Then, “OK” is written approximately
between 119 us and 120 us intervals, as observed in the orange
waveform. Otherwise, “ERROR” will be written, indicating a
failure.
The algorithm presented in [14] is capable of testing the
RV32I instruction set base. Fig. 3 shows the behavior of this
simulated algorithm on the processor, where eight signals can
be observed in the image. The first four are clk and SPI
communication signals. At the end of the test, it is expected
that the decimal value of 25 is written to memory address Fig. 3. Core simulation. Running tests on the processor.

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 Fig. 4. PWM simulation.

Fig. 6. Automated environment flowchart for test execution and validation.

In the second stage, an application comprising a series of
scripts, takes charge of managing, compiling, and executing all executing tests.
files and scripts necessary to structure and operate the testing That robust testing environment facilitates validation for
environment. That application spans tasks from preparing the all phases construction, demonstrating its adaptability and
input data to the execution and validation of tests. efficiency throughout the developmental process
The third stage entails the compilation of test files using the The RTL is also synthesized on the iCESugar-nano
RISC-V tool-chain, converting the required files into machine- FPGA. iCESugar-nano is an FPGA board based on Lattice
executable code. iCE40LP1KCM36, which is fully supported by the tool-chain
In the fourth stage, the system organizes the compiled files (YOSYS & nextpnr & icestorm). A small algorithm written
and required dependencies into specific directories according in C language is tested and then loaded in the external
to their test type. That setup streamlines test execution by flash. Thus, the instructions are obtained by the processor
enhancing accessibility and reference during the execution through the SPI peripheral. The code runs in a loop generating
phase. the Fibonacci sequence and writing it to the address of the
The fifth stage involves using the objdump tool to extract peripheral responsible for performing the PWM signal. The
instructions in hexadecimal format from the compiled files, results can be viewed in a Linux terminal, via the processor’s
which are then interpreted and analyzed for execution in digital UART peripheral.
simulators. The previous steps complete the front-end stage. Further-
In the sixth stage, the system executes and validates each more, a coverage test is performed using the Integrated Metrics
test using either Icarus Verilog or Xcelium. The results are Center tool to validate the test-bench’s performance in testing
stored in a log file. all processor signals, achieving a 100% coverage for the core.
In the final stage, the system configures and runs the tests Digital Implementation is the process of importing a gate-
on a physical device, like an FPGA or physical chip, where level netlist with library technology, generating a physical
binary tests are loaded into external flash memory or executed design that meets power, performance, and area goals. The
via the SPI test interface on an auxiliary FPGA. total area limited to the chip was 1.33 mm2 . The tool used
The SPI test interface, a synthesizable Verilog for this process is the Cadence’s Innovus. After importing the
module, functions as a debugging interface. It replaces the netlist design into the tool, a core area is specified for the
flash memory, handling communication with the SoC and floor-plan and timing library configurations.
The optimization phase is the process of interacting through
the project so that it meets time, area, and energy specifica-
tions. Generally, specifications are divided into timing, signal
integrity, power, and area, including operations such as buffer
insertion or removal, logic remapping, optimization of layers,
and resizing of gates, among others. It is necessary for the
design to meet these multiple objectives. Clock tree synthesis
is the process of inserting buffers into the clock path with
Fig. 5. UART simulation. the aim of minimizing clock skew and latency to optimize

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 Fig. 7. Physical implementation steps.

timing, and subsequently initiating the routing process. The TABLE I

buffer cells that should be used for creating the clock tree are R ESULTS COMPARISON .
usually specified in the technology’s documentation. Fig. 7
Our Work [17] [7] [18]
shows the main steps carried out in the digital implementation
Technology Node [nm] 180 180 180 180
of the project. ISA RV32I RV32I RV32I + RV32I
The main steps in the physical design verification process theZicsr
are design rule checking (DRCs), i.e., verification executed Target Freq. [MHz] 100 40 19.61 40
Average CPI 1 3 3 1
in relation to the rules provided by a foundry for a specific Power [µW/MHz] 675 410.3 514.9 295.1
technology and process node. On the other hand, layout versus # Cells 16886 4559 231231 -
schematic (LVS) rules verify whether there are any incom-
patibilities in connectivity between what is in the placed and TABLE II
routed design and the Verilog netlist. Connectivity tests report P HYSICAL SYNTHESIS RESULTS .
possible open nets, antennas, and partial routing loops, for
all or specified nets in the design. The verification previously PVT Power Slack Area U/Opt
Case @ 100 MHz [mW] [ps] [µm2 ] @100 MHz [pJ]
mentioned were met.
After the completion of the digital implementation stages, Best 108.31 2 1083.1
1334.86
Worst 67.85 0.5 678.5
the tests described in that section are carried out again. During
the current stage, however, they are now called regression
tests, since the design was optimized and modified during the
V. C ONCLUSION
intermediary phases, which may alter the expected behavior
of the circuit. The same developed structure is used. The test- This work focuses on developing a low-cost microprocessor
bench module created by us can be reused in all stages of using RISC-V architecture, showcasing the potential of the
the flow, serving as an interface for communication between Quark core for such projects. Successful gate-level simulations
the processor and the test module. The codes will be made and layout verification have been carried out for frequencies
available in the project’s GitHub repository up to 120 MHz, and the ASIC is currently being fabricated.
When comparing the results with other works, it is possible The estimated power dissipation and slack have been obtained
to observe in Table I that the implementation presented in the for best-case and worst-case scenarios. The paper provides
article stands out in relation to others, both in terms of CPI
and operating frequency. However, it is worth noting that the
target frequency of the processor is relatively high compared
to other implementations, which may have influenced energy
consumption. Therefore, it is important to consider that the
presented implementation can be optimized in relation to
energy consumption and the number of cells used, which could
result in even better performance.
The final layout, submitted for tape-out, is depicted in Fig. 8.
Power consumption estimates, obtained through rigorous en-
ergy analysis under worst-case conditions, indicate an average
processor consumption of approximately 68 mW, as detailed
in Table II, as follows. Upon receipt of the fabricated chip and
subsequent PCB assembly, power categorization studies will
be conducted. These studies aim to evaluate the processor’s
energy efficiency at lower operating frequencies, utilizing
benchmark algorithms for comparison. Fig. 8. Layout.

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