LPC 2148 peripherals

Course handled by

Dr.Saru Meena R.

Assistant Professor

Dept. of Electronics and Communication

Engineering,

Amrita School of Engineering

Amrita Vishwa Vidyapeetham

Coimbatore
 General purpose input and output (GPIO)

§ General-purpose input/output (GPIO) is a pin on an IC (Integrated Circuit)

§ It can be either input pin or output pin, whose behavior can be controlled at the run time

§ A group of these pins is called a port (Example, Port 0 of LPC2148 has 32 pins).

§ LPC2148 has two 32-bit General Purpose I/O ports : (a) PORT0 and (b) PORT1

Port 0 :

§ PORT0 is a 32-bit port

§ Out of these 32 pins, 28 pins can be configured as either general purpose input or output

§ 1 of these 32 pins (P0.31) can be configured as general-purpose output only

§ 3 of these 32 pins (P0.24, P0.26 and P0.27) are reserved. Hence, they are not available for use. Also, these pins
are not mentioned in pin diagram

2
 General purpose input and output (GPIO)

§ PORT1 is also a 32-bit port. Only 16 of these 32 pins (P1.16 –

P1.31) are available for use as general-purpose input or output

§ Almost every pin of these two ports has some alternate function

available

§ For example, P0.0 can be configured as the TXD pin for UART0

or as PWM1 pin as well

§ The functionality of each pin can be selected using the Pin

Function Select Registers (PINSEL)

Pin diagram of LPC 2148

3
 General purpose input and output (GPIO)

Pin Function Select Registers (PINSEL)

§ PINSEL registers are 32-bit registers. These registers are used to select or configure specific pin functionality.

§ There are 3 PINSEL registers in LPC2148:

1. PINSEL0 : - PINSEL0 is used to configure PORT0 pins P0.0 to P0.15.

2. PINSEL1 : - PINSEL1 is used to configure PORT0 pins P0.16 to P0.31

3. PINSEL2 : - PINSEL2 is used to configure PORT1 pins P1.16 to P1.31.

§ Any pin on the LPC2148 can have a maximum of 4 functions

§ In order to select one of the four functions, two corresponding bits of the PINSEL register are needed

4
General purpose input and output (GPIO)

5
 General purpose input and output (GPIO)

§ There are two types of GPIO : (a) Slow GPIO and (b) fast GPIO

Slow GPIO :

§ In slow GPIO mode, the access to GPIO registers is done through the VPB (VLSI Peripheral Bus)

§ The VPB clock is typically derived from the CPU clock (CCLK) but can be divided by a factor (default is 4)

§ This division makes GPIO operations slower compared to the fast mode

§ Slow GPIO operations can take more clock cycles due to the VPB divider

Key characteristics of slow GPIO :

§ Accesses GPIO through VPB (divided clock).

§ Suitable for most standard GPIO applications.

§ Can be relatively slower due to the clock division

6
 General purpose input and output (GPIO)

Fast GPIO registers:

§ The fast GPIO is an enhanced version of GPIO access, introduced to speed up the GPIO operations.

§ In fast GPIO mode, the GPIO registers are accessed directly through the AHB (Advanced High-performance

Bus), which runs at the CPU clock speed (CCLK) without any division.

§ Fast GPIO operations are much faster because the GPIO control is directly connected to the AHB bus.

Key characteristics of fast GPIO:

§ Accesses GPIO directly through the AHB (no clock division).

§ Provides faster response for GPIO pin operations.

§ Suitable for time-critical applications where fast response is needed (e.g., toggling pins at high frequency)

Thus, slow GPIO is slower due to clock division, while fast GPIO operates at the system clock speed and is used

when speed is critical

7
 General purpose input and output (GPIO)

Slow GPIO registers:

§ IOxDIR (GPIO Port Direction control register) : This is a 32-bit wide register. This register individually controls
the direction of each port pin. Setting a bit to ‘1’ configures the corresponding pin as an output pin. Setting a bit

to ‘0’ configures the corresponding pin as an input pin.

§ IOxSET (GPIO Port Output Set register) : This is a 32-bit wide register. This register is used to make pins of Port

(PORT0/PORT1) HIGH. Writing one to specific bit makes that pin HIGH. Writing zero has no effect.

§ IOxCLR (GPIO Port Output Clear register) : This is a 32-bit wide register. This register is used to make pins of
Port LOW. Writing one to specific bit makes that pin LOW. Writing zeroes has no effect.

§ IOxPIN (GPIO Port Pin value register): This is a 32-bit wide register. This register is used to read/write the value
on Port (PORT0/PORT1). But care should be taken while writing. Masking should be used to ensure write to the

desired pin

§ x=0 or 1 ; 0 if port 0 is used and 1 if port 1 is used

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General purpose input and output (GPIO)

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

13
General purpose input and output (GPIO)

Configuring the pins as input or output :

14
General purpose input and output (GPIO)

15
General purpose input and output (GPIO)

16
General purpose input and output (GPIO)

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Analog to digital converter (ADC)

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Analog to digital converter (ADC)

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 Analog to digital converter (ADC)

Registers associated with ADC :

1) ADxCR : ADC control register (size : 32 bit)

x=0 or 1 depending upon the ADC module chosen

x=0 if ADC0 is chosen ; x=1 if ADC1 is chosen

AD0CR :

Bits 7:0 – SEL

These bits select ADC0 channel as analog input. In software-controlled mode, only one of these bits should be
1.e.g. bit 7 (10000000) selects AD0.7 channel as analog input

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 Analog to digital converter (ADC)

Bits 15:8 – CLKDIV

§ The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC

§ This clock should be less than or equal to 4.5MHz

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 Analog to digital converter (ADC)

Peripheral clock (PCLK) :

§ CCLK → CPU clock (60 MHz)

§ 𝑓!"# = 12 𝑀𝐻𝑧

§ 𝑓!"# → PLL block → CCLK = 60 MHz

$$%&
§ CCLK → VPB DIV block → PCLK = '

§ If PCLK has to be 60 MHz , y=1 (i.e.) the

dividing factor in the VPB DIV block should

be 1

§ If PCLK has to be 30 MHz , y=2 (i.e.) the

dividing factor in the VPB DIV block should

be 2

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 Analog to digital converter (ADC)

Bits 15:8 – CLKDIV

§ The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC

§ This clock should be less than or equal to 4.5MHz

Calculation :

($%& (+,-.+/,-01 #1!#2)

§ 4
= 𝐴𝐷𝐶 𝑐𝑙𝑜𝑐𝑘 = 4.5 𝑀𝐻𝑧

($%& $(6 #1!#2

§ PCLK = 60 MHz ; ∴ 𝑥 = 135 ; but this x is made to 14 so that ≤ 4.5 𝑀𝐻𝑧
4

§ But to avoid the divide by zero error , LPC 2148 will add 1 to whatever value is being given in CLKDIV . ∴ 8 bit
binary representation of 135 is loaded in CLKDIV ; CLKDIV = 0000 1101

§ In short , value needed is 𝑥 = 145 ; value loaded is 𝑥 = 135 23

 Analog to digital converter (ADC)

Bit 16 – BURST

Burst mode in the LPC2148 ADC allows for continuous conversions without the need for constant manual

triggering

§ When burst =0 , the ADC waits for the user to tell it to start each time. It takes one reading, then stops.

§ Burst = 0 means the user must manually trigger the ADC to start each conversion, either by software (the user

tell it to start) or using an external signal (like pressing a button)

§ The ADC converts the signal once and then stops. The user must issue another command for the next
conversion.

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 Analog to digital converter (ADC)

Bit 16 – BURST

When BURST = 1, ADC works in burst mode

§ When burst mode is enabled, the ADC automatically samples and converts the selected analog input channels

repeatedly without requiring the user to start each conversion individually

§ In simple terms, it's like setting the ADC to autopilot mode—once activated, it keeps converting analog signals

into digital values continuously for the selected channels, instead of waiting for the user to say, "start a new

conversion”

§ When Burst = 1, the START bits must be 000, otherwise the conversions will not start

§ In Burst mode, ADC does repeated conversions at the rate selected by the CLKS field for the analog inputs
selected by SEL field

§ When Burst = 1, the START bits must be 000, otherwise the conversions will not start

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 Analog to digital converter (ADC)

Bits 19:17 – CLKS

Selects the number of clocks used for each conversion in burst mode and the number of bits of accuracy of Result

bits of AD0DR.

e.g. 000 uses 11 clocks for each conversion and provide 10 bits of result in corresponding ADDR register.

000 = 11 clocks / 10 bits

001 = 10 clocks / 9 bits § For 10 bit ADC , the smallest change in analog voltage (step size) =
010 = 9 clocks / 8 bits !.!
= 3.2 𝑚𝑣
#$%&
011 = 8 clocks / 7 bits § If the input voltage is 0v, the digital output is 0. If the input voltage
100 = 7 clocks / 6 bits becomes 3.3mv, the digital output is 1.
101 = 6 clocks / 5 bits § Only if there is a change in input voltage by 3.2 mv, there will be a

110 = 5 clocks / 4 bits transition to the next value in digital output

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 Analog to digital converter (ADC)

Bit 20 – RESERVED

Bit 21 – PDN ; used to decide whether ADC is in power down mode or involved in conversion

0 = ADC is in Power Down mode

1 = ADC is operational

Bit 23:22 – RESERVED

Bit 26:24 – START

When BURST bit is 0, these bits control whether and when A/D conversion is started

000 = No start (Should be used when clearing PDN to 0)

001 = Start conversion now

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 Analog to digital converter (ADC)

010 = Start conversion when edge selected by bit 27 of this register occurs on CAP0.2/MAT0.2 pin

011= Start conversion when edge selected by bit 27 of this register occurs on CAP0.0/MAT0.0 pin

100 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.1 pin

101 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.3 pin

110 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.0 pin

111 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.1 pin

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 Analog to digital converter (ADC)

Bit 27 – EDGE

This bit is significant only when the Start field contains 010-111. In these cases,

0 = Start conversion on a rising edge on the selected CAP/MAT signal

1 = Start conversion on a falling edge on the selected CAP/MAT signal

Bit 31:28 – RESERVED

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 Analog to digital converter (ADC)

ADxGDR (A/D Global Data Register) :

§ ADxGDR is a 32-bit register (x=0 or 1)

§ This register contains the ADC’s DONE bit and the result of the most recent A/D conversion

Bit 5:0 – RESERVED

Bits 15:6 – RESULT

§ When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or

equal to VSSA) to 1023 (greater than or equal to VREF).

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 Analog to digital converter (ADC)
Bit 23:16 – RESERVED

Bits 26:24 – CHN

§ These bits contain the channel from which ADC value is read.

e.g. 000 identifies that the RESULT field contains ADC value of channel 0.

Bit 29:27 – RESERVED

Bit 30 – Overrun

§ This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the
conversion that produced the result in the RESULT bits

§ This bit is cleared by reading this register

Bit 31 – DONE

§ This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the
AD0CR is written

§ If AD0CR is written while a conversion is still in progress, this bit is set and new conversion is started
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 Analog to digital converter (ADC)
AD0DR0-AD0DR7 (ADC0 Data Registers)

§ These are 32-bit registers.

§ They hold the result when A/D conversion is completed.

§ They also include flags that indicate when a conversion has been completed and when a conversion overrun
has occurred

AD0 data registers structure

Bit 5:0 – RESERVED

Bits 15:6 – RESULT

§ When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or
equal to VSSA) to 1023 (greater than or equal to VREF).

Bit 29:16 – RESERVED

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 Analog to digital converter (ADC)
Bit 30 – Overrun

§ This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the
conversion that produced the result in the RESULT bits

§ This bit is cleared by reading this register

Bit 31 – DONE

§ This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read

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 Analog to digital converter (ADC)
Steps in analog to digital conversion :

§ Configure the port pin to function as ADC

§ Configure the ADxCR (ADC Control Register) according to the need of application.

§ Start ADC conversion by writing appropriate value to START bits in ADxCR. (Example, writing 001 to START bits

of the register 26:24, conversion is started immediately).

§ Monitor the DONE bit (bit number 31) of the corresponding ADxDRy (ADC Data Register) till it changes from 0

to 1. This signals completion of conversion

§ Read the ADC result from the corresponding ADC Data Register ADxDRy. E.g. AD0DR1 contains ADC result of

channel 1 of ADC0.

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 Analog to digital converter (ADC)
Steps in analog to digital conversion :

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 Analog to digital converter (ADC)
Step 1 :
PINSEL 1 register

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 Analog to digital converter (ADC)
Step 2 : Enable the power/clock to ADC0

PCONP : Power control for peripheral register (32 bit register)

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 Analog to digital converter (ADC)
Step 3 : Select channel 3 in AD0

ADOCR (Bits 7:0)

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 Analog to digital converter (ADC)
Step 4 : Set the CLKDIV to 13 ADOCR

AD0CR | = 13<<8

Step 5 : Disable the BURST mode by making

bit 16 as 0. This is done via. AND operation
between AD0CR and 0xFFFEFFFF Bit 21 = 1 ; this can be done via. OR operation between AD0CR

AD0CR & = 0xFFFEFFFF and 0x00200000

Step 5 : Configure CLKS as 000 since 10 bit AD0CR | = 0x00200000

resolution is needed Step 7: Start the ADC conversion now

19 : 17 = 000 ; this can be done via AND ADC conversion can be started immediately by making bits 26 :
operation between AD0CR and 0xFFF1FFF 24 as 001. Bit 24 is made 1 via. OR operation between AD0CR and

AD0CR & = 0xFFF1FFF 0x01000000. Bits 25 and 26 are made 0 via. AND operation
between AD0CR and 0x F9FFFFFF
Step 6 : Make PDN = 1 to activate the ADC
module AD0CR | = 0x01000000

AD0CR &=0xF9FFFFFF
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 Analog to digital converter (ADC)
Step 8 : Check whether analog to digital ADODR3
conversion is over or not by monitoring the
DONE bit (bit 31) in AD0GDR

AD0GDR & = 0x80000000 ; separate out bit

Except the RESULT bits , all the other bits in AD0DR3 are made 0
31 alone from AD0GDR
via. AND operation between (AD0DR3 >> 6) and 0x000003FF
If AD0GDR & = 0x80000000 is 1 , it
val = (AD0DR3>>6) & 0X000003FF
indicates that analog to digital conversion is
Step 9 : Deactivate the ADC module by making START bits (bits
complete ; else , it indicates that the analog
26 : 24) in AD0DGR as 000. This is done via. AND operation
to digital conversion process is not yet
between AD0CR and 0x F8FFFFFF
completed
AD0GDR & = 0xF8FFFFFF
§ When DONE=1 , the 10 bit A/D conversion
result is available in bits 15 : 6 of To visualize the result in terms of ON / OFF of 10 LEDs connected

AD0DR3. To visualize the result starting to port 1 (P1.16 to P1.25) , IO1PIN = val <<16 (since port 1 has pins

from bit 0 , the data in AD0DR3 has to be only from P1.16 to P1.31)

shifted right by 6. 40
 Analog to digital converter (ADC)
while(1) delay(200000);
Complete ADC code :
{ void adc_init(void)
# include <LPC214x.h>
AD0CR | = 0x00000008; {
void adc_init(void);
AD0CR | = 13<<8; PINSEL1& = 0xDFFFFFFF;
void delay(int j);
AD0CR & = 0xFFFEFFFF; PINSEL1|=0x10000000;
unsigned int val;
AD0CR & = 0xFFF1FFFF; PCONP|= (unsigned long) (0x00000001 << 12) ;
int main ()
AD0CR | = 0x00200000; }
{
AD0CR | = 0x01000000 ; void delay (int j)
PINSEL2 = 0x00000000;
AD0CR &=0xF9FFFFFF; {
IO1DIR = 0xFFFFFFFF;
while((AD0GDR & = 0x80000000)==0); for(i=0;i<=j;i++)
adc_init();
val = (AD0DR3>>6) & 0X000003FF; {

IO1PIN = val <<16

AD0GDR & = 0xF8FFFFFF; }

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}
 Timer in LPC 2148
§ LPC has two timer units : Timer 0 and timer 1

§ Each timer module can either work in timer mode or in counter mode

Timer mode :

§ Objective: In Timer Mode, the Timer captures time intervals. It is used to create delays, trigger events after a
specified time, or generate periodic signals

§ Clock source: The clock source for Timer Mode is the PCLK (Peripheral Clock) of the microcontroller.

Operation:

§ The Timer's internal counter is incremented by each pulse from the PCLK, based on the pre-scaler value.

§ It can be configured the timer to generate interrupts after a certain value (e.g., Timer match register).

§ The timer register increments up to a pre-defined value or overflows and resets, creating a periodic event if
set up with interrupts

§ Use Case: Timer Mode is used when you need a precise delay or to generate periodic actions like blinking
an LED or controlling a PWM signal.
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 Timer in LPC 2148

Counter mode :

§ Objective: In Counter Mode, the timer counts the number of external events or pulses. It acts like a digital

counter and is used to count occurrences of an external signal.

§ Clock Source: In this mode, an external input pin acts as the clock source instead of the internal PCLK.

Operation:

§ The counter register increments whenever a pulse is detected at the external clock input.

§ The input signal must be applied at one of the designated Timer/Counter pins (e.g., CAP or MAT pins).

§ This mode is ideal for applications where the need is to measure or count the frequency or occurrence of an

external signal

§ Use case: Counter mode is used in scenarios like measuring rotational speed, counting the number of
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sensor pulses, or detecting events such as button presses
 Timer in LPC 2148

§ The timer module in LPC 2148 supports two advanced functionalities: Capture mode and Match mode

§ There are upto four 32 bit capture channels per timer and four 32 bit match registers

Capture mode :

Objective: In Capture mode, the timer captures the current value of the timer counter when a specific external

event (like a signal pulse) occurs

Operation :

§ The Timer has dedicated Capture input pins (e.g., CAP0.0, CAP0.1).

§ When an edge (rising or falling) is detected on the Capture pin, the value of the Timer Counter (TC) is copied

to the corresponding Capture Register (CR)

§ Configure whether to capture on a rising edge, falling edge, or both

44
 Timer in LPC 2148

Match mode :

Objective: In Match mode, the timer counter value is compared with a predefined value, and specific actions
are performed when they match

Operation:

§ Match Registers (MR0, MR1) are used to specify the value that should be compared against the Timer

Counter (TC)

§ When the Timer Counter matches a value in the match register, several actions can be configured:

Generate an Interrupt: When the counter matches, an interrupt can be generated to perform specific actions

like toggling a pin or updating a value.

Reset the Timer: The timer can be reset to start counting again.

Stop the Timer: The timer can stop on a match, which is useful for one-shot timing operations

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Timer in LPC 2148

TCLK – Timer clock

§ The timer can be made to count faster

or slower by changing the value in the
prescaler register

46
Registers associated with timer

1. T0CTCR (Timer0 Counter Control Register)

§ It is a 32 bit register

§ Used to select between timer counter mode

§ When in counter mode, it is used to select the pin and edges for counting.

Bits 1:0 – Counter/Timer Mode

§ This field selects which rising edges of PCLK can increment Timer’s Prescale Counter (PC), or clear PC and
increment Timer Counter (TC).

§ 00 = Timer Mode: Every rising edge of PCLK

§ 01 = Counter Mode (Rising edge): TC is incremented on rising edge on the capture input selected by Bits 3:2.

§ 10 = Counter Mode (falling edge) : TC is incremented on falling edge on the capture input selected by Bits
3:2

§ 11 = Counter Mode (Both rising and falling edge): TC is incremented on both edges on the capture input
selected by Bits 3:2 47
Registers associated with timer

1. T0CTCR (Timer0 Counter Control Register)

Bits 3:2 – Count Input Select

§ These bits determine which capture input to use for the external event counter

§ 00 = CAP0.0

§ 01 = CAP0.1

§ 10 = CAP0.2

§ 11 = CAP0.3

Bits 31:4 – Reserved

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Registers associated with timer

2. T0PR (Timer0 Prescale Register)

§ It is a 32-bit register

§ It holds the maximum value of the Prescale Counter

3. T0PC (Timer0 Prescale Counter Register)

§ It is a 32-bit register

§ It controls the division of PCLK by some constant value before it is applied to the Timer Counter

§ It is incremented on every PCLK

§ When it reaches the value in Prescale Register, the Timer Counter(TC) is incremented by 1 and Prescale
Counter is reset on next PCLK

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Registers associated with timer

4. T0TC (Timer0 Timer Counter)

§ It is a 32-bit timer counter
§ When the timer is Reset and enabled , TC is set to 0 and incremented by 1 every ‘PR+1’ clock cycles
§ It is incremented when the Prescale Counter (PC) reaches its maximum value held by Prescaler Register
(PR)
§ In short , TC will increment for every PR+1 clock cycles in PCLK
5.T0TCR (Timer 0 timer control register)
Bit 0 : used to enable or disable the timer.
§ Bit 0 = 1 enables the timer
§ Bit 0 = 0 disables the timer
Bit 1 : used for resetting the Timer Counter and Prescale Counter
§ Bit 1 =1 will reset the TC (Timer Counter) and PC (Prescale Counter) to 0 on the next positive edge of the
PCLK
§ The remaining bits are reserved and should not be modified 50
 Calculations in delay generation using timer

Find the no.of clock counts needed to generate a delay of 1

sec given that the input clock frequency for the timer unit
is 1 kHz

Solution :

Given that TCLK = 1KHz

Time of one clock period (𝑇!" + 𝑇!## ) is calculated as :

$ $
Time of one clock period = %&'(
= $))) = 1𝑚𝑠 ⟹ the delay

required for TC to increment by 1 is 1msec

Required delay to be generated = 1 sec = 𝑛 ∗ time of one

clock period

1
∴n= = 1000
1×10*+

i.e. 1000 clock counts provide a time interval of 1 second 51

 Steps in timer programming

1) Power Up the Timer Peripheral: Ensure that the Timer module is powered by configuring the Power
Control for Peripherals Register (PCONP)

2) Configure the Prescale Register: The Prescale Register (PR) is used to set the timer resolution. By
default, the timer increments every peripheral clock cycle (PCLK), but the Prescale Register is used to
to slow down the counting

3) Configure Timer Control Register (TCR): The TCR (Timer Control Register) controls enabling, disabling,
and resetting the Timer Counter (TC). To enable the timer, set bit 0 of TCR to 1

4) Wait for desired delay: Use the Timer Counter (TC) value to measure the elapsed time ; loop until the
desired count is reached

5) Once the desired count is reached , stop the timer

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 Steps in timer programming

Write an embedded C code to turn ON / turn OFF of an LED connected to P0.10 for every 1 sec. Use timer
0 module and take TCLK = 1 KHz

#include <lpc214x.h>

void initPLL(void); // Setup PLL and Clock Frequency

void initTimer0(void); // Setup and Initialize timer 0 followed by delay generation

int main(void)

initPLL(); //Initialize CPU and Peripheral Clocks @ 60Mhz

IO0DIR = (1<<10); //Configure Pin P0.10 as Output

PCONP|=1<<1 ; // Power on the timer 0 module

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 Steps in timer programming

while(1) void initTimer0(void)

{ {
IO0SET = (1<<10); //Turn ON LED T0CTCR = 0x0; //Set Timer 0 into Timer Mode
void initTimer0(void); T0PR = 59999; //Increment T0TC at every 60000
IO0CLR = (1<<10); //Turn LED OFF clock cycles

void initTimer0(void); T0TCR |=0x00000001 ; //enable the timer

} T0TC =0x00000000 ; //reset the TC register

manually
//return 0;
TOPC = 0x00000000; //reset the PC register
}
manually
while (T0TC < 1000); // Wait for 1 second (1000 ms)
TOTCR &=~(0x00000001) ; // disabling the timer
}

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 Steps in timer programming

void initPLL()
{
PLL0CON=0X01;

PLL0CFG=0X04;
PLL0FEED=0XAA;
PLL0FEED=0X55;
while((PLL0STAT&(0X01<<10))==0);
PLL0CON=0X03;

PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV=0X01;
}

55
 Programming with timer

Practice tasks :
1) Write an embedded C code that turns ON and OFF LEDs connected to P1.16 to P1.19 for every 100ms.The
delay has to be generated using timer 1. Take TCLK = 1 MHz.
2) Write an embedded C code to turn ON and OFF of LEDs connected to P1.16,P.17 and P1.19 for every 500
ms. Take TCLK = 1KHz. The delay has to be generated using timer 1 module.

56
 UART in LPC 2148

§ UART(Universal Asynchronous Receiver/Transmitter)

is a serial communication protocol in which data is
transferred serially bit by bit at a time

§ LPC2148 has two inbuilt UARTs available i.e.

UART0&UART1

UART0 :

§ TXD0 (Output pin): Serial Transmit data pin (P0.0)

§ RXD0 (Input pin): Serial Receive data pin (P0.1)

UART1 :

§ TXD1 (Output pin): Serial Transmit data pin

§ RXD1 (Input pin): Serial Receive data pin

57
 UART in LPC 2148

§ The LPC2148 uses a baud rate clock to generate

a specific communication speed

§ The UART baud rate generator is configured by

dividing the system clock (PCLK) by a specific
divisor value

,&'(
§ -
= 𝐵𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 ∗ 16 = 𝐵𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 𝑐𝑙𝑜𝑐𝑘

§ Baud rate = 9600 ; PCLK = 60 MHz.

.)∗$))))))
§ = 9600 ∗ 16 ; 𝑥 = 390.6 = 3910
-

58
 UART in LPC 2148

§ Therefore, the divisor value (x) = 3910 . The

hexadecimal equivalent of this divisor value has
to be loaded into 16 bit register called
UARTxDivisorLatch Enable (UxDLL). x can either
be 0 or 1 depending upon the UART module used

§ For UART 0 , U0DLL is the Divisor Latch LSB

(least significant byte) and U0DLM is the
Divisor Latch MSB (most significant byte)

59
UART in LPC 2148

60
 Frame structure of UART

START bit: It is a bit with which indicates

that serial communication has started and
it is always low.

Data bits packet: Data bits can be packets of

5 to 9 bits. Normally we use 8 bit data
Frame structure of UART
packet, which is always sent after the
START bit. § Usually, an asynchronous serial communication frame
consists of a START bit (1 bit) followed by a data byte (8
STOP bit: This usually is one or two bits in
bits) and then a STOP bit (1 bit), which forms a 10-bit
length. It is sent after data bits packet to
frame as shown in the figure above
indicate the end of frame. Stop bit is always
logic high. § The frame can also consist of 2 STOP bits instead of a
single bit, and there can also be a PARITY bit after the
STOP bit.

61
Registers associated with UART

Module taken up for study : UART0

Registers associated with UART0 :

§ UART0 line control register (U0LCR)

§ UART0 line status register (U0LSR)

§ UART0 Divisor latch MSB (U0DLM)

§ UART0 Divisor latch LSB (U0DLL)

§ UART0 transmit holding register (U0THR)

§ UART0 receive buffer register (U0RBR)

§ PINSEL register to configure the particular port for UART TX/RX functionality

62
Registers associated with UART

UART0 line control register (U0LCR) :

§ Size of the register : 8 bit

Bit 1:0 - Word Length Select

00 = 5-bit character length U0LCR structure

01 = 6-bit character length Bit 3 - Parity enable

10 = 7-bit character length § 0 = Disable parity generation and checking

11 = 8-bit character length § 1 = Enable parity generation and checking

Bit 2 - Number of stop bits Bit 5:4 - Parity select

§ 0 = 1 stop bit § 00 = Odd Parity

§ 1 = 2 stop bits § 01 = Even Parity

§ 10 = Forced “1” Stick Parity (parity bit is always set to '1’)

§ 11 = Forced “0” Stick Parity (parity bit is always set to ‘0’)

63
Registers associated with UART

UART0 line control register (U0LCR) :

Bit 6 - Break control

§ 0= Disable break transmission

§ 1 = Enable break transmission U0LCR structure

Bit 7 - Divisor Latch Access Bit (DLAB)

§ 0 = Disable access to Divisor Latches

§ 1 = Enable access to Divisor Latches

§ DLAB bit has to be 1 to access the data in U0DLL and U0DLM

§ DLAB bit has to 0 to access the transmit and receive registers of UART

§ Make DLAB = 1 and generate the required baud rate, then make DLAB =
0 and access transmitter and receiver registers of UART0

64
Registers associated with UART

UART0 line status register (U0LSR) :

§ It is an 8-bit read only register.

§ It provides status information on

UART0 RX and TX blocks U0LSR structure
§ Bits of interest : Bit 0 and bit 5
§ In transmission mode (LPC 2148 is the transmitter and PC is
Bit 0 - Receiver Data Ready
the receiver) , the data to be transmitted is there in the U0THR
§ 0 = U0RBR is empty register and it will be transmitted in a bit by bit manner. After
§ 1 = U0RBR contains valid data all the bits are transmitted, U0THR becomes empty

Bit 5 - Transmitter Holding Register § In the reception mode (LPC 2148 is the receiver and PC is the
Empty transmitter), the data that is received by the LPC 2148 is there

§ 0 = U0THR has valid data in the register U0RBR.In this case , Bit 0 of U0LSR will be 1

§ 1 = U0THR empty
65
Registers associated with UART

U0LSR structure

§ Bit 0 - Receiver Data Ready

§ Bit 1 - Overrun Error

§ Bit 2 - Parity Error

§ Bit 3 - Framing Error

§ Bit 4 - Break Interrupt

§ Bit 5 - Transmitter Holding Register Empty

§ Bit 6 - Transmitter Empty

§ Bit 7 - Error in RX FIFO (RXFE)

66
Registers associated with UART
UART0 receive buffer register (U0RBR) :

§ It is an 8-bit read only register

§ This register contains the received data

§ It contains the “oldest” received byte in the receive FIFO U0RBR structure
§ If the character received is less than 8 bits, the unused MSBs are padded
with zeroes.

§ The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to
access the U0RBR. (DLAB = 0)

UART0 Transmit Holding Register (U0THR)

§ It is an 8-bit write only register. U0THR structure

§ Data to be transmitted is written to this register.

§ It contains the “newest” received byte in the transmit FIFO

§ The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to
67
access theU0THR. (DLAB = 0)
 UART transmission
Write an embedded C code to continuously transmit a character from LPC 2148 to PC (UART transmission).Use
UART 0 module and take PCLK = 60 MHz. Required Baud rate = 9600

#include <lpc214x.h>

void initPLL(void); // Setup PLL and Clock Frequency

int main(void)

initPLL(); //Initialize CPU and Peripheral Clocks @ 60Mhz

PINSEL0 | = 0X00000005; // configure P0.0 and P0.1 as TX0 and RX0 pins of UART0

U0LCR = 0x83 ; // 8 bit data,no parity,1 stop bit and DLAB = 1

U0DLL = 0x87;

U0DLM = 0x01;

U0LCR = 0x03 ; // make DLAB = 0 to access U0THR and U0RBR registers

68
 UART transmission
while(1)
{
U0THR = ‘a’; //put the data to be transmitted in U0THR register
while ((U0LSR & (0x01<<5)==0); // check the 5th bit in U0LSR register and see if it is zero or 1. If the 5th bit is 1 , it
tells that the data in U0THR is transmitted completely//
}
void initPLL()
{
PLL0CON=0X01;
PLL0CFG=0X04;
PLL0FEED=0XAA;
PLL0FEED=0X55; while((PLL0STAT&(0X01<<10))==0); PLL0CON=0X03;
PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV=0X01;
69
}
 UART reception
Write an embedded C code to continuously receive a character from PC to LPC 2148 (UART reception).Use UART 0
module and take PCLK = 60 MHz. Required Baud rate = 9600. LPC 2148 will receive a character through PC
terminal and will transmit the same character back to the PC terminal.

#include <lpc214x.h>

void initPLL(void); // Setup PLL and Clock Frequency

unsigned char mydata;

int main(void)

initPLL(); //Initialize CPU and Peripheral Clocks @ 60Mhz

PINSEL0 | = 0X00000005; // configure P0.0 and P0.1 as TX0 and RX0 pins of UART0

U0LCR = 0x83 ; // 8 bit data,no parity,1 stop bit and DLAB = 1

U0DLL = 0x87;

U0DLM = 0x01;
70
U0LCR = 0x03 ; // make DLAB = 0 to access U0THR and U0RBR registers
UART reception
while(1)
{
while((U0LSR & 0x01)==0); //check if the reception is over or not
mydata = U0RBR ;
//transmit the received data back to PC so that the received data can be visualized in the terminal
U0THR = mydata; //put the data to be transmitted in U0THR register
while ((U0LSR & (0x01<<5)==0);
}
void initPLL()
{
PLL0CON=0X01;
PLL0CFG=0X04;
PLL0FEED=0XAA;
PLL0FEED=0X55; while((PLL0STAT&(0X01<<10))==0); PLL0CON=0X03;
PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV=0X01;
} 71
Digital to analog converter (DAC)
§ Digital to Analog Converter (DAC) are mostly used to generate
analog signals (e.g. sine wave, triangular wave etc.) from digital
values

§ LPC2148 has 10 bit DAC (i.e.) the range of digital input is 0 −

1023

§ LPC2148 has Analog output pin (AOUT) on chip, where the

digital value can be observed in the form of analog output
voltage

§ The Analog voltage on AOUT pin is calculated as ((VALUE/1024)

* VREF)

§ The output voltage changes by changing VALUE(10-bit digital

value) field in DACR (DAC Register)

§ Eg. : If the digital value is 512, then, the corresponding analog

voltage on AOUT pin will be ((512/1024) * VREF) = VREF/2
where VREF = 3.3V 72
Digital to analog converter (DAC)
DAC register configuration :

§ DACR is a 32-bit register

§ It is a read-write register

§ Bit 5:0 – RESERVED DACR (DAC Register)

Bits 15:6 – VALUE

§ This field contains the 10-bit digital value that is to be converted

in to analog voltage. The analog output voltage is got out on
AOUT pin and it is calculated with the formula (VALUE/1024) *
VREF.

Bit 16 – BIAS

§ 0 = Maximum settling time of 1µsec and maximum current is

700µA

§ 1 = Settling time of 2.5µsec and maximum current is 350µA

§ Bit 31:17 – RESERVED

73
Digital to analog converter (DAC)
Programming steps:

§ First, configure P0.25/AOUT pin as DAC output using PINSEL register

§ Then set settling time using BIAS bit in DACR register

§ Write the 10-bit digital value (which has to be converted into analog form) in
VALUE field of DACR register

74
Digital to analog converter (DAC)
1) Write an embedded C code to generate a triangular waveform using
DAC of LPC 2148
for (i=1023 ; i>=0;i--)
#include <lpc214x.h>
{
void delay () ;
DACR = i<<6;
int main(void)
delay();
{
}
int i,j;
}
PINSEL1 |= (1<<19); //Select AOUT function for P0.25. bits[19:18] = [1 0]
}
DACR = 0;
void delay ()
while(1)
{
{
for (j=0;j<=50000;j++)
for (i=0 ; i< 1024 ; i++)
}
{
DACR = i<<6;
delay();
75
}
Digital to analog converter (DAC)
2) Write an embedded C code to generate a sawtooth waveform of frequency 50
Hz with 100 samples using DAC of LPC 2148. Take TCLK = 1 MHz and PCLK =
One
60MHz. Use timer 0 for delay generation sawtooth
cycle
Solution :

7
Given that f = 50 Hz ⟹ 𝑇 = = 20 𝑚𝑠
8
20ms
Duration of one sawtooth cycle = 20 ms and this one sawtooth cycle is sliced into
100 samples

9:×7:!"
100 samples = 20 ms ⟹ 1 sample = = 200𝜇𝑠𝑒𝑐
7::

∴ The time interval between each sample = 200𝜇𝑠𝑒𝑐

This 200𝜇𝑠𝑒𝑐 delay should be generated using timer 0

§ In the code, the for loop should start from 0 and end in 99 since the no.of
samples =100 ; In order to use the full bandwidth of 0 – 1023 , each digital
value is multiplied by 10 so that 100 samples will cover the entire 0 – 1023
76
span
Digital to analog converter (DAC)
#include <lpc214x.h>
void initPLL(void); // Setup PLL and Clock Frequency
void init_timer(void);
int main(void)
{
initPLL(); // to set the PCLK = 60 MHz for timer
PINSEL1 |= (1<<19); //Select AOUT function for P0.25. bits[19:18] = [1 0]
DACR = 0;
unsigned int step = 1023/100 ;
while(1)
{
for (i=0 ; i< 100 ; i++)
{
DACR = (i*step) <<6;
init_timer(); 77
Digital to analog converter (DAC)
DACR = 0; // Set DAC output to 0 while (T0TC < 200); // Wait for 200 𝜇𝑠𝑒𝑐 delay
init_timer(); // Small delay for the falling edge TOTCR &=~(0x00000001) ; // disabling the timer
} }
} void initPLL()
void init_timer(void) {
{ PLL0CON=0X01;
T0CTCR = 0x0; //Set Timer 0 into Timer Mode PLL0CFG=0X04;
T0PR = 59; //Increment T0TC at every 6 clock PLL0FEED=0XAA;
cycles
PLL0FEED=0X55;
T0TCR |=0x00000001 ; //enable the timer
while((PLL0STAT&(0X01<<10))==0);
T0TC =0x00000000 ; //reset the TC register
PLL0CON=0X03;
manually
PLL0FEED=0XAA;
TOPC = 0x00000000; //reset the PC register
manually PLL0FEED=0X55;
VPBDIV=0X01;
78
}
Digital to analog converter (DAC)
3) Write an embedded C code to generate a triangular waveform of frequency 50 Hz
with 100 samples using DAC of LPC 2148. Take TCLK = 1 MHz and PCLK = 60MHz. Use
One
timer 0 for delay generation 10ms triangular
wave cycle
Solution :
10ms
7
Given that f = 50 Hz ⟹ 𝑇 = = 20 𝑚𝑠
8
20ms
Duration of one triangular cycle = 20 ms and this one cycle is sliced into 100
§ Out of the total 100
samples
samples for one cycle , 50
§ Out of the total 100 samples for one cycle , 50 samples are used for generating the samples are used for
generating the rising edge
rising edge and 50 samples are used for generating the falling edge of the and 50 samples are used
for generating the falling
triangular wave
edge of the triangular
§ Rising edge duration = falling edge duration = Duration of one cycle /2 ⟹ Rising wave

edge duration = falling edge duration is 10 ms

§ 50 samples covers 10 ms duration ⟹ 1 sample = 200𝜇𝑠𝑒𝑐

§ This 200𝜇𝑠𝑒𝑐 delay should be generated using timer 0

79
§ Step = 1023/50
Digital to analog converter (DAC)
#include <lpc214x.h>
void initPLL(void); // Setup PLL and Clock Frequency
void init_timer(void);
int main(void)
{
initPLL(); // to set the PCLK = 60 MHz for timer
PINSEL1 |= (1<<19); //Select AOUT function for P0.25. bits[19:18] = [1 0]
DACR = 0;
unsigned int step = 1023/50 ;
while(1)
{
for (i=0 ; i< 50 ; i++)
{
DACR = (i*step) <<6;
init_timer(); 80
Digital to analog converter (DAC)
for(i=49 ; i>=0;i--) while (T0TC < 200); // Wait for 200 𝜇𝑠𝑒𝑐 delay
{ TOTCR &=~(0x00000001) ; // disabling the timer
DACR = (i*step)<<6; }
init_timer(); // Small delay for the falling edge void initPLL()
} {
}
PLL0CON=0X01;
void init_timer(void)
PLL0CFG=0X04;
{
PLL0FEED=0XAA;
T0CTCR = 0x0; //Set Timer 0 into Timer Mode
PLL0FEED=0X55;
T0PR = 59; //Increment T0TC at every 6 clock
while((PLL0STAT&(0X01<<10))==0);
cycles
PLL0CON=0X03;
T0TCR |=0x00000001 ; //enable the timer
PLL0FEED=0XAA;
T0TC =0x00000000 ; //reset the TC register
PLL0FEED=0X55;
manually
VPBDIV=0X01;
TOPC = 0x00000000; //reset the PC register 81
manually }
Digital to analog converter (DAC)
4) Write an embedded C code to generate a square waveform of frequency 50 Hz with 100 samples using
DAC of LPC 2148. Take TCLK = 1 MHz and PCLK = 60MHz. Use timer 0 for delay generation

Solution :

7
Given that f = 50 Hz ⟹ 𝑇 = = 20 𝑚𝑠
8

Duration of one cycle = 20 ms and this one cycle is sliced into 100 samples (50 samples for 𝑇<= and 50
samples for 𝑇<>> )

7:×7:!"
50 samples = 10 ms ⟹ 1 sample = = 200𝜇𝑠𝑒𝑐
?:

∴ The time interval between each sample = 200𝜇𝑠𝑒𝑐

This 200𝜇𝑠𝑒𝑐 delay should be generated using timer 0

82
Digital to analog converter (DAC)
#include <lpc214x.h>
void initPLL(void); // Setup PLL and Clock Frequency
void init_timer(void);
int main(void)
{
initPLL(); // to set the PCLK = 60 MHz for timer
PINSEL1 |= (1<<19); //Select AOUT function for P0.25. bits[19:18] = [1 0]
DACR = 0;
while(1)
{
DACR = 0<<6;
init_timer();

83
Digital to analog converter (DAC)
DACR = 1023 <<6; while (T0TC < 200); // Wait for 200 𝜇𝑠𝑒𝑐 delay
init_timer(); TOTCR &=~(0x00000001) ; // disabling the timer
} }
} void initPLL()
void init_timer(void) {
{ PLL0CON=0X01;
T0CTCR = 0x0; //Set Timer 0 into Timer Mode PLL0CFG=0X04;
T0PR = 59; //Increment T0TC at every 6 clock PLL0FEED=0XAA;
cycles
PLL0FEED=0X55;
T0TCR |=0x00000001 ; //enable the timer
while((PLL0STAT&(0X01<<10))==0);
T0TC =0x00000000 ; //reset the TC register
PLL0CON=0X03;
manually
PLL0FEED=0XAA;
TOPC = 0x00000000; //reset the PC register
manually PLL0FEED=0X55;
VPBDIV=0X01;
84
}
 Interrupts in LPC 2148
§ An interrupt is a signal sent to the CPU which indicates
that a system event has a occurred which needs
immediate attention“

§ An ‘Interrupt ReQuest‘ i.e an ‘IRQ‘ can be thought of as a

special request to the CPU to execute a function(small
piece of code) when an interrupt occurs. This function
or ‘small piece of code’ is technically called an
‘Interrupt Service Routine‘ or ‘ISR‘

§ So when an IRQ arrives to the CPU , it stops executing

the code current code and start executing the ISR

§ After the ISR execution has finished the CPU gets back
to where it had stopped

85
 Interrupts in LPC 2148
How the interrupt works ?

§ Whenever any device needs service of microcontroller, the device notifies the microcontroller by sending
interrupt signal

§ Upon receiving an interrupt signal, the microcontroller stops or interrupt main program flow and saves
the address of the next instruction (PC) on the stack pointer (SP)

§ It jumps to a fixed location in memory, called interrupt vector table that hold the address of the ISR
(Interrupt Service Routine). Each interrupt has its own ISR. The microcontroller gets the address of the ISR
from the interrupt vector table and jump to it.

§ It starts to execute the Interrupt Service Routine until it reaches the last instruction of the subroutine

§ Upon executing last instruction in Interrupt Service Routine the microcontroller returns to the place where
it left off or interrupted previously

§ First, it gets the program counter (PC) address from the stack pointer by popping the top 4 bytes of the
stack into the PC

§ Then it starts to execute from that address and continue executing main program
86
 Interrupts in LPC 2148
§ There are two types of interrupts : (a) FastIRQs or FIQs (b) Normal
IRQs or IRQs. Normal IRQs can be further classified as : (a)
Vectored IRQ and (b) Non-Vectored IRQ

§ Interrupts are handled by Vectored Interrupt Controller(VIC)

Types of Interrupts in LPC2148

§ FastInterruptRequest i.e. FIQ :which has highest priority

§ Vectored Interrupt Request i.e VectoredIRQ which has ‘middle’ or

priority between FIQ and Non-Vectored IRQ

§ Non-VectoredIRQ which has the lowest priority

87
 Interrupts in LPC 2148
§ Vectored means that the CPU is aware of the address of the ISR when the interrupt occurs

§ Non-Vectored means that CPU doesn’t know the address of the ISR (nor) the source of the IRQ when the
interrupt occurs

§ For Non – Vectored interrupts , CPU needs to be supplied by the ISR address

§ For the Vectored interrupts , the system internally maintains a table called IVT or Interrupt Vector Table
which contains the information about Interrupts sources and their corresponding ISR address

Handling of non – vectored interrupts :

§ Non-Vectored ISRs doesn’t point to a unique ISR

§ The CPU needs to be supplied with the address of the ‘default’ or a ‘common’ ISR that needs to be executed
when the interrupt occurs

§ In LPC2148, this is facilitated by a register called ‘VICDefVectAddr‘

§ The user must assign the address of the default ISR to this register for handling Non-Vectored IRQs

88
 Interrupts in LPC 2148
§ Vectored means that the CPU is aware of the address of the ISR when the interrupt occurs

§ Non-Vectored means that CPU doesn’t know the address of the ISR (nor) the source of the IRQ when the
interrupt occurs

§ For Non – Vectored interrupts , CPU needs to be supplied by the ISR address

§ For the Vectored interrupts , the system internally maintains a table called IVT or Interrupt Vector Table
which contains the information about Interrupts sources and their corresponding ISR address

Handling of non – vectored interrupts :

§ Non-Vectored ISRs doesn’t point to a unique ISR

§ The CPU needs to be supplied with the address of the ‘default’ or a ‘common’ ISR that needs to be executed
when the interrupt occurs

§ In LPC2148, this is facilitated by a register called ‘VICDefVectAddr‘

§ The user must assign the address of the default ISR to this register for handling Non-Vectored IRQs

89
 Interrupts in LPC 2148
VICIntSelect (R/W) :

90
 Interrupts in LPC 2148
VICIntEnable (R/W) :

§ This is used to enable interrupts

§ Writing a 1 at a given bit location will make the corresponding interrupt Enabled

§ Writing 0′s has no effect

VICIntEnClr (R/W) :

§ This register is used to disable interrupts

§ This is similar to VICIntEnable expect writing a 1 here will disabled the corresponding Interrupt

§ This has an effect on VICIntEnable since writing at a specific bit location will clear the corresponding bit in
the VICIntEnable register

§ Writing 0′s has no effect

91
 Interrupts in LPC 2148
VICIRQStatus (R) :

§ This register is used for reading the current status of the enabled IRQ interrupts

§ If a bit location is read as 1 then it means that the corresponding interrupt is enabled and active

VICFIQStatus (R) :

§ This register is used for reading the current status of the enabled FIQ interrupts

§ If a bit location is read as 1 then it means that the corresponding interrupt is enabled and active

VICSoftInt :

§ This register is used to generate interrupts using software i.e manually generating interrupts using code

§ If the value written to any bit location is 1, then, the correspoding interrupt is triggered i.e. it forces the
interrupt to occur

§ Writing 0 here has no effect

VICSoftIntClear:

§ This register is used to clear the interrupt request that was triggered(forced) using VICSoftInt.

§ Writing a 1 will release(or clear) the forcing of the corresponding interrupt. 92

 Interrupts in LPC 2148
Vector Address Registers (VICVectAddr0 – VICVectAddr15):

§ Vector Address Registers are used to hold the addresses of the ISR of the 16 Vectored IRQ slots

§ If Slot 0 (VICVectCntl0) is assigned to TIMER0 IRQ, then the address for the interrupt function must be
assigned to VICVectAddr0.

Default Vector Address Register (VICDefVectAddr):

§ Default Vector Address Register holds the address of the ISR for Non – Vectored IRQs

§ This address acts as the default or common ISR address when a Non – Vectored IRQ occurs

Vector Address Register (VICVectAddr):

§ This is a different and single register and must not be confused with Vector Address Registers
(VICVectAddr0 – VICVectAddr15)

§ It is a read / write register and when the data is read from this register, it returns address of ISR

§ Writing a value to this register indicates the VIC that the execution of the current interrupt is finished.
Hence, this register is written with a dummy value at the end of the ISR to indicate the end of execution.

93
 Interrupts in LPC 2148
Vectored Interrupt Controller (VIC) Vectored Interrupt Controller (VIC)
§ There are 22 Interrupt Sources in LPC2148

§ But there are only 16 Slots in in the Vectored Interrupt Controller

(VIC) −slot 0 to slot 15 (VICVectCnt0 – VICVectCnt15)

§ These 22 possible sources have to be shared by using slots 0 to

15 of VIC

§ Slot 0 has the highest priority

§ Slot 15 has the lowest priority

Interrupt sources in LPC 2148

94
Interrupts in LPC 2148

95
Interrupts in LPC 2148

96
 Interrupts in LPC 2148
How to write the ISR ?

97
 Interrupts in LPC 2148
Three steps process to enable vectored IRQ :

98
 Interrupts in LPC 2148
Assign TIMER0 IRQ and the corresponding ISR to Slot 0.

§ Enable the TIMER0 IRQ (using VICIntEnable Register)

§ Allocate Slot 0 to TIMER0 IRQ (using one of the VICVectCntl0 – 15 Registers)

§ Assign the ISR Address (using one of the VICVectAddr0 – 15 Registers

Based on the above steps, the following assignments must be made to setup the interrupt.

§ VICIntEnable | = (1<<4); // 4 is the timer 0 interrupt source number

§ VICVectCntl0 = (1<<5) | 4; // To enable timer 0 interrupt

§ VICVectAddr0 = (unsigned) userISR; userISR is the name of the ISR

99
 Interrupts in LPC 2148
Match registers :

§ The match registers (like T0MR0, T0MR1, etc.) specify the value at which Timer 0 generates an event.

§ When the timer counter (T0TC) reaches a match value (such as in T0MR0), it triggers a specific action like
setting a flag, generating an interrupt, or resetting the timer counter.

§ To use a match register for delay, set T0MR0 to the calculated value for the desired delay based on PCLK
and the prescaler

100
 Interrupts in LPC 2148
T0IR (Timer 0 interrupt register)

§ T0IR is used to clear interrupt flags generated by match events in Timer 0.

§ When a match occurs (for example, Timer 0 Counter matches a value in MR0), an interrupt flag is set.
Writing a 1 to the respective bit in T0IR clears this flag, acknowledging the interrupt and allowing new
interrupts to be triggered
§ Bits in T0IR correspond to match registers (MR0 to MR3) and capture registers, allowing for individual
clearing of each interrupt flag
101
 Interrupts in LPC 2148
TOMCR (Timer 0 match control register) : § T0MCR configures actions for match events
on each of Timer 0's match registers (MR0 to
MR3).
The bits in T0MCR control:
§ Whether an interrupt should be generated
when a match occurs.
§ Whether the timer counter (T0TC) should
reset upon a match, allowing for repeated
timing intervals.
§ Whether Timer 0 should stop on a match,
which can be useful for single-shot timing
operations.
§ Each match register has three associated bits
in T0MCR to control the behavior (interrupt
generation, reset, and stop).
102
 Interrupts in LPC 2148
Blink LED connected to P0.10 when interrupt is generated after every 0.5 Sec. Take PCLK = 60MHz and TCLK =
1KHz

include <lpc214x.h>
void initClocks(void);
void initTimer0(void);
__irq void timer0ISR(void);
int main(void)
{
initClocks(); // Initialize PLL to setup clocks
initTimer0(); // Initialize Timer0
IO0DIR = (1<<10); // Configure pin P0.10 as Output
IO0PIN = (1<<10);
T0TCR = (1<<0); // Enable timer
while(1); // Infinite Idle Loop
}
103
Interrupts in LPC 2148

void initTimer0(void)
{
T0CTCR = 0x0; //Set Timer Mode
T0PR = 60000-1; //Increment T0TC at every 60000 clock cycles
//60000 clock cycles @60Mhz = 1 mS
T0MR0 = 500-1; //Zero Indexed Count-hence subtracting 1
T0MCR = (1<<0) | (1<<1);//Set bit0 & bit1 to Interrupt & Reset TC on MR0
VICVectAddr4 = (unsigned )timer0ISR; //Pointer Interrupt Function (ISR)
VICVectCntl4 = (1<<5) | 4; //(bit 5 = 1)->to enable Vectored IRQ slot
//bit[4:0]) -> this the source number
VICIntEnable = (1<<4); // Enable timer0 interrupt
T0TCR = (1<<1); // Reset Timer
}

104
Interrupts in LPC 2148

_irq void timer0ISR(void)

{
long int readVal; while(!(PLL0STAT & 0x00000400));
readVal = T0IR; // Read current IR value PLL0CON = 0x03; //Connect PLL
if((readVal & 0x01)==1)) after PLL is locked
{ PLL0FEED = 0xAA; //Feed
IO0PIN ^= (1<<10); // Toggle LED at Pin P0.10 sequence
T0IR = readVal; // Write back to IR to clear Interrupt Flag PLL0FEED = 0x55;
VICVectAddr = 0x0; // End of interrupt execution VPBDIV = 0x01; //PCLK is same
} as CCLK i.e.60 MHz
void initClocks(void) }
{
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x04; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
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PLL0FEED = 0x55;
 Interrupts in LPC 2148
Design a LPC2148 based system to perform the following tasks :

Task1 : Blink an LED at P1.31 using software delay.

Task2 : Generate a square wave at 1KHz @ P1.25 using Timer0 Match Interrupt

106