Imp.

Terminology

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Bit-0
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Nibble-0000 (4bits)
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Byte-0000 0000 (8bits)
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Word-0000 0000 0000 0000 (16bits / 2bytes)

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Imp. Terminology

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1 Kilobyte (1KB)– 210 bytes – 1024 bytes
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1 Megabyte (1MB) – 220 bytes - 1,048,576
bytes – 1024 KB
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1 Gigabyte (1GB) – 240 bytes – 1024 MB

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Internal organization of a Computer

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Internal organization of a Computer

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The internal working of every computer can
be broken down into three parts:
– CPU (central processing unit)
– Memory
– Input/Output devices

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Internal organization of a Computer

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Memory characteristics
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Memory capacity
– number of bits that a semiconductor memory chip can
store is called chip capacity
– units of Kb, Mb
– Memory capacity of an IC – bits (Kb, Mb)
– Memory capacity of the computer system– bytes
(KB, MB)

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Memory organization
●
Memory chips are organized into a number of locations
within the IC
– Each location can hold
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1 bit,
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4 bits,
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8 bits, or even 16 bits, depending on how it is
designed internally

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Memory organization
●
the number of bits that each location within the memory
chip can hold is always equal to the number of data pins
on the chip
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How many locations exist inside a memory chip?
– depends on the number of address pins
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the number of locations within a memory IC always
equals 2 to the power of the number of address
pins

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Memory organization

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A memory chip contains 2x locations, where x is the number
of address pins
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Each location contains y bits, where y is the number of data
pins on the chip
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The entire chip will contain 2x * y bits, where x is the
number of address pins and y is the number of data pins on the
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Memory organization

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A0–A10 - address inputs
– where 11 address lines gives 211 = 2K
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I/O0–I/O7 are for data I/O
– where 8-bit data lines give an
organization of 2K × 8
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WE (write enable)
– for writing data into SRAM (active low)
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OE (output enable)
– for reading data out of SRAM (active low)
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CS (chip select)
– used to select the memory chip

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Memory organization
●
A given memory chip has 12 address pins and 4 data pins.
– Find:
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(a) the organization, and
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(b) the capacity
– (a) This memory chip has 4,096 locations (212 = 4,096), and
each location can hold 4 bits of data
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This gives an organization of 4,096 × 4, often
represented as 4K × 4
– The capacity is equal to 16K bits since there is a total of 4K
locations and each location can hold 4 bits of data

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Commonly used memory

●
RAM – Random Access Memory
●
used by the computer for temporary
storage of programs that it is running
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data is lost when the computer is turned
off
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Hence, RAM is called volatile memory

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Commonly used memory

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ROM – Read-Only Memory
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contains programs and information
essential to operation of the computer
●
information in ROM is permanent,cannot
be changed by the user, and is not lost
when the power is turned off
– hence, ROM is called nonvolatile
memory

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Internal organization of a Computer

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 Internal organization of a Computer

●
the CPU needs to send/receive
data to/from memory and I/O
●
connecting the devices
(memory or I/O) to the CPU
with unique wires increases
the number of CPU pins
●
therefore, the CPU is connected
to memory and I/O through
shared strips of wire called the
bus

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Internal organization of a Computer
●
A computer bus allows
information to be
carried from place to
place just as a street
allows cars to carry
people from place to
place

●
there are three types
of buses in every
computer:
●
address bus,
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data bus, and
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control bus
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Data bus
●
data buses are used to carry information in and out
of a CPU
– more the data buses available, the better the CPU
– if one thinks of data buses as highway lanes, it is
clear that more lanes provide a better pathway
between the CPU and its external devices
– increase in the number of lanes increases the cost
of construction
●
more data buses mean a more expensive CPU
and computer

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Data bus
●
the average size of data buses in CPUs varies
between 8 and 64 bits
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Data buses are bidirectional because the CPU must
use them either to receive or to send data
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The processing power of a computer is related to the
size of its buses
– 8-bit bus can send out one byte at a time,
– but a 16-bit bus can send out two bytes at a time,
which is twice as fast

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Address bus
●
address bus is used to identify the devices and
memory connected to the CPU
– more address buses available, the larger the
number of devices that can be addressed
– the number of address buses for a CPU
determines the number of locations with which it
can communicate
– the number of locations is always equal to 2x
●
where x is the number of address lines,
regardless of the size of the data bus
●
for example, a CPU with 16 address lines can
provide a total of 65,536 (216 ) or 64K of
addressable memory
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Address bus
●
each location can have a maximum of 1 byte of data
●
this is because all general-purpose
microprocessor CPUs are what is called byte
addressable
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The address bus is a unidirectional bus, which
means that the CPU uses the address bus only to
send out addresses

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Control bus
●
used by CPU for communicating with other devices
within the computer
●
there are separate control signals for I/O and
memory
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eg: MEMR (memory read), MEMW (memory
write), IOR (IO read), and IOW (IO write)
– to read from memory, the CPU enables
MEMR
– in order to read from I/O, CPU activates the
IOR etc.,

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Internal organization of a Computer

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CPU architecture
●
to perform an action (any calculation, controlling a
device) specified by a program stored in the
memory, the CPU:
●
fetch these instructions from memory and
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execute them
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to perform the actions of fetch and execute, the CPU
needs particular hardware resources

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CPU architecture

Block diagram of a CPU

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 CPU architecture: Registers
●
Registers:
– CPU uses registers to store information temporarily
– the information could be:
●
two values to be processed,
●
or the address of the value needed to be fetched from
memory
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can be of size 8-bit, 16-bit, 32-bit, or even 64-bit registers,
depending on the CPU

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 CPU architecture: Registers
●
Registers:
– CPU uses registers to store information temporarily
– the information could be:
●
two values to be processed,
●
or the address of the value needed to be fetched from
memory
●
can be of size 8-bit, 16-bit, 32-bit, or even 64-bit registers,
depending on the CPU
●
the disadvantage of more and bigger registers is the increased
cost of such a CPU

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CPU architecture: ALU
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Arithmetic/Logic Unit (ALU)
– responsible for performing arithmetic functions
such as add, subtract, multiply, and divide,
– and logic functions such as AND, OR, and NOT

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CPU architecture: Program Counter(PC)
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Program Counter (PC)
– always points to the address of the next
instruction to be executed
– after the execution of an instruction, the value of
the PC increased to point to the address of the
next instruction to be executed

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CPU architecture: Instruction Decoder
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Instruction decoder
– interpret the instruction fetched into the CPU
– a kind of dictionary:
●
storing the meaning of each instruction and
what steps the CPU should take upon receiving
a given instruction
– a CPU capable of understanding more instructions
requires more transistors to design

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CPU architecture: Instruction Decoder
●
Instruction decoder
– interpret the instruction fetched into the CPU
– a kind of dictionary:
●
storing the meaning of each instruction and
what steps the CPU should take upon receiving
a given instruction
– a CPU capable of understanding more instructions
requires more transistors to design

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Steps of Instruction Process

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Harvard and von Neumann
architectures
●
every microprocessor must have memory space
to store program (code) and data
●
while code provides instructions to the CPU
– the data provides the information to be
processed
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the CPU uses buses (wire traces) to access the
code ROM and data RAM memory spaces

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Harvard and von Neumann
architectures
●
the early computers used the same bus for
accessing both the code and data
– von Neumann (Princeton) architecture
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requires only one memory for their code and
data
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the process of accessing the code or data could
cause them to get in each other’s way
– and slow down the processing speed of the
CPU, because each had to wait for the other to
finish fetching

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Harvard and von Neumann
architectures
●
to speed up the process of program execution,
some CPUs use what is called Harvard
architecture
●
in Harvard architecture, there are separate buses
for the code and data memories
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Harvard and von Neumann
architectures

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Harvard and von Neumann
architectures

●
Which one is better?

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