HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

SCHOOL OF ELECTRONICS AND TELECOMMUNICATIONS

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FINAL TERM PROJECT REPORT

Name of instructor: Assoc. Prof, PhD Hoàng Mạnh Thắng
Name of students:
Đào Xuân Bách MSSV: 20224356
Hàn Ngọc Minh MSSV: 20224373

Hanoi, 2025
Foreword
This final project for Digital Electronics 1 highlights the knowledge and skills acquired throughout the
semester. It integrates theoretical concepts with practical implementation, focusing on finite state
machines (FSM), sequential circuits, state minimization, and optimization techniques to deepen
understanding of key principles in digital electronics.

The primary objective of this project is to design, analyze, and simulate a sequential circuit capable of
detecting specific bit sequences using Flip-Flops, which serves as the topic for the final term project for the
non-specialized section.

We would like to express our sincere gratitude to our instructor, Assoc. Prof., Ph.D. Hoang Manh Thang,
and our team members for their invaluable support and contributions, which have been essential to the
successful completion of this project. While every effort was made to ensure accuracy, we acknowledge
that errors may still exist in this report and welcome constructive feedback from our instructor.

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Contents
Foreword ........................................................................................................................................................................... 2
Contents ............................................................................................................................................................................ 3
A. Introduction: ........................................................................................................................................................ 4
1. Task requirement: ................................................................................................................................................ 4
2. Specification requirements: ................................................................................................................................. 4
B. Design task: .......................................................................................................................................................... 4
1. Finite state machines (FSM): ................................................................................................................................ 4
2. State table: ........................................................................................................................................................... 5
3. Minimizing the partitions ..................................................................................................................................... 5
4. Encoding states..................................................................................................................................................... 7
5. Encoding table in binary: ...................................................................................................................................... 7
6. Excitation table: .................................................................................................................................................... 7
7. Truth table for minimizing functions: ................................................................................................................... 7
8. Functions after minimizing: .................................................................................................................................. 8
9. Circuit simulation on Proteus: .............................................................................................................................. 8
C. Analysis task:........................................................................................................................................................ 9
1. Designed electronic circuit ................................................................................................................................... 9
2. Functions: ...........................................................................................................................................................10
3. Excitation table: ..................................................................................................................................................10
4. Encoding table: ...................................................................................................................................................10
5. Encoding states in binary:...................................................................................................................................11
6. States table: ........................................................................................................................................................11
7. Minimizing the amount of states: ......................................................................................................................11
8. Finite State Machine:..........................................................................................................................................11
9. Discuss the differences: ......................................................................................................................................12
D. Practical circuit: ..................................................................................................................................................12
1. Component preparation .....................................................................................................................................12
2. Real Circuit:.........................................................................................................................................................14
Conclusion........................................................................................................................................................................17

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A. Introduction:
1. Task requirement:
a. Design task: Design a sequential circuit (with at least 5 states) to detect a bit sequence input W if
one of the two bit groups appears at the input. These bit groups have different lengths (e.g., 2 bits
and 5 bits, or 3 bits and 4 bits). In this design, the steps should include state minimization and
optimization through adjacent state encoding. Then, simulate and implement the circuit
b. Analysis task: Analyze the designed electronic circuit above, identify the minimized states, and
draw the state transition diagram of the final design. Then compare and discuss the differences in
the state transition diagram obtained from the analysis and the one in the original design.
2. Specification requirements:
a. Input 𝑤: A sequential input bit stream (1 bit at each time step).
b. Output 𝑧:
- 𝑧 = 1 if one of the two specified bit patterns is detected in the input stream.
- 𝑧 = 0 otherwise.
c. Clock (CLK): Input clock signal to control the sequential circuit.
d. Reset (RESET’): Resets the circuit’s state to its initial state.
e. Target bit input to detect:
101
𝑤=[ →𝑧=1
0101
f. Type of Sequential Circuit:
- Use All Flip-Flops D to store states.
- Moore FSM: The output 𝑧 depends only on the current state.
g. Power Consumption: Use a 5V power supply from the Arduino UNO

B. Design task:
- Input sequence:
101
𝑤=[ →𝑧=1
0101
1. Finite state machines (FSM):
- Suppose the initial state is A, when 𝑤 = 0 then the circuit does nothing with 𝑧 = 0
- Moore FSM:

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- Structure of a Moore Finite State Machine:
• State: Represents a specific condition of the system.
• Input: Signal or data provided to control the system.
• Output: Determined based on the current state.
• State Transition: Describes the transition between states when a specific input is received
- Characteristics of a Moore Finite State Machine:
• Output is determined by the current state and does not directly depend on the input.
• Each state can have a fixed output.
2. State table:
Next
Present 𝑧
𝑤=0 𝑤=1
𝐴 𝐸 𝐵 0
𝐵 𝐶 𝐵 0
𝐶 𝐸 𝐷 0
𝐷 𝐶 𝐵 1
𝐸 𝐸 𝐹 0
𝐹 𝐺 𝐵 0
𝐺 𝐸 𝐻 0
𝐻 𝐺 𝐵 1
3. Minimizing the partitions

− 𝑃1 = (𝐴𝐵𝐶𝐷𝐸𝐹𝐺𝐻)

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−𝑃2 = (𝐴𝐵𝐶𝐸𝐹𝐺)(𝐷𝐻)
0−successor
→ (𝐸𝐶𝐸𝐸𝐺𝐸)
(𝐴𝐵𝐶𝐸𝐹𝐺) 1−successor → (𝐴𝐵𝐸𝐹)(𝐶𝐺)
→ (𝐵𝐵𝐷𝐹𝐵𝐻)
0−successor
→ (𝐶𝐺)
(𝐷𝐻) 1−successor → same block
→ (𝐵𝐵)

−𝑃3 = (𝐴𝐵𝐸𝐹)(𝐶𝐺)(𝐷𝐻)
0−successor
→ (𝐸𝐶𝐸𝐺)
(𝐴𝐵𝐸𝐹) 1−successor → (𝐴𝐸)(𝐵𝐹)
→ (𝐵𝐵𝐹𝐵)
0−successor
→ (𝐸𝐸)
(𝐶𝐺) 1−successor → same block
→ (𝐷𝐻)
0−successor
→ (𝐶𝐺)
(𝐷𝐻) 1−successor → same block
→ (𝐵𝐵)

−𝑃4 = (𝐴𝐸)(𝐵𝐹)(𝐶𝐺)(𝐷𝐻)
0−successor
→ (𝐸𝐸)
(𝐴𝐸) 1−successor → same block
→ (𝐵𝐹)
0−successor
→ (𝐶𝐺)
(𝐵𝐹) 1−successor → same block
→ (𝐵𝐵)
0−successor
→ (𝐸𝐸)
(𝐶𝐺) 1−successor → same block
→ (𝐷𝐻)
0−successor
→ (𝐶𝐺)
(𝐷𝐻) 1−successor → same block
→ (𝐵𝐵)

→ Therefore, we would replace state 𝐴 for state 𝐸, state 𝐵 for state 𝐹, state 𝐶 for state 𝐺, state 𝐷 for
state 𝐻

- New encoding table:

Next
Present 𝑧
𝑤=0 𝑤=1
𝐴 𝐴 𝐵 0
𝐵 𝐶 𝐵 0
𝐶 𝐴 𝐷 0

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 𝐷 𝐶 𝐵 1

4. Encoding states
- States have the same next state: {𝐴, 𝐶}, {𝐵, 𝐷}, {𝐴, 𝐵, 𝐷}
- States are the same next state of previous state: {𝐴, 𝐵}, {𝐶, 𝐵}, {𝐴, 𝐷}
- States have the same output corresponding to the input: {𝐴, 𝐵, 𝐶}
- K-map encoding:

0 1

0 𝐴 𝐶
1 𝐵 𝐷
- Encoding states in binary:
𝐴 00
𝐵 10
𝐶 01
𝐷 11
5. Encoding table in binary:
Next
Present 𝑧
𝑤=0 𝑤=1
00 00 10 0
10 01 10 0
01 00 11 0
11 01 10 1
6. Excitation table:
Next
Present
𝑤=0 𝑤=1 𝑧
𝑄1 𝑄2 𝑄1+ 𝑄2+ 𝐷1 𝐷2 𝑄1+ 𝑄2+ 𝐷1 𝐷2
00 00 00 10 10 0
01 00 00 11 11 0
10 01 01 10 10 0
11 01 01 10 10 1
7. Truth table for minimizing functions:
a. Calculating 𝐷1 , 𝐷2
𝑤 𝑄1 𝑄2 𝐷1 𝐷2 𝑚
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 2

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 0 1 1 0 1 3
1 0 0 1 0 4
1 0 1 1 1 5
1 1 0 1 0 6
1 1 1 1 0 7
b. Calculating 𝑧:
𝑄1 𝑄2 𝑧
0 0 0
0 1 0
1 0 0
1 1 1
8. Functions after minimizing:
𝑫𝟏 = 𝒇(𝑸𝟐 , 𝑸𝟏 , 𝒘) = 𝒘
𝑫𝟐 = 𝒇(𝑸𝟐 , 𝑸𝟏 , 𝒘) = 𝒘′ 𝑸𝟏 + 𝒘𝑸′𝟏 𝑸𝟐
𝒛 = 𝒇(𝑸𝟐 , 𝑸𝟏 ) = 𝑸𝟏 𝑸𝟐
9. Circuit simulation on Proteus:
- 𝑫𝟏

𝑫𝟏 = 𝒘

- 𝑫𝟐

𝑫𝟐 = 𝒘′ 𝑸𝟏 + 𝒘𝑸′𝟏 𝑸𝟐

- 𝒛

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 𝒛 = 𝒇(𝑸𝟐 , 𝑸𝟏 ) = 𝑸𝟏 𝑸𝟐
- Full circuit:
• Using NE555 for providing CLK for Flip-flop
• RESET’ at 0: The circuit’s state will go back to A as an initial state

C. Analysis task:
1. Designed electronic circuit
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2. Functions:
𝑫𝟏 = 𝒇(𝑸𝟐 , 𝑸𝟏 , 𝒘) = 𝒘
𝑫𝟐 = 𝒇(𝑸𝟐 , 𝑸𝟏 , 𝒘) = 𝒘′ 𝑸𝟏 + 𝒘𝑸′𝟏 𝑸𝟐
𝒛 = 𝒇(𝑸𝟐 , 𝑸𝟏 ) = 𝑸𝟏 𝑸𝟐
3. Excitation table:
Next
Present
𝑤=0 𝑤=1 𝑧
𝑄1 𝑄2 𝐷1 𝐷2 𝑄1+ 𝑄2+ 𝐷1 𝐷2 𝑄1+ 𝑄2+
00 00 00 10 10 0
01 00 00 11 11 0
10 01 01 10 10 0
11 01 01 10 10 1
4. Encoding table:

Next
Present 𝑧
𝑤=0 𝑤=1
00 00 10 0
01 00 11 0
10 01 10 0
11 01 10 1
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5. Encoding states in binary:
𝐴 00
𝐵 01
𝐶 10
𝐷 11
6. States table:
Next
Present 𝑧
𝑤=0 𝑤=1
𝐴 𝐴 𝐶 0
𝐵 𝐴 𝐷 0
𝐶 𝐵 𝐶 0
𝐷 𝐵 𝐶 1
7. Minimizing the amount of states:

− 𝑃1 = (𝐴𝐵𝐶𝐷)

−𝑃2 = (𝐴𝐵𝐶)(𝐷)
0−successor
→ (𝐴𝐴𝐵)
(𝐴𝐵𝐶) 1−successor → (AC)(B)
→ (𝐶𝐷𝐶)

−𝑃3 = (𝐴𝐶)(𝐵)(𝐷)
0−successor
→ (𝐴𝐵)
(𝐴𝐶) 1−successor → (A)(C)
→ (𝐶𝐶)

−𝑃4 = (𝐴)(𝐵)(𝐶)(𝐷)

→ After partition minimization, the states remain unchanged as before.

8. Finite State Machine:

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9. Discuss the differences:
- After reanalyzing the circuit designed above, the two FSMs have different structures but identical
functionality.
- First FSM has 8 states, while the second one has only 4 states. This happens because during
partition minimizing process, we detect that some states produce the same outputs and transition
to equivalent states for all inputs
- However, despite the fact that in the second FSM, the order of the state getting organized is
change, the function of the states is still the same and we still get 𝑧 = 1 at the particular state (here
is 𝐷)

D. Practical circuit:
1. Component preparation
- According to the calculated states, which is 4, we need 2 Flip-flops, and in fact, 1 IC 74HC174 is just
enough to satisfy the requirement
- Cost of logic gates: 𝐶𝑂𝑆𝑇 = 2(𝑁𝑂𝑇) + 4(𝐴𝑁𝐷) + 1(𝑂𝑅) = 7
- Component selection:
No Name Description

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1 74HC04 (NOT gates)

2 74HC08 (AND gates)

3 74HC32(OR gates)

NE555(Pulse
4
generator)

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 5 74HC174(D Flip-flop)

6 Arduino R3

2. Real Circuit:
- To make comparison between non-minimizing partition circuit and minimizing partition circuit,we
construct 2 practical circuits.
- First one is the non-minimizing partition circuit with 3 D Flip-Flops

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- Second one is the minimizing partition circuit with 2 D Flip-Flops

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Conclusion
In this final term project, our group successfully designed and implemented a digital circuit based
on moderately advanced concepts in Digital Electronics, specifically focusing on sequential circuits.

The process began with the creation of a state transition diagram, followed by state optimization
using partition minimization techniques and effective state encoding. The circuit underwent
extensive simulation to verify its functionality prior to practical assembly. Adjustments were made
along the way to enhance efficiency, reducing resource utilization while maintaining overall
reliability.

A reanalysis of the designed circuit confirmed that the results aligned with the initial requirements
and expectations.

This project offered valuable insights and practical experience, significantly strengthening our grasp
of digital circuit design principles. We look forward to receiving feedback from our instructor to
further refine our work and advance our skills for future endeavors.

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