LF to 2.

5 GHz
TruPwr™ Detector
AD8361
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Calibrated rms response
VPOS
Excellent temperature stability i INTERNAL FILTER
RFIN χ2 FLTR
Up to 30 dB input range at 2.5 GHz
TRANS- AD8361
700 mV rms, 10 dBm, re 50 Ω maximum input CONDUCTANCE
CELLS ERROR
±0.25 dB linear response up to 2.5 GHz i
χ2 AMP × 7.5
VRMS
Single-supply operation: 2.7 V to 5.5 V BUFFER

Low power: 3.3 mW at 3 V supply ADD

BAND-GAP OFFSET
Rapid power-down to less than 1 µA PWDN REFERENCE
SREF

APPLICATIONS

01088-C-002
COMM

Measurement of CDMA, W-CDMA, QAM, other complex IREF

modulation waveforms
RF transmitter or receiver power measurement Figure 2. 8-Lead MSOP

GENERAL DESCRIPTION VPOS

i INTERNAL FILTER
RFIN χ2 FLTR
The AD8361 is a mean-responding power detector for use in
TRANS- AD8361
high frequency receiver and transmitter signal chains, up to CONDUCTANCE
CELLS ERROR
2.5 GHz. It is very easy to apply. It requires a single supply only i
χ2 AMP × 7.5
between 2.7 V and 5.5 V, a power supply decoupling capacitor, BUFFER VRMS

and an input coupling capacitor in most applications. The

output is a linear-responding dc voltage with a conversion gain PWDN
BAND-GAP
REFERENCE
of 7.5 V/V rms. An external filter capacitor can be added to

01088-C-003
COMM
increase the averaging time constant.
IREF
3.0
2.8
SUPPLY Figure 3. 6-Lead SOT-23
2.6 REFERENCE MODE
2.4 The AD8361 is intended for true power measurement of simple
2.2
2.0
INTERNAL and complex waveforms. The device is particularly useful for
REFERENCE MODE
measuring high crest-factor (high peak-to-rms ratio) signals,
V rms (Volts)

1.8
1.6 such as CDMA and W-CDMA.
1.4
GROUND
1.2
REFERENCE MODE The AD8361 has three operating modes to accommodate a
1.0
0.8
variety of analog-to-digital converter requirements:
0.6
1. Ground reference mode, in which the origin is zero.
0.4
0.2 2. Internal reference mode, which offsets the output 350 mV
01088-C-001

0.0
0 0.1 0.2 0.3 0.4 0.5 above ground.
RFIN (V rms)
3. Supply reference mode, which offsets the output to VS/7.5.
Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz
(6-Lead SOT-23 Package Ground Reference Mode Only) The AD8361 is specified for operation from −40°C to +85°C
and is available in 8-lead MSOP and 6-lead SOT-23 packages. It
is fabricated on a proprietary high fT silicon bipolar process.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD8361

TABLE OF CONTENTS
Specifications..................................................................................... 3 Applications..................................................................................... 12

Absolute Maximum Ratings............................................................ 4 Output Reference Temperature Drift Compensation ........... 16

ESD Caution.................................................................................. 4 Evaluation Board ............................................................................ 21

Pin Configuration and Function Descriptions............................. 5 Characterization Setups............................................................. 23

Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 24

Circuit Description......................................................................... 11 Ordering Guide .......................................................................... 24

REVISION HISTORY
8/04—Data Sheet Changed from Rev. B to Rev. C.
Changed Trimpots to Trimmable Potentiometers .........Universal
Changes to Specifications ................................................................ 3
Changed Using the AD8361 Section Title to Applications ....... 12
Changes to Figure 43...................................................................... 14
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 24

2/01—Data Sheet Changed from Rev. A to Rev. B.

Rev. C | Page 2 of 24
 AD8361

SPECIFICATIONS
TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted.
Table 1.
Parameter Condition Min Typ Max Unit
SIGNAL INPUT INTERFACE (Input RFIN)
Frequency Range1 2.5 GHz
Linear Response Upper Limit VS = 3 V 390 mV rms
Equivalent dBm, re 50 Ω 4.9 dBm
VS = 5 V 660 mV rms
Equivalent dBm, re 50 Ω 9.4 dBm
Input Impedance2 225||1 Ω||pF
RMS CONVERSION (Input RFIN to Output V rms)
Conversion Gain 7.5 V/V rms
fRF = 100 MHz, VS = 5 V 6.5 8.5 V/V rms
Dynamic Range Error Referred to Best Fit Line3
±0.25 dB Error4 CW Input, −40°C < TA < +85°C 14 dB
±1 dB Error CW Input, −40°C < TA < +85°C 23 dB
±2 dB Error CW Input, −40°C < TA < +85°C 26 dB
CW Input, VS = 5 V, −40°C < TA < +85°C 30 dB
Intercept-Induced Dynamic Internal Reference Mode 1 dB
Range Reduction5, 6 Supply Reference Mode, VS = 3.0 V 1 dB
Supply Reference Mode, VS = 5.0 V 1.5 dB
Deviation from CW Response 5.5 dB Peak-to-Average Ratio (IS95 Reverse Link) 0.2 dB
12 dB Peak-to-Average Ratio (W-CDMA 4 Channels) 1.0 dB
18 dB Peak-to-Average Ratio (W-CDMA 15 Channels) 1.2 dB
OUTPUT INTERCEPT5 Inferred from Best Fit Line3
Ground Reference Mode (GRM) 0 V at SREF, VS at IREF 0 V
fRF = 100 MHz, VS = 5 V −50 +150 mV
Internal Reference Mode (IRM) 0 V at SREF, IREF Open 350 mV
fRF = 100 MHz, VS = 5 V 300 500 mV
Supply Reference Mode (SRM) 3 V at IREF, 3 V at SREF 400 mV
VS at IREF, VS at SREF VS/7.5 V
fRF = 100 MHz, VS = 5 V 590 750 mV
POWER-DOWN INTERFACE
PWDN HI Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C VS − 0.5 V
PWDN LO Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 0.1 V
Power-Up Response Time 2 pF at FLTR Pin, 224 mV rms at RFIN 5 µs
100 nF at FLTR Pin, 224 mV rms at RFIN 320 µs
PWDN Bias Current <1 µA
POWER SUPPLIES
Operating Range −40°C < TA < +85°C 2.7 5.5 V
Quiescent Current 0 mV rms at RFIN, PWDN Input LO7 1.1 mA
Power-Down Current GRM or IRM, 0 mV rms at RFIN, PWDN Input HI <1 µA
SRM, 0 mV rms at RFIN, PWDN Input HI 10 × VS µA

1
Operation at arbitrarily low frequencies is possible; see Applications section.
2
Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively.
3
Calculated using linear regression.
4
Compensated for output reference temperature drift; see Applications section.
5
SOT-23-6L operates in ground reference mode only.
6
The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40.
7
Supply current is input level dependant; see Figure 16.

Rev. C | Page 3 of 24
AD8361

ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter Rating
Supply Voltage VS 5.5 V
SREF, PWDN 0 V, VS
IREF VS − 0.3 V, VS
RFIN 1 V rms
Equivalent Power, re 50 Ω 13 dBm
Internal Power Dissipation1 200 mW
6-Lead SOT-23 170 mW
8-Lead MSOP 200 mW
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range 300°C
(Soldering 60 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1
Specification is for the device in free air.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 4 of 24
 AD8361

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPOS 1 8 SREF VRMS 1 6 VPOS

IREF 2 AD8361 7 VRMS
AD8361

01088-C-004
RFIN 3 TOP VIEW 6 FLTR COMM 2 TOP VIEW 5 RFIN
(Not to Scale) (Not to Scale)

01088-C-005
PWDN 4 5 COMM
FLTR 3 4 PWDN
Figure 4. 8-Lead MSOP
Figure 5. 6-Lead SOT-23

Table 3. Pin Function Descriptions

Pin No. Pin No.
MSOP SOT-23 Mnemonic Description
1 6 VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V.
2 N/A IREF Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this
pin should be tied to VPOS. Do not ground this pin.
3 5 RFIN Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance
is 225 Ω.
4 4 PWDN Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than
100 mV). When a logic high (greater than VS − 0.5 V) is applied, the device is turned off and the supply
current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference
mode VS divided by 100 kΩ).
5 2 COMM Device Ground Pin.
6 3 FLTR By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is
lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals.
7 1 VRMS Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load
>10 kΩ to ground.
8 N/A SREF Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;
otherwise, it should be connected to COMM (ground).

Rev. C | Page 5 of 24
AD8361

TYPICAL PERFORMANCE CHARACTERISTICS

2.8 3.0
2.6 900MHz
2.5
2.4
2.0
2.2 100MHz
1900MHz 1.5
2.0
1.8 1.0
OUTPUT (V)

ERROR (dB)
1.6 0.5
2.5GHz
1.4 0
1.2 –0.5
1.0
–1.0
0.8 MEAN ±3 SIGMA
–1.5
0.6
–2.0
0.4
0.2 –2.5
0.0 01088-C-006 –3.0

01088-C-009
0 0.1 0.2 0.3 0.4 0.5 0.01 0.02 0.1 0.4
INPUT (V rms) (–21dBm) (–7dBm) (+5dBm)
INPUT (V rms)
Figure 6. Output vs. Input Level, Frequencies 100 MHz, 900 MHz,
1900 MHz, and 2500 MHz, Supply 2.7 V, Ground Reference Mode, MSOP Figure 9. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of
Mean, Sine Wave, Supply 3.0 V, Frequency 900 MHz

5.5 3.0
5.5V
5.0 2.5

4.5 2.0
5.0V
4.0 1.5
3.0V 1.0
3.5
OUTPUT (V)

ERROR (dB)

0.5
3.0
0
2.5
–0.5
2.0 2.7V
–1.0
1.5 MEAN ±3 SIGMA
–1.5
1.0 –2.0
0.5 –2.5
01088-C-007

0.0 –3.0

01088-C-010
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.01 0.02 0.1 0.6
INPUT (V rms) (–21dBm) (–7dBm) (+8.6dBm)
INPUT (V rms)

Figure 7. Output vs. Input Level, Figure 10. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side
Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz of Mean, Sine Wave, Supply 5.0 V, Frequency 900 MHz

5.0 3.0
CW
IS95
4.5 REVERSE LINK 2.5
2.0
4.0
1.5
3.5 IS95
1.0 CW REVERSE LINK
ERROR (dB)

3.0
OUTPUT (V)

0.5
2.5 0.0
WCDMA
2.0 4- AND 15-CHANNEL –0.5 4-CHANNEL
–1.0
1.5
–1.5 15-CHANNEL
1.0
–2.0
0.5
–2.5
01088-C-008

01088-C-011

0.0 –3.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.01 0.02 0.1 0.2 0.6 1.0
INPUT (V rms) INPUT (V rms)

Figure 8. Output vs. Input Level with Figure 11. Error from CW Linear Reference vs. Input with Different Waveforms
Different Waveforms Sine Wave (CW), IS95 Reverse Link, Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and
W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 5.0 V W-CDMA 15-Channel, Supply 3.0 V, Frequency 900 MHz

Rev. C | Page 6 of 24
 AD8361
3.0 3.0
2.5 2.5

2.0 2.0

1.5 1.5
+85°C
1.0 1.0

ERROR (dB)
ERROR (dB)

0.5 0.5

0 0

–0.5 –0.5

–1.0 –1.0
MEAN ±3 SIGMA –40°C
–1.5 –1.5

–2.0 –2.0

2.5 –2.5
–3.0 –3.0

01088-C-015
01088-C-012
0.01 0.02 0.1 0.4 0.01 0.02 0.1 0.4
(–21dBm) (–7dBm) (+5dBm) (–21dBm) (–7dBm) (+5dBm)
INPUT (V rms) INPUT (V rms)

Figure 12. Error from CW Linear Reference vs. Input, 3 Sigma to Either Side of Figure 15. Output Delta from +25°C vs. Input Level, 3 Sigma to Either
Mean, IS95 Reverse Link Signal, Supply 3.0 V, Frequency 900 MHz Side of Mean Sine Wave, Supply 3.0 V, Frequency 1900 MHz,
Temperature −40°C to +85°C

3.0 11
2.5 VS = 5V
10
INPUT OUT
2.0 OF RANGE
9
1.5
8

SUPPLY CURRENT (mA)

–40°C +25°C
1.0 VS = 3V
7
ERROR (dB)

0.5 INPUT OUT

6 OF RANGE
0 +85°C
5
–0.5 +25°C
4
–1.0
MEAN ±3 SIGMA +85°C
–1.5 3

–2.0 2

–2.5 1
–40°C

01088-C-016
–3.0 0
01088-C-013

0.01 0.02 0.1 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
(–21dBm) (–7dBm) (+8.6dBm) INPUT (V rms)
INPUT (V rms)

Figure 13. Error from CW Linear Reference vs. Input Level, 3 Sigma to Either Figure 16. Supply Current vs. Input Level, Supplies 3.0 V, and 5.0 V,
Side of Mean, IS95 Reverse Link Signal, Supply 5.0 V, Frequency 900 MHz Temperatures −40°C, +25°C, and +85°C

3.0 250 1.8

+25°C
2.5 +85°C
2.0 1.6
200

SHUNT CAPACITANCE (pF)

1.5
SHUNT RESISTANCE (Ω)

+85°C –40°C 1.4

1.0 +85°C
ERROR (dB)

0.5 150 1.2

0

–0.5 1.0
100
–1.0 +25°C
–40°C 0.8
–1.5 –40°C
50
–2.0 0.6
–2.5
01088-C-017

–3.0 0 0.4
01088-C-014

0.01 0.02 0.1 0.4 0 500 1000 1500 2000 2500

(–21dBm) (–7dBm) (+5dBm) FREQUENCY (MHz)
INPUT (V rms)

Figure 14. Output Delta from +25°C vs. Input Level, 3 Sigma to Figure 17. Input Impedance vs. Frequency, Supply 3 V,
Either Side of Mean Sine Wave, Supply 3.0 V, Temperatures −40°C, +25°C, and +85°C, MSOP
Frequency 900 MHz, Temperature −40°C to +85°C (See Applications for SOT-23 Data)

Rev. C | Page 7 of 24
AD8361
0.03 0.18
0.16
0.02
0.14

0.01 0.12

GAIN CHANGE (V/V rms)

INTERCEPT CHANGE (V)

0.10
0.00 MEAN ±3 SIGMA
0.08

–0.01 0.06
0.04
–0.02
0.02
MEAN ±3 SIGMA
–0.03 0.00

–0.02
–0.04
–0.04

01088-C-021
01088-C-018
–0.05 –0.06
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 18. Output Reference Change vs. Temperature, Figure 21. Conversion Gain Change vs. Temperature, Supply 3 V,
Supply 3 V, Ground Reference Mode Ground Reference Mode, Frequency 900 MHz

0.02 0.18
0.16
0.14
0.01
GAIN CHANGE (V/V rms) 0.12
INTERCEPT CHANGE (V)

0.10
MEAN ±3 SIGMA
0.00 0.08
0.06
0.04
–0.01
MEAN ±3 SIGMA 0.02
0.00
–0.02
–0.02
–0.04

01088-C-022
01088-C-019

–0.03 –0.06
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 19. Output Reference Change vs. Temperature, Supply 3 V, Figure 22. Conversion Gain Change vs. Temperature, Supply 3 V,
Internal Reference Mode (MSOP Only) Internal Reference Mode, Frequency 900 MHz (MSOP Only)

0.03 0.18
0.16
0.02
0.14

0.01 0.12
INTERCEPT CHANGE (V)

GAIN CHANGE (V/V rms)

0.10
0.00 MEAN ±3 SIGMA
0.08

–0.01 0.06
0.04
–0.02
0.02
MEAN ±3 SIGMA
–0.03 0.00

–0.02
–0.04
–0.04
01088-C-023
01088-C-020

–0.05 –0.06
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 20. Output Reference Change vs. Temperature, Supply 3 V, Figure 23. Conversion Gain Change vs. Temperature, Supply 3 V,
Supply Reference Mode (MSOP Only) Supply Reference Mode, Frequency 900 MHz (MSOP Only)

Rev. C | Page 8 of 24
 AD8361

GATE PULSE FOR PWDN INPUT

900MHz RF TONE

370mV 500mV PER 370mV

VERTICAL
DIVISION

270mV 270mV
500mV PER
VERTICAL
DIVISION
RF INPUT RF INPUT

67mV
67mV

25mV

01088-C-027
01088-C-024
25mV

5µs PER HORIZONTAL DIVISION 2µs PER HORIZONTAL DIVISION

Figure 24. Output Response to Modulated Pulse Input for Various RF Input Figure 27. Output Response Using Power-Down Mode for Various RF Input
Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor Levels, Supply 3 V, Frequency 900 MHz, No Filter Capacitor

GATE PULSE FOR

900MHz RF TONE PWDN INPUT

370mV 500mV PER 370mV

VERTICAL
DIVISION

270mV 270mV
500mV PER
VERTICAL
RF INPUT DIVISION RF INPUT

67mV 67mV

01088-C-028
01088-C-025

25mV 25mV

50µs PER HORIZONTAL DIVISION 20µs PER HORIZONTAL DIVISION

Figure 25. Output Response to Modulated Pulse Input for Various RF Input Figure 28. Output Response Using Power-Down Mode for Various RF Input
Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor Levels, Supply 3 V, Frequency 900 MHz, 0.01 µF Filter Capacitor

HPE3631A HPE3631A
POWER SUPPLY TEK TDS784C POWER SUPPLY TEK TDS784C
SCOPE SCOPE

C4 C2 C4 C2
0.01µF 100pF AD8361 100pF AD8361
0.01µF
1 VPOS SREF 8 1 VPOS SREF 8
TEK P6204 TEK P6204
2 IREF VRMS 7 2 IREF VRMS 7
FET PROBE FET PROBE
C1 C3 C1 C3
3 RFIN FLTR 6 C5 3 RFIN FLTR 6 C5
R1 0.1µF 100pF R1 0.1µF 100pF
75Ω 4 PWDN COMM 5 75Ω 4 PWDN COMM 5
01088-C-026

HP8648B HP8648B
01088-C-029
SIGNAL SIGNAL HP8110A
GENERATOR GENERATOR SIGNAL
GENERATOR

Figure 26. Hardware Configuration for Figure 29. Hardware Configuration

Output Response to Modulated Pulse Input for Output Response Using Power-Down Mode

Rev. C | Page 9 of 24
AD8361
7.8 16

7.6
14
7.4 VS = 3V
CONVERSION GAIN (V/V rms)

7.2 12

7.0 10

PERCENT
6.8
8
6.6

6.4 6

6.2 4
6.0
2
5.8

01088-C-033
01088-C-030
5.6 0
100 1000 6.9 7.0 7.2 7.4 7.6 7.8
CARRIER FREQUENCY (MHz) CONVERSION GAIN (V/V rms)

Figure 30. Conversion Gain Change vs. Frequency, Supply 3 V, Ground Figure 33. Conversion Gain Distribution Frequency 100 MHz,
Reference Mode, Frequency 100 MHz to 2500 MHz, Representative Device Supply 5 V, Sample Size 3000

SUPPLY RF
12
INPUT
370mV 500mV PER
VERTICAL 10
DIVISION

270mV 8
PERCENT

67mV 4
01088-C-031

25mV 2
20µs PER HORIZONTAL DIVISION

01088-C-034
0
0.32 0.34 0.36 0.38 0.40 0.42 0.44
Figure 31. Output Response to Gating on Power Supply, for Various RF Input IREF MODE INTERCEPT (V)
Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor
Figure 34. Output Reference, Internal Reference Mode, Supply 5 V,
Sample Size 3000 (MSOP Only)

HP8110A 12
AD811
PULSE
50Ω GENERATOR
10
732Ω TEK TDS784C
SCOPE
8
PERCENT

C4 C2
0.01µF 100pF AD8361
6
1 VPOS SREF 8
TEK P6204
2 IREF VRMS 7
FET PROBE 4
C1 C3
3 RFIN FLTR 6 C5
R1 0.1µF 100pF
75Ω 4 COMM 5 2
PWDN
01088-C-035
01088-C-032

HP8648B 0
SIGNAL 0.64 0.66 0.68 0.70 0.72 0.74 0.76
GENERATOR SREF MODE INTERCEPT (V)

Figure 32. Hardware Configuration for Output Response to Power Supply Figure 35. Output Reference, Supply Reference Mode, Supply 5 V,
Gating Measurements Sample Size 3000 (MSOP Only)

Rev. C | Page 10 of 24
 AD8361

CIRCUIT DESCRIPTION
The AD8361 is an rms-responding (mean power) detector that The squaring cells have very wide bandwidth with an intrinsic
provides an approach to the exact measurement of RF power response from dc to microwave. However, the dynamic range of
that is basically independent of waveform. It achieves this such a system is fairly small, due in part to the much larger
function through the use of a proprietary technique in which dynamic range at the output of the squaring cells. There are
the outputs of two identical squaring cells are balanced by the practical limitations to the accuracy of sensing very small error
action of a high-gain error amplifier. signals at the bottom end of the dynamic range, arising from small
random offsets that limit the attainable accuracy at small inputs.
The signal to be measured is applied to the input of the first
squaring cell, which presents a nominal (LF) resistance of On the other hand, the squaring cells in the AD8361 have a
225 Ω between the RFIN and COMM pins (connected to the Class-AB aspect; the peak input is not limited by their quiescent
ground plane). Because the input pin is at a bias voltage of about bias condition but is determined mainly by the eventual loss of
0.8 V above ground, a coupling capacitor is required. By making square-law conformance. Consequently, the top end of their
this an external component, the measurement range may be response range occurs at a fairly large input level (approximately
extended to arbitrarily low frequencies. 700 mV rms) while preserving a reasonably accurate square-law
response. The maximum usable range is, in practice, limited by
The AD8361 responds to the voltage, VIN, at its input by the output swing. The rail-to-rail output stage can swing from a
squaring this voltage to generate a current proportional to VIN few millivolts above ground to less than 100 mV below the
squared. This is applied to an internal load resistor, across which supply. An example of the output induced limit: given a gain of
a capacitor is connected. These form a low-pass filter, which 7.5 and assuming a maximum output of 2.9 V with a 3 V supply,
extracts the mean of VIN squared. Although essentially voltage- the maximum input is (2.9 V rms)/7.5 or 390 mV rms.
responding, the associated input impedance calibrates this port
in terms of equivalent power. Therefore, 1 mW corresponds to a Filtering
voltage input of 447 mV rms. The Applications section shows An important aspect of rms-dc conversion is the need for
how to match this input to 50 Ω. averaging (the function is root-MEAN-square). For complex RF
waveforms, such as those that occur in CDMA, the filtering
The voltage across the low-pass filter, whose frequency may be provided by the on-chip, low-pass filter, although satisfactory
arbitrarily low, is applied to one input of an error-sensing for CW signals above 100 MHz, is inadequate when the signal
amplifier. A second identical voltage-squaring cell is used to has modulation components that extend down into the
close a negative feedback loop around this error amplifier. This kilohertz region. For this reason, the FLTR pin is provided: a
second cell is driven by a fraction of the quasi-dc output voltage capacitor attached between this pin and VPOS can extend the
of the AD8361. When the voltage at the input of the second averaging time to very low frequencies.
squaring cell is equal to the rms value of VIN, the loop is in a
stable state, and the output then represents the rms value of the Offset
input. The feedback ratio is nominally 0.133, making the rms-dc An offset voltage can be added to the output (when using the
conversion gain ×7.5, that is MSOP version) to allow the use of ADCs whose range does not
extend down to ground. However, accuracy at the low end
VOUT = 7.5 × VIN rms degrades because of the inherent error in this added voltage.
This requires that the IREF (internal reference) pin be tied to
By completing the feedback path through a second squaring VPOS and SREF (supply reference) to ground.
cell, identical to the one receiving the signal to be measured,
several benefits arise. First, scaling effects in these cells cancel; In the IREF mode, the intercept is generated by an internal
thus, the overall calibration may be accurate, even though the reference cell and is a fixed 350 mV, independent of the supply
open-loop response of the squaring cells taken separately need voltage. To enable this intercept, IREF should be open-circuited,
not be. Note that in implementing rms-dc conversion, no and SREF should be grounded.
reference voltage enters into the closed-loop scaling. Second, the
tracking in the responses of the dual cells remains very close In the SREF mode, the voltage is provided by the supply. To
over temperature, leading to excellent stability of calibration. implement this mode, tie IREF to VPOS and SREF to VPOS.
The offset is then proportional to the supply voltage and is
400 mV for a 3 V supply and 667 mV for a 5 V supply.

Rev. C | Page 11 of 24
AD8361

APPLICATIONS
Basic Connections +VS 2.7V – 5.5V

Figure 36 through Figure 38 show the basic connections for the

AD8361’s MSOP version in its three operating modes. In all 100pF

modes, the device is powered by a single supply of between AD8361

0.01µF
2.7 V and 5.5 V. The VPOS pin is decoupled using 100 pF and 1 VPOS SREF 8
0.01 µF capacitors. The quiescent current of 1.1 mA in CC 2 IREF VRMS 7 V rms
operating mode can be reduced to 1 µA by pulling the PWDN 100pF
RFIN 3 RFIN FLTR 6
pin up to VPOS.

01088-C-038
R1 CFLTR
75Ω 4 PWDN COMM 5
A 75 Ω external shunt resistance combines with the ac-coupled
input to give an overall broadband input impedance near 50 Ω. Figure 38. Basic Connections for Supply Referenced Mode
Note that the coupling capacitor must be placed between the
The output voltage is nominally 7.5 times the input rms voltage
input and the shunt impedance. Input impedance and input
(a conversion gain of 7.5 V/V rms). Three modes of operation
coupling are discussed in more detail below.
are set by the SREF and IREF pins. In addition to the ground
The input coupling capacitor combines with the internal input reference mode shown in Figure 36, where the output voltage
resistance (Figure 37) to provide a high-pass corner frequency swings from around near ground to 4.9 V on a 5.0 V supply, two
given by the equation additional modes allow an offset voltage to be added to the
output. In the internal reference mode (Figure 37), the output
1 voltage swing is shifted upward by an internal reference voltage
f 3 dB =
2 π × CC × RIN of 350 mV. In supply referenced mode (Figure 38), an offset
voltage of VS/7.5 is added to the output voltage. Table 4
With the 100 pF capacitor shown in Figure 36 through Figure 38, summarizes the connections, output transfer function, and
the high-pass corner frequency is about 8 MHz. minimum output voltage (i.e., zero signal) for each mode.
+VS 2.7V – 5.5V
Output Swing
Figure 39 shows the output swing of the AD8361 for a 5 V
100pF
supply voltage for each of the three modes. It is clear from
0.01µF AD8361 Figure 39 that operating the device in either internal reference
1 VPOS SREF 8
mode or supply referenced mode reduces the effective dynamic
CC 2 IREF VRMS 7 V rms range as the output headroom decreases. The response for lower
100pF
RFIN 3 RFIN FLTR 6 supply voltages is similar (in the supply referenced mode, the
01088-C-036

R1
75Ω
CFLTR offset is smaller), but the dynamic range reduces further as
4 PWDN COMM 5
headroom decreases. Figure 40 shows the response of the
AD8361 to a CW input for various supply voltages.
Figure 36. Basic Connections for Ground Reference Mode
5.0
SUPPLY REF
+VS 2.7V – 5.5V 4.5

4.0
INTERNAL REF
100pF 3.5
GROUND REF
3.0
OUTPUT (V)

0.01µF AD8361
1 VPOS SREF 8 2.5

CC 2 IREF VRMS 7 V rms 2.0

100pF
RFIN 3 RFIN FLTR 6 1.5
01088-C-037

R1 CFLTR
75Ω 4 PWDN COMM 5 1.0

0.5
Figure 37. Basic Connections for Internal Reference Mode
01088-C-039

0.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
INPUT (V rms)

Figure 39. Output Swing for Ground, Internal, and

Supply Referenced Mode, VPOS = 5 V (MSOP Only)

Rev. C | Page 12 of 24
 AD8361
5.5 should however be noted that offsets at the low end can be
5.5V
5.0 either positive or negative, so this plot could also trend upwards
4.5
5.0V
at the low end. Figure 9, Figure 10, Figure 12, and Figure 13
4.0 show a ±3 sigma distribution of the device error for a large
3.0V
3.5 population of devices.
OUTPUT (V)

3.0 2.0
2.5
1.5
2.0 2.7V
1.5 1.0
2.5GHz
1.0
0.5

ERROR (dB)
0.5 100MHz

01088-C-040
0.0
0.0 1.9GHz
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
INPUT (V rms) –0.5
100MHz
Figure 40. Output Swing for Supply Voltages of –1.0
2.7 V, 3.0 V, 5.0 V and 5.5 V (MSOP Only)
Dynamic Range –1.5
900MHz
Because the AD8361 is a linear-responding device with a –2.0

01088-C-042
0.01 0.02 0.1 0.4 1.0
nominal transfer function of 7.5 V/V rms, the dynamic range in (–21dBm) (–7dBm) (+5dBm)
INPUT (V rms)
dB is not clear from plots such as Figure 39. As the input level is
increased in constant dB steps, the output step size (per dB) also Figure 42. Representative Unit, Error in dB vs. Input Level, VS = 2.7 V
increases. Figure 41 shows the relationship between the output
It is also apparent in Figure 42 that the error plot tends to shift
step size (i.e., mV/dB) and input voltage for a nominal transfer
to the right with increasing frequency. Because the input
function of 7.5 V/V rms.
impedance decreases with frequency, the voltage actually
Table 4. Connections and Nominal Transfer Function for applied to the input also tends to decrease (assuming a constant
Ground, Internal, and Supply Reference Modes source impedance over frequency). The dynamic range is
Output almost constant over frequency, but with a small decrease in
Reference Intercept conversion gain at high frequency.
Mode IREF SREF (No Signal) Output
Ground VPOS COMM Zero 7.5 VIN Input Coupling and Matching
Internal OPEN COMM 0.350 V 7.5 VIN + 0.350 V The input impedance of the AD8361 decreases with increasing
Supply VPOS VPOS VS/7.5 7.5 VIN + VS/7.5 frequency in both its resistive and capacitive components
(Figure 17). The resistive component varies from 225 Ω at
700 100 MHz down to about 95 Ω at 2.5 GHz.

600 A number of options exist for input matching. For operation at

multiple frequencies, a 75 Ω shunt to ground, as shown in
500 Figure 43, provides the best overall match. For use at a single
frequency, a resistive or a reactive match can be used. By
400
mV/dB

plotting the input impedance on a Smith Chart, the best value

300
for a resistive match can be calculated. The VSWR can be held
below 1.5 at frequencies up to 1 GHz, even as the input
200 impedance varies from part to part. (Both input impedance and
input capacitance can vary by up to ±20% around their nominal
100
values.) At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a
shunt resistor is not sufficient to reduce the VSWR below 1.5.
01088-C-041

0
0 100 200 300 400 500 600 700 800 Where VSWR is critical, remove the shunt component and
INPUT (mV)
insert an inductor in series with the coupling capacitor as
Figure 41. Idealized Output Step Size as a Function of Input Voltage shown in Figure 44.
Plots of output voltage versus input voltage result in a straight
Table 5 gives recommended shunt resistor values for various
line. It may sometimes be more useful to plot the error on a
frequencies and series inductor values for high frequencies. The
logarithmic scale, as shown in Figure 42. The deviation of the
coupling capacitor, CC, essentially acts as an ac-short and plays
plot for the ideal straight line characteristic is caused by output
no intentional part in the matching.
clipping at the high end and by signal offsets at the low end. It

Rev. C | Page 13 of 24
AD8361
Table 6. Recommended Values for a Reactive Input
CC
RFIN RFIN
Matching (Figure 45)

01088-C-043
RSH Frequency (MHz) CM (pF) LM (nH)
AD8361 100 16 180
Figure 43. Input Coupling/Matching Options, Broadband Resistor Match 800 2 15
900 2 12
LM CC
1800 1.5 4.7
RFIN RFIN 1900 1.5 4.7

01088-C-044
2500 1.5 3.3
AD8361

Figure 44. Input Coupling/Matching Options, Series Inductor Match

Input Coupling Using a Series Resistor
Figure 46 shows a technique for coupling the input signal into
the AD8361 that may be applicable where the input signal is
CM CC
much larger than the input range of the AD8361. A series
RFIN RFIN resistor combines with the input impedance of the AD8361 to
01088-C-045

LM attenuate the input signal. Because this series resistor forms a

AD8361 divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
Figure 45. Input Coupling/Matching Options, Narrowband Reactive Match method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the transmission line’s impedance, then the VSWR
RSERIES CC of the system is relatively unaffected.
RFIN RFIN
01088-C-046

250 1.7

AD8361
200 1.4
Figure 46. Input Coupling/Matching Options, Attenuating the Input Signal

CAPACITANCE (pF)
RESISTANCE (Ω)

150 1.1
Table 5. Recommended Component Values for Resistive or
Inductive Input Matching (Figure 43 and Figure 44)
Frequency Matching Component 100 0.8

100 MHz 63.4 Ω Shunt

800 MHz 75 Ω Shunt 0.5
50
900 MHz 75 Ω Shunt
1800 MHz 150 Ω Shunt or 4.7 nH Series

01088-C-047
0 0.2
1900 MHz 150 Ω Shunt or 4.7 nH Series 0 500 1000 1500 2000 2500 3000 3500
2500 MHz 150 Ω Shunt or 2.7 nH Series FREQUENCY (MHz)

Alternatively, a reactive match can be implemented using a shunt Figure 47. Input Impedance vs. Frequency, Supply 3 V, SOT-23
inductor to ground and a series capacitor, as shown in Figure 45. A Selecting the Filter Capacitor
method for hand calculating the appropriate matching components The AD8361’s internal 27 pF filter capacitor is connected in
is shown on page 12 of the AD8306 data sheet. parallel with an internal resistance that varies with signal level
from 2 kΩ for small signals to 500 Ω for large signals. The
Matching in this manner results in very small values for CM,
resulting low-pass corner frequency between 3 MHz and
especially at high frequencies. As a result, a stray capacitance as
12 MHz provides adequate filtering for all frequencies above
small as 1 pF can significantly degrade the quality of the match.
240 MHz (i.e., 10 times the frequency at the output of the
The main advantage of a reactive match is the increase in
squarer, which is twice the input frequency). However, signals
sensitivity that results from the input voltage being gained up
with high peak-to-average ratios, such as CDMA or W-CDMA
(by the square root of the impedance ratio) by the matching
signals, and low frequency components require additional
network. Table 6 shows the recommended values for reactive
filtering. TDMA signals, such as GSM, PDC, or PHS, have a
matching.
peak-to average ratio that is close to that of a sinusoid, and the
internal filter is adequate.

Rev. C | Page 14 of 24
 AD8361
The filter capacitance of the AD8361 can be augmented by current consumption, disabling the device reduces the leakage
connecting a capacitor between Pin 6 (FLTR) and VPOS. Table 7 current to less than 1 µA. Figure 27 and Figure 28 show the
shows the effect of several capacitor values for various response of the output of the AD8361 to a pulse on the PWDN
communications standards with high peak-to-average ratios pin, with no capacitance and with a filter capacitance of 0.01 µF,
along with the residual ripple at the output, in peak-to-peak and respectively; the turn-on time is a function of the filter
rms volts. Note that large filter capacitors increase the enable and capacitor. Figure 31 shows a plot of the output response to the
pulse response times, as discussed below. supply being turned on (i.e., PWDN is grounded and VPOS is
Table 7. Effect of Waveform and CFILT on Residual AC pulsed) with a filter capacitor of 0.01 µF. Again, the turn-on
time is strongly influenced by the size of the filter capacitor.
Output Residual AC
Waveform CFILT V dc mV p-p mV rms If the input of the AD8361 is driven while the device is disabled
IS95 Reverse Link Open 0.5 550 100 (PWDN = VPOS), the leakage current of less than 1 µA
1.0 1000 180 increases as a function of input level. When the device is
2.0 2000 360 disabled, the output impedance increases to approximately
0.01 µF 0.5 40 6 16 kΩ.
1.0 160 20
Volts to dBm Conversion
2.0 430 60
0.1 µF 0.5 20 3 In many of the plots, the horizontal axis is scaled in both rms
1.0 40 6 volts and dBm. In all cases, dBm are calculated relative to an
2.0 110 18 impedance of 50 Ω. To convert between dBm and volts in a
IS95 8-Channel 0.01 µF 0.5 290 40 50 Ω system, the following equations can be used. Figure 48
Forward Link 1.0 975 150 shows this conversion in graphical form.

⎡ (V rms )2 ⎤
2.0 2600 430
0.1 µF 0.5 50 7 ⎢ ⎥
1.0 190 30 Power (dBm ) = 10log ⎢
50 Ω ⎥
⎢ 0.001 W ⎥
(
= 10log 20 (V rms )2 )
2.0 670 95
⎢ ⎥
W-CDMA 15 0.01 µF 0.5 225 35 ⎢⎣ ⎥⎦
Channel 1.0 940 135
log −1 (dBm/10 )
2.0 2500 390
⎛ dBm ⎞
0.1 µF 0.5 45 6 V rms = 0.001 W × 50 Ω × log −1 ⎜ ⎟=
1.0 165 25 ⎝ 10 ⎠ 20
2.0 550 80
V rms dBm
+20
Operation at Low Frequencies
1 +10
Although the AD8361 is specified for operation up to 2.5 GHz,
there is no lower limit on the operating frequency. It is only 0
necessary to increase the input coupling capacitor to reduce the 0.1
–10
corner frequency of the input high-pass filter (use an input
resistance of 225 Ω for frequencies below 100 MHz). It is also –20

necessary to increase the filter capacitor so that the signal at the 0.01
–30
output of the squaring circuit is free of ripple. The corner
01088-C-048

–40
frequency is set by the combination of the internal resistance of
0.001
2 kΩ and the external filter capacitance.
Power Consumption, Enable and Power-On Figure 48. Conversion from dBm to rms Volts

The quiescent current consumption of the AD8361 varies with

the size of the input signal from about 1 mA for no signal up to
7 mA at an input level of 0.66 V rms (9.4 dBm, re 50 Ω). If the
input is driven beyond this point, the supply current increases
steeply (see Figure 16). There is little variation in quiescent
current with power supply voltage.

The AD8361 can be disabled either by pulling the PWDN

(Pin 4) to VPOS or by simply turning off the power to the
device. While turning off the device obviously eliminates the

Rev. C | Page 15 of 24
AD8361
Output Drive Capability and Buffering OUTPUT REFERENCE TEMPERATURE DRIFT
The AD8361 is capable of sourcing an output current of COMPENSATION
approximately 3 mA. If additional current is required, a simple The error due to low temperature drift of the AD8361 can be
buffering circuit can be used as shown in Figure 51. Similar reduced if the temperature is known. Many systems incorporate
circuits can be used to increase or decrease the nominal a temperature sensor; the output of the sensor is typically
conversion gain of 7.5 V/V rms (Figure 49 and Figure 50). In digitized, facilitating a software correction. Using this
Figure 50, the AD8031 buffers a resistive divider to give a slope information, only a two-point calibration at ambient is required.
of 3.75 V/V rms. In Figure 49, the op amp’s gain of two increases
the slope to 15 V/V rms. Using other resistor values, the slope The output voltage of the AD8361 at ambient (25°C) can be
can be changed to an arbitrary value. The AD8031 rail-to-rail expressed by the equation
op amp, used in these example, can swing from 50 mV to 4.95 V
on a single 5 V supply and operate at supply voltages down to VOUT = (GAIN × VIN ) + ς ΟΣ
2.7 V. If high output current is required (>10 mA), the AD8051,
where GAIN is the conversion gain in V/V rms and VOS is the
which also has rail-to- rail capability, can be used down to a
extrapolated output voltage for an input level of 0 V. GAIN and
supply voltage of 3 V. It can deliver up to 45 mA of output
VOS (also referred to as intercept and output reference) can be
current.
calculated at ambient using a simple two-point calibration by
5V measuring the output voltages for two specific input levels.
0.01µF 100pF
Calibration at roughly 35 mV rms (−16 dBm) and 250 mV rms
0.01µF (+1 dBm) is recommended for maximum linear dynamic range.
VPOS
VOUT
However, alternative levels and ranges can be chosen to suit the
AD8031 15V/V rms application. GAIN and VOS are then calculated using the
AD8361
equations
COMM PWDN
5kΩ (VOUT2 − VOUT1 )
GAIN =
01088-C-049

5kΩ VIN2 − VIN1

Figure 49. Output Buffering Options, Slope of 15 V/V rms VOS = VOUT1 − (GAIN × VIN1 )

Both GAIN and VOS drift over temperature. However, the drift
100pF
5V of VOS has a bigger influence on the error relative to the output.
0.01µF
This can be seen by inserting data from Figure 18 and Figure 21
10kΩ
(intercept drift and conversion gain) into the equation for VOUT.
VPOS
VOUT
These plots are consistent with Figure 14 and Figure 15, which
0.01µF
5kΩ show that the error due to temperature drift decreases with
AD8361
increasing input level. This results from the offset error having a
5kΩ AD8031 3.75V/V rms
diminishing influence with increasing level on the overall
01088-C-050

COMM PWDN
measurement error.

Figure 50. Output Buffering Options, Slope of 3.75 V/V rms From Figure 18, the average intercept drift is 0.43 mV/°C from
−40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a
5V
less rigorous compensation scheme, the average drift over the
0.01µF 100pF complete temperature range can be calculated as

⎛ 0.010 V − (− 0.028 V ) ⎞
DRIFTVOS (V/°C ) = ⎜⎜
0.01µF
VPOS
⎟⎟ = 0.000304 V/°C
VOUT
⎝ + 85°C − (− 40°C ) ⎠
AD8031 7.5V/V rms
AD8361
With the drift of VOS included, the equation for VOUT becomes
01088-C-051

COMM PWDN
VOUT = (GAIN × VIN) + VOS + DRIFTVOS × (TEMP − 25°C)

Figure 51. Output Buffering Options, Slope of 7.5 V/V rms

Rev. C | Page 16 of 24
 AD8361
The equation can be rewritten to yield a temperature Extended Frequency Characterization
compensated value for VIN: Although the AD8361 was originally intended as a power
measurement and control device for cellular wireless
VIN =
(VOUT − VOS − DRIFTVOS × (TEMP − 25°C )) applications, the AD8361 has useful performance at higher
GAIN frequencies. Typical applications may include MMDS, LMDS,
WLAN, and other noncellular activities.
Figure 52 shows the output voltage and error (in dB) as a
function of input level for a typical device (note that output In order to characterize the AD8361 at frequencies greater than
voltage is plotted on a logarithmic scale). Figure 53 shows the 2.5 GHz, a small collection of devices were tested. Dynamic
error in the calculated input level after the temperature range, conversion gain, and output intercept were measured at
compensation algorithm has been applied. For a supply voltage several frequencies over a temperature range of −30°C to +80°C.
of 5 V, the part exhibits a worst-case linearity error over Both CW and 64 QAM modulated input wave forms were used
temperature of approximately ±0.3 dB over a dynamic range of in the characterization process in order to access varying peak-
35 dB. to-average waveform performance.
2.5 10
The dynamic range of the device is calculated as the input
2.0
power range over which the device remains within a
1.5 permissible error margin to the ideal transfer function. Devices
+85°C
1.0 were tested over frequency and temperature. After identifying
+25°C
an acceptable error margin for a given application, the usable
ERROR (dB)

0.5
VOUT (V)

dynamic measurement range can be identified using the plots in

0 1.0
Figure 54 through Figure 57. For instance, for a 1 dB error
–0.5
margin and a modulated carrier at 3 GHz, the usable dynamic
–40°C
–1.0 range can be found by inspecting the 3 GHz plot of Figure 57.
–1.5 Note that the −30°C curve crosses the −1 dB error limit at
–2.0 −17 dBm. For a 5 V supply, the maximum input power should
not exceed 6 dBm in order to avoid compression. The resultant
01088-C-052

–2.5 0.1
–25 –20 –15 –10 –5 0 5 10 usable dynamic range is therefore
PIN (dBm)

Figure 52. Typical Output Voltage and Error vs. 6 dBm − (−17 dBm)
Input Level, 800 MHz, VPOS = 5 V
or 23 dBm over a temperature range of −30°C to +80°C.
2.0
2.5 10
1.5 2.0
+80°C
1.0 1.5
+25°C +85°C +25°C
0.5 1.0
–30°C
ERROR (dB)

0 0.5
ERROR (dB)

VOUT (V)
–0.5 0
–40°C 1
–1.0
–0.5
–1.5 –1.0

–2.0 –1.5

–2.5 –2.0
01088-C-053

–3.0
01088-0-054

–2.5 0.1
–30 –25 –20 –15 –10 –5 0 5 10
–25 –20 –15 –10 –5 0 5 10
PIN (dBm)
PIN (dBm)
Figure 53. Error after Temperature Compensation of
Figure 54. Transfer Function and Error Plots Measured at
Output Reference,800 MHz, VPOS = 5 V
1.5 GHz for a 64 QAM Modulated Signal

Rev. C | Page 17 of 24
AD8361
2.5 10 2.5 10

2.0 2.0
+80°C
1.5 1.5
+25°C
1.0 1.0
–30°C CW
ERROR (dB)

0.5

ERROR (dB)
0.5

VOUT (V)

VOUT (V)
0 1 0 1

–0.5 –0.5

–1.0 –1.0
64 QAM
–1.5 –1.5

–2.0 –2.0

01088-C-055

01088-C-058
–2.5 0.1 –2.5 0.1
–25 –20 –15 –10 –5 0 5 10 –25 –20 –15 –10 –5 0 5 10
PIN (dBm) PIN (dBm)

Figure 55. Transfer Function and Error Plots Measured at Figure 58. Error from CW Linear Reference vs. Input Drive Level for CW
2.5 GHz for a 64 QAM Modulated Signal and 64 QAM Modulated Signals at 3.0 GHz

2.5 10 8.0

2.0
+80°C
7.5
1.5

CONVERSION GAIN (V/V rms)

+25°C
1.0
–30°C 7.0
ERROR (dB)

0.5
VOUT (V)

0 1 6.5

–0.5
6.0
–1.0

–1.5
5.5
–2.0
01088-C-056

01088-C-059
–2.5 0.1 5.0
–25 –20 –15 –10 –5 0 5 10 100 200 400 800 1200 1600 2200 2500 2700 3000
PIN (dBm) FREQUENCY (MHz)

Figure 56. Transfer Function and Error Plots Measured at Figure 59. Conversion Gain vs. Frequency for a
2.7 GHz for a 64 QAM Modulated Signal Typical Device, Supply 3 V, Ground Reference Mode

2.5 10
The transfer functions and error for a CW input and a 64 QAM
2.0 input waveform is shown in Figure 58. The error curve is
+80°C
1.5 generated from a linear reference based on the CW data. The
+25°C
1.0 increased crest factor of the 64 QAM modulation results in a
–30°C
decrease in output from the AD8361. This decrease in output is
ERROR (dB)

0.5
a result of the limited bandwidth and compression of the
VOUT (V)

0 1
internal gain stages. This inaccuracy should be accounted for in
–0.5 systems where varying crest factor signals need to be measured.
–1.0
The conversion gain is defined as the slope of the output voltage
–1.5
versus the input rms voltage. An ideal best fit curve can be
–2.0
found for the measured transfer function at a given supply
01088-C-057

–2.5
–25 –20 –15 –10 –5 0 5 10
0.1 voltage and temperature. The slope of the ideal curve is
PIN (dBm) identified as the conversion gain for a particular device. The
Figure 57. Transfer Function and Error Plots Measured at
conversion gain relates the measurement sensitivity of the
3.0 GHz for a 64 QAM Modulated Signal AD8361 to the rms input voltage of the RF waveform. The
conversion gain was measured for a number of devices over a
temperature range of −30°C to +80°C. The conversion gain for a
typical device is shown in Figure 59. Although the conversion
gain tends to decrease with increasing frequency, the AD8361
provides measurement capability at frequencies greater than

Rev. C | Page 18 of 24
 AD8361
2.5 GHz. However, it is necessary to calibrate for a given One of the AD8361s (U2) has a net gain of about 14 dB
application to accommodate for the change in conversion gain preceding it and therefore operates most accurately at low input
at higher frequencies. signal levels. This is referred to as the weak signal path. U4, on
Dynamic Range Extension for the AD8361 the other hand, does not have the added gain and provides
accurate response at high levels. The output of U2 is attenuated
The accurate measurement range of the AD8361 is limited by
by R1 in order to cancel the effect of U2’s preceding gain so that
internal dc offsets for small input signals and by square law
the slope of the transfer function (as seen at the slider of R1) is
conformance errors for large signals. The measurement range
the same as that of U4 by itself.
may be extended by using two devices operating at different
signal levels and then choosing only the output of the device The circuit comprising U3, U5, and U6 is a crossfader, in which
that provides accurate results at the prevailing input level. the relative gains of the two inputs are determined by the output
currents of a fuzzy comparator made from Q1 and Q2.
Figure 60 depicts an implementation of this idea. In this circuit,
Assuming that the slider of R2 is at 2.5 V dc, the fuzzy
the selection of the output is made gradually over an input level
comparator commands full weighting of the weak signal path
range of about 3 dB in order to minimize the impact of
when the output of U2 is below about 2.0 V dc, and full
imperfect matching of the transfer functions of the two
weighting of the strong signal path when the output of U3
AD8361s. Such a mismatch typically arises because of the
exceeds about 3.0 V dc. U3 and U5 are OTAs (operational
variation of the gain of the RF preamplifier U1 and both the
transconductance amplifiers).
gain and slope variations of the AD8361s with temperature.

5V

270Ω 0.01µF
12V U2

RFC 1 8 +12V
16kΩ
U1 100pF 2 7
AD8361 2
6dB ERA-3 R1 U3
3 6 5V 5kΩ 6
PAD 20dB
68Ω 0.1µF CA3080
4 5 3 5
8.2nF

12V –5V
5V

20kΩ 100Ω 2 7 U6
5V 1kΩ 1kΩ 6
AD820 VOUT
20kΩ 3
RF 6dB R2 Q2 Q1 4
INPUT SPLITTER 10kΩ 2N3906 2N3906

5V

0.01µF
U4
+12V
1 8
20kΩ 2
100pF 2 7 U5 5
AD8361
3 6 5V CA3080
3 6
68Ω 0.1µF 12kΩ
4 5
1MΩ
–5V
01088-C-060

–5V +5V
R3
10kΩ

Figure 60. Range Extender Application

Rev. C | Page 19 of 24
AD8361
U6 provides feedback to linearize the inherent tanh transfer VOUT
function of the OTAs. When one OTA or the other is fully
MISALIGNMENT INDICATES
selected, the feedback is very effective. The active OTA has zero MALADJUSTMENT OF R3
differential input; the inactive one has a potentially large
differential input, but this does not matter because the inactive
OTA is not contributing to the output. However, when both
TRANSITION
OTAs are active to some extent, and the two signal inputs to the REGION

01088-C-062
crossfader are different, it is impossible to have zero differential
inputs on the OTAs. In this event, the crossfader admittedly RF INPUT LEVEL – V rms

generates distortion because of the nonlinear transfer function

Figure 62. Intercept Adjustment
of the OTAs. Fortunately, in this application, the distortion is
not very objectionable for two reasons: In principle, this method could be extended to three or more
AD8361s in pursuit of even more measurement range. However,
1. The mismatch in input levels to the crossfader is never it is very important to pay close attention to the matter of not
large enough to evoke very much distortion because the excessively overdriving the AD8361s in the weaker signal paths
AD8361s are reasonably well-behaved. under strong signal conditions.
2. The effect of the distortion in this case is merely to distort
the otherwise nearly linear slope of the transition between Figure 63 shows the extended range transfer function at multiple
the crossfader’s two inputs. temperatures. The discontinuity at approximately 0.2 V rms arises
as a result of component temperature dependencies. Figure 64
VOUT shows the error in dB of the range extender circuit at ambient
m1 ≠ m2 temperature. For a 1 dB error margin, the range extender circuit
DIFFERING m2
SLOPES INDICATE offers 38 dB of measurement range.
MALADJUSTMENT
OF R1 3.0
REF LINE

m1 2.5
TRANSITION
REGION +80°C
01088-C-061

2.0
RF INPUT LEVEL – V rms
VOUT (V)

–30°C
1.5
Figure 61. Slope Adjustment
This circuit has three trimmable potentiometers. The suggested 1.0
setup procedure is as follows:
0.5
1. Preset R3 at midrange.

01088-C-063
2. Set R2 so that its slider’s voltage is at the middle of the 0
0 0.2 0.4 0.6 0.8 1.0
desired transition zone (about 2.5 V dc is recommended). DRIVE LEVEL (V rms)

3. Set R1 so that the transfer function’s slopes are equal on Figure 63. Output vs. Drive Level over Temperature for
both sides of the transition zone. This is perhaps best a 1 GHz 64 QAM Modulated Signal
accomplished by making a plot of the overall transfer 5

function (using linear voltage scales for both axes) to assess 4

the match in slope between one side of the transition 3
region and the other (see Figure 61). Note: it may be 2
helpful to adjust R3 to remove any large misalignment in 1
ERROR (dB)

the transfer function in order to correctly perceive slope

0
differences.
–1
4. Finally (re)adjust R3 as required to remove any remaining
–2
misalignment in the transfer function (see Figure 62).
–3

–4
01088-C-064

–5
–32 –27 –22 –17 –12 –7 –2 3 8 13
DRIVE LEVEL (dBm)

Figure 64. Error from Linear Reference at 25°C for a

1 GHz 64 QAM Modulated Signal

Rev. C | Page 20 of 24
 AD8361

EVALUATION BOARD
Figure 65 and Figure 68 show the schematic of the AD8361
evaluation board. Note that uninstalled components are drawn
in as dashed. The layout and silkscreen of the component side
are shown in Figure 66, Figure 67, Figure 69, and Figure 70. The
board is powered by a single supply in the 2.7 V to 5.5 V range.
The power supply is decoupled by 100 pF and 0.01 µF
capacitors. Additional decoupling, in the form of a series
resistor or inductor in R6, can also be added. Table 8 details the
various configuration options of the evaluation board.

Table 8. Evaluation Board Configuration Options

Component Function Default Condition
TP1, TP2 Ground and Supply Vector Pins. Not Applicable
SW1 Device Enable. When in Position A, the PWDN pin is connected to +VS and the AD8361 is in power- SW1 = B
down mode. In Position B, the PWDN pin is grounded, putting the device in operating mode.
SW2/SW3 Operating Mode. Selects either ground reference mode, internal reference mode or supply SW2 = A, SW3 = B
reference mode. See Table 4 for more details. (Ground Reference Mode)
C1, R2 Input Coupling. The 75 Ω resistor in Position R2 combines with the AD8361’s internal input R2 = 75 Ω (Size 0402)
impedance to give a broadband input impedance of around 50 Ω. For more precise matching C1 = 100 pF (Size 0402)
at a particular frequency, R2 can be replaced by a different value (see Input Coupling and
Matching and Figure 43 through Figure 46).
Capacitor C1 ac couples the input signal and creates a high-pass input filter whose corner
frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower
frequencies. If resistive attenuation is desired at the input, series resistor R1, which is
nominally 0 Ω, can be replaced by an appropriate value.
C2, C3, R6 Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and 100 pF. A series C2 = 0.01 µF (Size 0402)
inductor or small resistor can be placed in R6 for additional decoupling. C3 = 100 pF (Size 0402)
R6 = 0 Ω (Size 0402)
C5 Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a C5 = 1 nF (Size 0603)
capacitance in C5.
C4, R5 Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms. C4 = R5 = Open (Size 0603)

Rev. C | Page 21 of 24
AD8361

VPOS C3 C2
100pF 0.01µF
TP2
C2 C3 VS R4 AD8361
R6 J2
0.01µF 100pF 0Ω
0Ω 1 VRMS VPOS 6 TP2 VPOS
VS SW3
A J1
AD8361 C4 R5
SW2 VPOS SREF 8 B (OPEN) (OPEN) 2 COMM RFIN 5
A 1 R4
0Ω C1 R2
B
C1 2 IREF VRMS 7 Vrms 100pF 75Ω
3 FLTR PWDN 4
100pF C5 R5 C4
(OPEN) (OPEN) C5
RFIN 3 RFIN FLTR 6 VPOS 1nF
R2 1 3
1nF TP1
75Ω 4 COMM 5 J3
PWDN 2
SW1

01088-C-068
VPOS TP1 R7
50Ω

01088-C-065
A
B
SW1
Figure 68. Evaluation Board Schematic, SOT-23

Figure 65. Evaluation Board Schematic, MSOP

01088-C-066

01088-C-069
Figure 66. Layout of Component Side, MSOP Figure 69. Layout of the Component Side, SOT-23
01088-C-067

01088-C-070

Figure 67. Silkscreen of Component Side, MSOP Figure 70. Silkscreen of the Component Side, SOT-23

Rev. C | Page 22 of 24
 AD8361
Problems caused by impedance mismatch may arise using the Analysis
evaluation board to examine the AD8361 performance. One The conversion gain and output reference are derived using the
way to reduce these problems is to put a coaxial 3 dB attenuator coefficients of a linear regression performed on data collected
on the RFIN SMA connector. Mismatches at the source, cable, in its central operating range (35 mV rms to 250 mV rms). This
and cable interconnection, as well as those occurring on the range was chosen to avoid areas of operation where offset
evaluation board, can cause these problems. distorts the linear response. Error is stated in two forms error
from linear response to CW waveform and output delta from
A simple (and common) example of such a problem is triple 2°C performance.
travel due to mismatch at both the source and the evaluation
board. Here the signal from the source reaches the evaluation The error from linear response to CW waveform is the
board and mismatch causes a reflection. When that reflection difference in output from the ideal output defined by the
reaches the source mismatch, it causes a new reflection, which conversion gain and output reference. This is a measure of both
travels back to the evaluation board, adding to the original the linearity of the device response to both CW and modulated
signal incident at the board. The resultant voltage varies with waveforms. The error in dB uses the conversion gain multiplied
both cable length and frequency dependence on the relative by the input as its reference. Error from linear response to CW
phase of the initial and reflected signals. Placing the 3 dB pad at waveform is not a measure of absolute accuracy, since it is
the input of the board improves the match at the board and thus calculated using the gain and output reference of each device.
reduces the sensitivity to mismatches at the source. When such However, it does show the linearity and effect of modulation on
precautions are taken, measurements are less sensitive to cable the device response. Error from 25° C performance uses the
length and other fixture issues. In an actual application when performance of a given device and waveform type as the
the distance between AD8361 and source is short and well reference; it is predominantly a measure of output variation
defined, this 3 dB attenuator is not needed. with temperature.
C4 C2
CHARACTERIZATION SETUPS 0.1µF 100pF
Equipment AD8361
The primary characterization setup is shown in Figure 72. The VPOS 1 VPOS SREF 8 SREF

signal source used was a Rohde & Schwarz SMIQ03B, version IREF 2 IREF VRMS 7 VRMS
C3
3.90HX. The modulated waveforms used for IS95 reverse link, RFIN 3 RFIN FLTR 6
IS95 nine active channels forward (forward link 18 setting), R1 C1
75Ω

01088-C-071
0.1µF 4 PWDN COMM 5
and W-CDMA 4-channel and 15-channel were generated using
the default settings coding and filtering. Signal levels were PWDN

calibrated into a 50 Ω impedance.

Figure 71. Characterization Board

AD8361
CHARACTERIZATION
BOARD
SMIQ038B RF SIGNAL DC OUTPUT
RF SOURCE RFIN VRMS
3dB
ATTENUATOR
PRUP +VS SREF IREF

DC SOURCES
IEEE BUS
01088-C-072

PC CONTROLLER DC MATRIX / DC SUPPLIES / DMM

Figure 72. Characterization Setup

Rev. C | Page 23 of 24
AD8361

OUTLINE DIMENSIONS
3.00 2.90 BSC
BSC

8 5 6 5 4
3.00 4.90 2.80 BSC
BSC BSC 1.60 BSC
4 1 2 3

PIN 1
PIN 1 INDICATOR
0.65 BSC 0.95 BSC
1.90
1.30 BSC
0.15 1.10 MAX 1.15
0.00 0.90
0.80
0.38 8° 0.60 1.45 MAX 0.22
0.23
0.22 0° 0.40
0.08 0.08
COPLANARITY SEATING 10° 0.60
0.10 PLANE 0.15 MAX 0.50
SEATING 4° 0.45
0.30
PLANE 0° 0.30
COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 73. 8-Lead Mini Small Outline Package [MSOP] COMPLIANT TO JEDEC STANDARDS MO-178AB
(RM-8)
Dimensions shown in millimeters Figure 74. 6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8361ARM −40°C to +85°C 8-Lead MSOP, Tube RM-8 J3A
AD8361ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 J3A
AD8361ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 J3A
AD8361ARMZ1 −40°C to +85°C 8-Lead MSOP, Tube RM-8 J3A
AD8361ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 J3A
AD8361ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 J3A
AD8361ART-REEL −40°C to +85°C 6-Lead SOT-23, 13" Tape and Reel RT-6 J3A
AD8361ART-REEL7 −40°C to +85°C 6-Lead SOT-23, 7" Tape and Reel RT-6 J3A
AD8361ARTZ-RL71 −40°C to +85°C 6-Lead SOT-23, 7" Tape and Reel RT-6 J3A
AD8361-EVAL Evaluation Board MSOP
AD8361ART-EVAL Evaluation Board SOT-23-6L

1
Z = Pb-free part.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C01088–0–8/04(C)

Rev. C | Page 24 of 24