Lecture 10

Analysis and Design

of
Sequential Logic Circuits
Aaron Tan, NUS 2

6.2 Sequential Circuits: Analysis (1/7)

▪ Given a sequential circuit diagram, we can
analyze its behaviour by deriving its state table
and hence its state diagram.
▪ Requires state equations to be derived for the
flip-flop inputs, as well as output functions for the
circuit outputs other than the flip-flops (if any).
▪ We use A(t) and A(t+1) (or simply A and A+) to
represent the present state and next state,
respectively, of a flip-flop represented by A.
Aaron Tan, NUS 3

6.2 Sequential Circuits: Analysis (2/7)

▪ Example using D flip-flops

x D Q A
State equations:
A+ = A∙x + B∙x Q' A'
B+ = A'∙x
Output function: D Q B
y = (A + B)∙x'
Q' B'
CP

Figure 1
Aaron Tan, NUS 4

6.2 Sequential Circuits: Analysis (3/7)

▪ From the state equations and output function, we
derive the state table, consisting of all possible
binary combinations of present states and inputs.
▪ State table
▪ Similar to truth table.
▪ Inputs and present state on the left side.
▪ Outputs and next state on the right side.
m+n
▪ m flip-flops and n inputs → 2 rows.
Aaron Tan, NUS 5

6.2 Sequential Circuits: Analysis (4/7)

▪ State table for circuit of Figure 1:
State equations: Output function:
A+ = A∙x + B∙x y = (A + B)∙x'
B+ = A'∙x
Present Next
State Input State Output
A B x A+ B+ y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Aaron Tan, NUS 6

6.2 Sequential Circuits: Analysis (5/7)

▪ Alternative form of state table:
Present Next
State Input State Output
+ +
A B x A B y
Full table 0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

Present Next State Output

State x=0 x=1 x=0 x=1
Compact table
AB A B A +B +
+ +
y y
00 00 01 0 0
01 00 11 1 0
10 00 10 1 0
11 00 10 1 0
Aaron Tan, NUS 7

6.2 Sequential Circuits: Analysis (6/7)

▪ From the state table, we can draw the state
diagram.
▪ State diagram
▪ Each state is denoted by a circle.
▪ Each arrow (between two circles) denotes a transition of the
sequential circuit (a row in state table).
▪ A label of the form a/b is attached to each arrow where a (if
there is one) denotes the inputs while b (if there is one)
denotes the outputs of the circuit in that transition.
▪ Each combination of the flip-flop values represents a
state. Hence, m flip-flops → up to 2m states.
Aaron Tan, NUS 8

6.2 Sequential Circuits: Analysis (7/7)

▪ State diagram of the circuit of Figure 1:
Present Next State Output
State x=0 x=1 x=0 x=1
AB + +
A B A +B + y y
00 00 01 0 0
01 00 11 1 0 0/0 1/0
10 00 10 1 0 0/1
11 00 10 1 0 00 10

1/0 0/1 0/1 1/0

DONE! 1/0
01 11
Aaron Tan, NUS 9

6.2 Flip-flop Input Functions (1/3)

▪ The outputs of a sequential circuit are functions of the
present states of the flip-flops and the inputs. These are
described algebraically by the circuit output functions.
▪ In Figure 1: y = (A + B)∙x'

▪ The part of the circuit that generates inputs to the flip-

flops are described algebraically by the flip-flop input
functions (or flip-flop input equations).
▪ The flip-flop input functions determine the next state
generation.
▪ From the flip-flop input functions and the characteristic
tables of the flip-flops, we obtain the next states of the
flip-flops.
Aaron Tan, NUS 10

6.2 Flip-flop Input Functions (2/3)

▪ Example: circuit with a JK flip-flop.
▪ We use 2 letters to denote each flip-flop input: the first
letter denotes the input of the flip-flop (J or K for J-K flip-
flop, S or R for S-R flip-flop, D for D flip-flop, T for T flip-
flop) and the second letter denotes the name of the flip-
flop.
B
C'
JA = B∙C'∙x + B'∙C∙x' x
KA = B + y B' J Q A
C
x'
B K Q'
y
CP
Aaron Tan, NUS 11

6.2 Flip-flop Input Functions (3/3)

▪ In Figure 1, we obtain the following state equations by
observing that Q+ = DQ for a D flip-flop:
A+ = A∙x + B∙x (since DA = A∙x + B∙x)
B+ = A'∙x (since DB = A'∙x)

x D Q A

Q' A'

D Q B

Q' B'
CP

y
Figure 1
Aaron Tan, NUS 12

6.2 Analysis: Example #2 (1/3)

▪ Given Figure 2, a sequential circuit with two J-K flip-flops
A and B, and one input x.
J Q A

x K Q'

J Q B

K Q'
Figure 2
CP

▪ Obtain the flip-flop input functions from the circuit:

JA = B JB = x'
KA = B∙x' KB = A'∙x + A∙x' = A  x
 Aaron Tan, NUS 13

6.2 Analysis: Example #2 (2/3)

JA = B JB = x'
KA = B∙x' KB = A'∙x + A∙x' = A  x
◼ Fill the state table using the above functions, knowing
the characteristics of the flip-flops used.
Present Next
J K Q(t+1) Comments state Input state Flip-flop inputs
0 0 Q(t) No change A B x A+ B + JA KA JB KB
0 1 0 Reset
1 0 1 Set 0 0 0 0 1 0 0 1 0
1 1 Q(t)' Toggle 0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0


 Aaron Tan, NUS 14

6.2 Analysis: Example #2 (3/3)

◼ Draw the state diagram from the state table.
Present Next
state Input state Flip-flop inputs
A B x A+ B+ JA KA JB KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
0 11
00
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
0 0 0

1 10
01
1


Aaron Tan, NUS 15

6.2 Analysis: Example #3 (1/3)

▪ Derive the state table and state diagram of this circuit.

J Q A J Q B

K Q' K Q'

CP
y
x

Figure 3

▪ Flip-flop input functions:

JA = B JB = KB = (A  x)' = A∙x + A'∙x'
KA = B'
 Aaron Tan, NUS 16

6.2 Analysis: Example #3 (2/3)

▪ Flip-flop input functions:
JA = B JB = KB = (A  x)' = A∙x + A'∙x'
KA = B'
▪ State table:
Present Next
state Input state Output Flip-flop inputs
A B x A+ B+ y JA KA JB KB
0 0 0 0 1 0 0 1 1 1
0 0 1 0 0 1 0 1 0 0
0 1 0 1 0 1 1 0 1 1
0 1 1 1 1 0 1 0 0 0
1 0 0 0 0 1 0 1 0 0
1 0 1 0 1 0 0 1 1 1
1 1 0 1 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1 1


 Aaron Tan, NUS 17

6.2 Analysis: Example #3 (3/3)

▪ State diagram:
Present Next
state Input state Output Flip-flop inputs
+ +
A B x A B y JA KA JB KB
0 0 0 0 1 0 0 1 1 1
0 0 1 0 0 1 0 1 0 0
0 1 0 1 0 1 1 0 1 1
0 1 1 1 1 0 1 0 0 0
1/1
1 0 0 0 0 1 0 1 0 0
1 0 1 0 1 0 0 1 1 1
0/1
00 10
1 1 0 1 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1 1
0/0 0/1 1/1
1/0

01 1/0 11

0/0


Aaron Tan, NUS 18

6.3 Flip-flop Excitation Tables (1/2)

▪ Analysis: Starting from a circuit diagram, derive
the state table or state diagram.
▪ Design: Starting from a set of specifications (in
the form of state equations, state table, or state
diagram), derive the logic circuit.
▪ Characteristic tables are used in analysis.
▪ Excitation tables are used in design.
Aaron Tan, NUS 19

6.3 Flip-flop Excitation Tables (1/2)

▪ Excitation tables: given the required transition from
present state to next state, determine the flip-flop input(s).
Q Q+ J K Q Q+ S R
0 0 0 X 0 0 0 X
0 1 1 X 0 1 1 0
1 0 X 1 1 0 0 1
1 1 X 0 1 1 X 0
JK Flip-flop SR Flip-flop

Q Q+ D Q Q+ T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
D Flip-flop T Flip-flop
Aaron Tan, NUS 20

6.4 Sequential Circuits: Design

▪ Design procedure:
▪ Start with circuit specifications – description of circuit
behaviour, usually a state diagram or state table.
▪ Derive the state table.
▪ Perform state reduction if necessary.
▪ Perform state assignment.
▪ Determine number of flip-flops and label them.
▪ Choose the type of flip-flop to be used.
▪ Derive circuit excitation and output tables from the state
table.
▪ Derive circuit output functions and flip-flop input functions.
▪ Draw the logic diagram.
 Aaron Tan, NUS 21

6.4 Design: Example #1 (1/5)

▪ Given the following state diagram, design the sequential
circuit using JK flip-flops.

0 Questions:
00 How many flip-flops are needed?
1 How many input variable are
1
there?
1
01 11
0 Answers:
0 Two flip-flops.
1
10 Let’s call them A and B.
One input variable.
0
Let’s call it x.


 Aaron Tan, NUS 22

6.4 Design: Example #1 (2/5)

▪ Circuit state/excitation table, using JK flip-flops.
0
Present Next State
00 State x=0 x=1
1 1 AB A+B+ A+B+
1
00 00 01
01 11 01 10 01
0 10 10 11
0 1 11 11 00
10 Present Next
state Input state Flip-flop inputs
0
A B x A+ B+ JA KA JB KB
Q Q+ J K
0 0 0 0 0 0 X 0 X
0 0 0 X 0 0 1 0 1 0 X 1 X
0 1 1 X 0 1 0 1 0 1 X X 1
1 0 X 1 0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 1 X 0 1 0 1 1 1 X 0 1 X
JK Flip-flop’s 1 1 0 1 1 X 0 X 0
excitation table. 1 1 1 0 0 X 1 X 1


Aaron Tan, NUS 23

6.4 Design: Example #1 (3/5)

▪ Block diagram.

A' A B' B
Q' Q Q' Q
K J K J
CP
KA JA KB JB

A' Combinational
A External
B circuit output(s)
B' (none)
x
External
What are to input(s)
go in here?
Aaron Tan, NUS 24

6.4 Design: Example #1 (4/5)

▪ From state table, get flip-flop input functions.
Present Next
Bx B
state Input state Flip-flop inputs A 00 01 11 10
A B x A+ B+ JA KA JB KB 0 0 0 0 1
0 0 0 0 0 0 X 0 X
A 1 X X X X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1 x
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X JA = B∙x'
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0 Bx B
1 1 1 0 0 X 1 X 1 A 00 01 11 10
0 X X X X
Bx B Bx B
A 00 01 11 10 A 00 01 11 10 A 1 0 0 1 0
0 0 1 X X 0 X X 0 1 x
A 1 0 1 X X A 1 X X 1 0 KA = B∙x
x x
JB = x KB = (A  x)'
Aaron Tan, NUS 25

6.4 Design: Example #1 (5/5)

▪ Flip-flop input functions:
JA = B∙x' JB = x
KA = B∙x KB = (A  x)'

▪ Logic diagram:
A
B

Q' Q Q' Q
K J K J
CP

x
Aaron Tan, NUS 26

6.4 Design: Example #2 (1/3)

▪ Using D flip-flops, design the circuit based on the state
table below. (Exercise: Design it using JK flip-flops.)

Present Next
state Input state Output
A B x A+ B+ y
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0
Aaron Tan, NUS 27

6.4 Design: Example #2 (2/3)

▪ Determine expressions for flip-flop inputs and the circuit
output y.
Bx B
Present Next A 00 01 11 10
state Input state Output 0 0 0 0 1
A B x A+ B+ y DA = A∙B' + B∙x'
A 1 1 1 0 1
0 0 0 0 0 0
0 0 1 0 1 1 x
0 1 0 1 0 0 Bx B
0 1 1 0 1 0 A 00 01 11 10
1 0 0 1 0 0 0
1 0 1 1 1 1 0 1 1 0 DB = A'∙x + B'∙x
1 1 0 1 1 0 A 1 0 1 0 1 + A∙B∙x'
1 1 1 0 0 0
x
Bx B
DA(A,B,x) =  m(2,4,5,6) A 00 01 11 10
DB(A,B,x) =  m(1,3,5,6) 0 0 1 0 0
y = B'∙x
y(A,B,x) =  m(1,5) A 1 0 1 0 0

x
Aaron Tan, NUS 28

6.4 Design: Example #2 (3/3)

▪ From derived expressions, draw logic diagram:
DA = A∙B' + B∙x'
DB = A'∙x + B'∙x + A.B∙x'
y = B'∙x

D Q A
x
Q' A'

D Q B

Q' B'
CP

y
Aaron Tan, NUS 29

6.4 Design: Example #3 (1/4)

▪ Design involving unused states.

Are there other

Given these Derive these
unused states?
Unused state 000:
0 0 0 0 X X X X X X X X X X
0 0 0 1 X X X X X X X X X X
 Aaron Tan, NUS 30

6.4 Design: Example #3 (2/4)

▪ From state table, obtain expressions for flip-flop inputs.

Cx C Cx C
AB 00 01 11 10 AB 00 01 11 10
00 X X 0 0 00 X X X X
01 0 1 1 0 01 X 0 0 X
B B
11 X X X X 11 X X X X
A A
10 X X X 0 10 0 0 0 1
SA = B∙x RA = C∙x'
x x

Cx C Cx C
AB 00 01 11 10 AB 00 01 11 10
00 X X 1 0 00 X X 0 X
01 X 0 0 0 01 0 1 1 1
B B
11 X X X X 11 X X X X
A A
10 0 0 0 0 10 X X X X
SB = A'∙B'∙x x x RB = B∙C + B∙x


 Aaron Tan, NUS 31

6.4 Design: Example #3 (3/4)

▪ From state table, obtain expressions for flip-flop inputs
(cont’d).
Cx C Cx C
AB 00 01 11 10 AB 00 01 11 10
00 X X 0 X 00 X X 1 0
01 1 0 0 X 01 0 X 1 0
B B
11 X X X X 11 X X X X
A A
SC = x' 10 1 0 0 X 10 0 X 1 0 RC = x
x x

Cx C
AB 00 01 11 10
00 X X 0 0
01 0 0 0 0
B
11 X X X X
A
10 0 1 1 0
y = A∙x
x

Aaron Tan, NUS 32

6.4 Design: Example #3 (4/4)

▪ From derived expressions, draw the logic diagram:
SA = B∙x SB = A'∙B'∙x SC = x' y = A∙x
RA = C∙x' RB = B∙C + B∙x RC = x
y
x S Q A

R Q' A'

S Q B

R Q' B'

S Q C

R Q'
CP
Aaron Tan, NUS 33

7. Memory (1/4)
▪ Memory stores programs and data.
▪ Definitions:
▪ 1 byte = 8 bits
▪ 1 word: in multiple of bytes, a unit of transfer between main
memory and registers, usually size of register.
▪ 1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes;
1 GB (giga-bytes) = 230 bytes; 1 TB (tera-bytes) = 240 bytes.
▪ Desirable properties: fast access, large capacity,
economical cost, non-volatile.
▪ However, most memory devices do not possess all these
properties.
Aaron Tan, NUS 34

7. Memory (2/4)
Memory hierarchy
Fast, expensive
(small numbers),
volatile
registers

main memory

disk storage
Slow, cheap
magnetic tapes (large numbers),
non-volatile
Aaron Tan, NUS 35

7. Memory (3/4)
Data transfer
Address Memory
Up to 2k
0
addressable
Processor 1
locations. 2
k-bit address bus 3
MAR 4
5
n-bit data bus
MDR
:

Control lines
(R/W, etc.)
Aaron Tan, NUS 36

7. Memory (4/4)
▪ A memory unit stores binary information in groups of bits
called words.
▪ The data consists of n lines (for n-bit words). Data input
lines provide the information to be stored (written) into
the memory, while data output lines carry the information
out (read) from the memory.
▪ The address consists of k lines which specify which word
(among the 2k words available) to be selected for reading
or writing.
▪ The control lines Read and Write (usually combined into
a single control line Read/Write) specifies the direction of
transfer of the data.
Aaron Tan, NUS 37

7.1 Memory Unit

▪ Block diagram of a memory unit:
n data
input lines
n

k Memory unit
k address lines
2k words
n bits per word
Read/Write

n data
output lines
Aaron Tan, NUS 38

7.2 Read/Write Operations

▪ Write operation:
▪ Transfers the address of the desired word to the address lines.
▪ Transfers the data bits (the word) to be stored in memory to the
data input lines.
▪ Activates the Write control line (set Read/Write to 0).

▪ Read operation:
▪ Transfers the address of the desired word to the address lines.
▪ Activates the Read control line (set Read/Write to 1).

Memory Enable Read/Write Memory Operation

0 X None
1 0 Write to selected word
1 1 Read from selected word
Aaron Tan, NUS 39

7.3 Memory Cell

▪ Two types of RAM
▪ Static RAMs use flip-flops as the memory cells.
▪ Dynamic RAMs use capacitor charges to represent data. Though
simpler in circuitry, they have to be constantly refreshed.
▪ A single memory cell of the static RAM has the following
logic and block diagrams:
Select

Select
R

Input S Q Output Input BC Output

Read/Write
Read/Write
Logic diagram Block diagram
Aaron Tan, NUS 40

7.4 Memory Arrays (1/4)

▪ Logic construction
of a 43 RAM (with
decoder and OR
gates):
Aaron Tan, NUS 41

7.4 Memory Arrays (2/4)

▪ An array of RAM chips: memory chips are
combined to form larger memory.
▪ A 1K  8-bit RAM chip:

RAM 1K x 8

Input data 8 DATA (8) (8)

8
Output data
Address 10 ADRS (10)
Chip select CS
Read/write RW

Block diagram of a 1K x 8 RAM chip

Aaron Tan, NUS 42

7.4 Memory Arrays (3/4)

Address
Input data
Lines Lines 8 lines
11 10 0–9 0–1023
DATA (8) (8)
ADRS (10)
2x4
CS
decoder 1K x 8
RW

S0 0 1024 – 2047
1 DATA (8) (8)
S1 2 ADRS (10)
3 CS
1K x 8
RW

2048 – 3071
Read/write DATA (8) (8)
ADRS (10)
CS
1K x 8
RW

▪ 4K  8 RAM. 3072 – 4095

DATA (8) (8)
ADRS (10)
CS
1K x 8 Output
RW
data
Aaron Tan, NUS 43

7.4 Memory Arrays (4/4) Read/write control line not

included in this diagram.
21-bit
addresses 19-bit internal chip address
A0
A1

A 19
A 20

2-bit
decoder

512K x 8
memory chip 512k X 8
memory chip D 31-24 D 23-16 D 15-8 D 7-0

▪ 2M  32 memory module
19-bit 8-bit data
address input/output

▪ Using 512K  8 memory chips.

Chip select
Aaron Tan, NUS 44

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