COMPUTER ORGANIZATION AND ARCHITECTURE

Mizan-Tepi university
SCHOOL OF COMPUTING AND INFORMATICS
DEPARTMENT OF SOFTWARE ENGINEERING
ASSIGNMENT OF COMPUTER ORGANIZATION AND ARCHITECTECTURE

Group One
R.no Name ID
1. YESHWOND LISANWORK ……………………………..4719/16
2. MELKAMU BELAYNEH………………………………..4445/16
3. HUSINIYA MOHAMED………………………………...4343/16
4. CHOT TUT……………….…………………………4163/16
5. GATTUOCH KUN…….…………………………...………4282/16
6. NESIREDI JEMAL…………………….………….……..4503/16
7. OLIRA KETAMA…………….………………..…….2586/14
8. LELISE HAYILU………………………………..……4391/16
9. HIWOT LEMA…………………..………………..…..4339/16
10. PATHEL TIAY………………………………….………4524/16
11. SEID YIMAM……………………………………….4579/16
12. ASER MULATU…………………………………….4079/16

Submit to : Mr.Gizachew
Submition date :15/05/2017 E.C
COMPUTER ORGANIZATION AND ARCHITECTURE

Table of contents
CHAPTER 8 ---------------------------------------------------------------------------------------1
INPUT-OUTPUT ORGANIZATION --------------------------------------------------------- 1
Introduction ----------------------------------------------------------------------------------1
8.1.Peripheral Devices: -------------------------------------------------------------------- 1
8.2.Input - Output Interface --------------------------------------------------------------- 2
8.3.Asynchronous Data Transfer --------------------------------------------------------- 4
8.4.Modes of Data Transfer : ------------------------------------------------------------- 8
8.5.Priority Interrupt ----------------------------------------------------------------------11
8.6.Direct Memory Access (DMA): ----------------------------------------------------13
8.7. I/O Controllers ----------------------------------------------------------------------- 16
8.8.Serial Communication --------------------------------------------------------------- 18
Conclusion --------------------------------------------------------------------------------- 21
Reference -----------------------------------------------------------------------------------22

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COMPUTER ORGANIZATION AND ARCHITECTURE

CHAPTER 8

INPUT-OUTPUT ORGANIZATION

Introduction
Input-Output (I/O) organization within a computer system defines the mechanisms for
communication between the CPU and external devices. This crucial subsystem
encompasses a wide range of components, including peripheral devices (e.g.,
keyboards, monitors), input-output interfaces, and various data transfer modes such as
programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA).
Asynchronous data transfer allows for flexible data rates, while priority interrupts
ensure timely attention to critical devices. Input-Output Controllers (IOCs) manage
the operation of specific peripherals, and serial communication facilitates data
transmission over a single channel, often used for long-distance connections.

8.1.Peripheral Devices:
The Input / output organization of computer depends upon the size of computer and
the peripherals connected to it. The I/O Subsystem of the computer, provides an
efficient mode of communication between the central system and the outside
environment. The most common input output devices are:
 Monitor
 Keyboard
 Mouse
 Printer
 Magnetic tapes
The devices that are under the direct control of the computer are said to be connected
online.

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8.2.Input - Output Interface

Input Output Interface provides a method for transferring information between
internal storage and external I/O devices. Peripherals connected to a computer need
special communication links for interfacing them with the central processing unit.The
purpose of communication link is to resolve the differences that exist between the
central computer and each peripheral. The Major Differences are:-
 Peripherals are electromechnical and electromagnetic devices and CPU and
memory are electronic devices. Therefore, a conversion of signal values may be
needed.
 The data transfer rate of peripherals is usually slower than the transfer rate of
CPU and consequently, a synchronization mechanism may be needed.
 Data codes and formats in the peripherals differ from the word format in the
CPU and memory
 The operating modes of peripherals are different from each other and must be
controlled so as not to disturb the operation of other peripherals connected to
the CPU.
 To Resolve these differences, computer systems include special hardware
components between the CPU and Peripherals to supervises and synchronizes all
input and out transfers
 These components are called Interface Units because they interface
between the processor bus and the peripheral devices.
I/O BUS and Interface Module
It defines the typical link between the processor and several peripherals. The I/O Bus
consists of data lines, address lines and control lines. The I/O bus from the processor
is attached to all peripherals interface. To communicate with a particular device, the
processor places a device address on address lines. Each Interface decodes the address
and control received from the I/O bus, interprets them for peripherals and provides
signals for the peripheral controller. It is also synchronizes the data flow and
supervises the transfer between peripheral and processor. Each peripheral has its own
controller. For example, the printer controller controls the paper motion, the print
timing.The control lines are referred as I/O command. The commands are as
following:

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 Control command- A control command is issued to activate the peripheral

and to inform it what to do.
 Status command- A status command is used to test various status conditions
in the interface and the peripheral.
 Data Output command- A data output command causes the interface to
respond by transferring data from the bus into one of its registers.
 Data Input command- The data input command is the opposite of the data
output. In this case the interface receives on item of data from the peripheral
and places it in its buffer register. I/O Versus Memory Bus

To communicate with I/O, the processor must communicate with the memory unit.
Like the I/O bus, the memory bus contains data, address and read/write control lines.
There are 3 ways that computer buses can be used to communicate with memory and
I/O:
 Use two Separate buses , one for memory and other for I/O.
 Use one common bus for both memory and I/O but separate control lines for
each.
 Use one common bus for memory and I/O with common control lines.
I/O Processor
In the first method, the computer has independent sets of data, address and control
buses one for accessing memory and other for I/O. This is done in computers that
provides a separate I/O processor (IOP). The purpose of IOP is to provide an
independent pathway for the transfer of information between external device and
internal memory.

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8.3.Asynchronous Data Transfer

This Scheme is used when speed of I/O devices do not match with microprocessor,
and timing characteristics of I/O devices is not predictable. In this method, process
initiates the device and check its status. As a result, CPU has to wait till I/O device is
ready to transfer data. When device is ready CPU issues instruction for I/O transfer. In
this method two types of techniques are used based on signals before data transfer.
i. Strobe Control
ii. Handshaking

Strobe Signal :

The strobe control method of Asynchronous data transfer employs a single control
line to time each transfer. The strobe may be activated by either the source or the
destination unit.
Data Transfer Initiated by Source Unit:

In the block diagram fig. (a), the data bus carries the binary information from source
to destination unit. Typically, the bus has multiple lines to transfer an entire byte or
word. The strobe is a single line that informs the destination unit when a valid data
word is available. The timing diagram fig. (b) the source unit first places the data on
the data bus. The information on the data bus and strobe signal remain in the active
state to allow the destination unit to receive the data.

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Data Transfer Initiated by Destination Unit:

In this method, the destination unit activates the strobe pulse, to informing the source
to provide the data. The source will respond by placing the requested binary
information on the data bus. The data must be valid and remain in the bus long
enough for the destination unit to accept it. When accepted the destination unit then
disables the strobe and the source unit removes the data from the bus.

Disadvantage of Strobe Signal :

The disadvantage of the strobe method is that, the source unit initiates the transfer has
no way of knowing whether the destination unit has actually received the data item
that was places in the bus. Similarly, a destination unit that initiates the transfer has no
way of knowing whether the source unit has actually placed the data on bus. The
Handshaking method solves this problem.
Handshaking:
The handshaking method solves the problem of strobe method by introducing a
second control signal that provides a reply to the unit that initiates the transfer.
Principle of Handshaking:
The basic principle of the two-wire handshaking method of data transfer is as follow:
One control line is in the same direction as the data flows in the bus from the source
to destination. It is used by source unit to inform the destination unit whether there a
valid data in the bus. The other control line is in the other direction from the
destination to the source. It is used by the destination unit to inform the source
whether it can accept the data. The sequence of control during the transfer depends on
the unit that initiates the transfer.
Source Initiated Transfer using Handshaking:
The sequence of events shows four possible states that the system can be at any given
time. The source unit initiates the transfer by placing the data on the bus and enabling

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its data valid signal. The data accepted signal is activated by the destination unit after
it accepts the data from the bus. The source unit then disables its data accepted signal
and the system goes into its initial state.

Destination Initiated Transfer Using Handshaking:

The name of the signal generated by the destination unit has been changed to ready
for data to reflects its new meaning. The source unit in this case does not place data
on the bus until after it receives the ready for data signal from the destination unit.
From there on, the handshaking procedure follows the same pattern as in the source
initiated case. The only difference between the Source Initiated and the Destination
Initiated transfer is in their choice of Initial sate.

Advantage of the Handshaking method:

The Handshaking scheme provides degree of flexibility and reliability because the
successful completion of data transfer relies on active participation by both units. If
any of one unit is faulty, the data transfer will not be completed. Such an error can be

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detected by means of a Timeout mechanism which provides an alarm if the data is not
completed within time.
Asynchronous Serial Transmission:
The transfer of data between two units is serial or parallel. In parallel data
transmission, n bit in the message must be transmitted through n separate conductor
path. In serial transmission, each bit in the message is sent in sequence one at a time.
Parallel transmission is faster but it requires many wires. It is used for short distances
and where speed is important. Serial transmission is slower but is less expensive. In
Asynchronous serial transfer, each bit of message is sent a sequence at a time, and
binary information is transferred only when it is available. When there is no
information to be transferred, line remains idle. In this technique each character
consists of three points :
i. Start Bit- First bit, called start bit is always zero and used to indicate the beginning
character.
ii. Stop Bit- Last bit, called stop bit is always one and used to indicate end of
characters. Stop bit is always in the 1- state and frame the end of the characters to
signify the idle or wait state.
iii. Character Bit- Bits in between the start bit and the stop bit are known as
character bits. The character bits always follow the start bit.

Serial Transmission of Asynchronous is done by two ways:

a) Asynchronous Communication Interface
b) First In First out Buffer
Asynchronous Communication Interface:
It works as both a receiver and a transmitter. Its operation is initialized by CPU by
sending a byte to the control register. The transmitter register accepts a data byte from
CPU through the data bus and transferred to a shift register for serial transmission.
The receive portion receives information into another shift register, and when a

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complete data byte is received it is transferred to receiver register. CPU can select the
receiver register to read the byte through the data bus. Data in the status register is
used for input and output flags.
First In First Out Buffer (FIFO):
A First In First Out (FIFO) Buffer is a memory unit that stores information in such a
manner that the first item is in the item first out. A FIFO buffer comes with separate
input and output terminals. The important feature of this buffer is that it can input data
and output data at two different rates.
When placed between two units, the FIFO can accept data from the source unit at one
rate, rate of transfer and deliver the data to the destination unit at another rate. If the
source is faster than the destination, the FIFO is useful for source data arrive in bursts
that fills out the buffer. FIFO is useful in some applications when data are transferred
asynchronously.

8.4.Modes of Data Transfer :

Transfer of data is required between CPU and peripherals or memory or sometimes
between
any two devices or units of your computer system. To transfer a data from one unit to
another one should be sure that both units have proper connection and at the time of
data transfer the receiving unit is not busy. This data transfer with the computer is
Internal Operation. All the internal operations in a digital system are synchronized by
means of clock pulses supplied by a common clock pulse Generator. The data transfer
can be
i. Synchronous or
ii. Asynchronous
When both the transmitting and receiving units use same clock pulse then such a data
transfer is called Synchronous process. On the other hand, if the there is not concept
of clock pulses and the sender operates at different moment than the receiver then
such a data transfer is called Asynchronous data transfer. The data transfer can be
handled by various modes. some of the modes use CPU as an intermediate path,
others transfer the data directly to and from the memory unit and this can be handled
by 3 following ways:

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i. Programmed I/O
ii. Interrupt-Initiated I/O
iii. Direct Memory Access (DMA)

Programmed I/O Mode:

In this mode of data transfer the operations are the results in I/O instructions which is
a part of computer program. Each data transfer is initiated by a instruction in the
program. Normally the transfer is from a CPU register to peripheral device or vice-
versa. Once the data is initiated the CPU starts monitoring the interface to see when
next transfer can made. The instructions of the program keep close tabs on everything
that takes place in the interface unit and the I/O devices.

The transfer of data requires three instructions:

1. Read the status register
2. Check the status of the flag bit and branch to step one if not set or to step three if
set.
3. Read the data register .
In this technique CPU is responsible for executing data from the memory for output
and storing data in memory for executing of Programmed I/O as shown in Flowchart-:

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Drawback of the Programmed I/O :

The main drawback of the Program Initiated I/O was that the CPU has to monitor the
units all the times when the program is executing. Thus the CPU stays in a program
loop until the I/O unit indicates that it is ready for data transfer. This is a time
consuming process and the CPU time is wasted a lot in keeping an eye to the
executing of program.
To remove this problem an Interrupt facility and special commands are used.
Interrupt-Initiated I/O :
In this method an interrupt facility an interrupt command is used to inform the device
about the start and end of transfer. In the meantime the CPU executes other program.
When the interface determines that the device is ready for data transfer it generates an
Interrupt Request and sends it to the computer.
 When the CPU receives such an signal, it temporarily stops the execution of the
program and branches to a service program to process the I/O transfer and after
completing it returns back to task, what it was originally performing.In this type
of IO, computer does not check the flag. It continue to perform its task
 Whenever any device wants the attention, it sends the interrupt signal to the CPU.
 CPU then deviates from what it was doing, store the return address from PC and
branch to the address of the subroutine.

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There are two ways of choosing the branch address:

 Vectored Interrupt
 Non-vectored Interrupt
 In vectored interrupt :-the source that interrupt the CPU provides the branch
information. This information is called interrupt vectored.
 In non-vectored interrupt:- the branch address is assigned to the fixed address
in the memory.

8.5.Priority Interrupt
There are number of IO devices attached to the computer. They are all capable of
generating the interrupt. When the interrupt is generated from more than one device,
priority interrupt system is used to determine which device is to be serviced first.
Devices with high speed transfer are given higher priority and slow devices are given
lower priority. Establishing the priority can be done in two ways:
 Using Software :A pooling procedure is used to identify highest priority in
software means.
 Using Hardware

Polling Procedure :

There is one common branch address for all interrupts. Branch address contain the
code that polls the interrupt sources in sequence. The highest priority is tested
first.The particular service routine of the highest priority device is served. The
disadvantage is that time required to poll them can exceed the time to serve them in
large number of IO devices.

Using Hardware:

Hardware priority system function as an overall manager.It accepts interrupt request

and determine the priorities. To speed up the operation each interrupting devices has
its own interrupt vector. No polling is required, all decision are established by
hardware priority interrupt unit. It can be established by serial or parallel connection
of interrupt lines.

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Serial or Daisy Chaining Priority:

Device with highest priority is placed first. Device that wants the attention send the
interrupt request to the CPU. CPU then sends the INTACK signal which is applied to
PI(priority in) of the first device. If it had requested the attention, it place its
VAD(vector address) on the bus. And it block the signal by placing 0 in PO(priority
out) If not it pass the signal to next device through PO(priority out) by placing 1. This
process is continued until appropriate device is found. The device whose PI is 1 and
PO is 0 is the device that send the interrupt request.

Parallel Priority Interrupt :

It consist of interrupt register whose bits are set separately by the interrupting devices.
Priority is established according to the position of the bits in the register. Mask
register is used to provide facility for the higher priority devices to interrupt when
lower priority device is being serviced or disable all lower priority devices when
higher is being serviced. Corresponding interrupt bit and mask bit are AND and
applied to priority encoder. Priority encoder generates two bits of vector address.
Another output from it sets IST(interrupt status flip flop).

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8.6.Direct Memory Access (DMA):

In the Direct Memory Access (DMA) the interface transfer the data into and out of the
memory unit through the memory bus. The transfer of data between a fast storage
device such as magnetic disk and memory is often limited by the speed of the CPU.
Removing the CPU from the path and letting the peripheral device manage the

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memory buses directly would improve the speed of transfer. This transfer technique is
called Direct Memory Access (DMA). During the DMA transfer, the CPU is idle and
has no control of the memory buses. A DMA Controller takes over the buses to
manage the transfer directly between the I/O device and memory. The CPU may be
placed in an idle state in a variety of ways. One common method extensively used in
microprocessor is to disable the buses through special control signals such as:
 Bus Request (BR)
 Bus Grant (BG)
These two control signals in the CPU that facilitates the DMA transfer. The Bus
Request (BR) input is used by the DMA controller to request the CPU. When this
input is active, the CPU terminates the execution of the current instruction and places
the address bus, data bus and read write lines into a high Impedance state. High
Impedance state means that the output is disconnected.

The CPU activates the Bus Grant (BG) output to inform the external DMA that the
Bus Request (BR) can now take control of the buses to conduct memory transfer
without processor. When the DMA terminates the transfer, it disables the Bus Request
(BR) line. The CPU disables the Bus Grant (BG), takes control of the buses and return
to its normal operation. The transfer can be made in several ways that are:
i) DMA Burst :- In DMA Burst transfer, a block sequence consisting of a number of
Me mory words is transferred in continuous burst while the DMA controller is master
of the memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA controller to transfer one data
word at a time, after which it must returns control of the buses to the CPU.
DMA Controller: The DMA controller needs the usual circuits of an interface to
communicate with the CPU and I/O device. The DMA controller has three registers:
i. Address Register :- Address Register contains an address to specify the desired

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location in memory.
ii. Word Count Register :- WC holds the number of words to be transferred. The
register is incre/decre by one after each word transfer and internally tested for zero.
iii. Control Register :- Control Register specifies the mode of transfer.The unit
communicates with the CPU via the data bus and control lines. The registers in the
DMA are selected by the CPU through the address bus by enabling the DS (DMA
select) and RS (Register select) inputs. The RD (read) and WR (write) inputs are
bidirectional. When the BG (Bus Grant) input is 0, the CPU can communicate with
the DMA registers through the data bus to read from or write to the DMA registers.
When BG =1, the DMA can communicate directly with the memory by specifying an
address in the address bus and activating the RD or WR control.

DMA Transfer:
The CPU communicates with the DMA through the address and data buses as with
any interface unit. The DMA has its own address, which activates the DS and RS
lines. The CPU initializes the DMA through the data bus. Once the DMA receives the
start control command, it can transfer between the peripheral and the memory.
When BG = 0 the RD and WR are input lines allowing the CPU to communicate with
the internal DMA registers. When BG=1, the RD and WR are output lines from the
DMA controller to the random access memory to specify the read or write operation
of data.

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8.7. I/O Controllers

 The devices operate at wide-ranging data transfer speed and also many different
interface standards. The Keyboard, Mouse have very small data rates and are
asynchronous in data transfer to computer. Disk, Solid State Disks have high data
rates. USB has a mediocre data rate. And we know each one has a different
connector and interface standard.
 It is overloading on the part of CPU to deal with these devices directly. I/O
controllers play a bridging role between CPU, Memory and I/O Device by taking
care of all kinds of communication.
 Due to heterogeneity of the devices, each device /type of interface requires an I/O
Controller (Refer figure 20.1)
 I/O controllers also act as a buffer during data transfer

A data transfer from an I/O device involves:

 Initiate the operation (i.e. addressing the device)

 Direct the device (i.e. communicate the operation to be done and control the data
transfer)
 Closing of the IO operations ( i.e notifying the CPU that it is done or not done
with status).

To do the above, each IO Controller will typically have Data Register(s), Status
Register(s), Control Register(s), Address decoding logic and Control Circuitry as in
figure 20.2. The I/O Controller is connected to the system bus. Whenever the I/O
controller wants to use the bus, it has to contend and obtain. All communication from
the CPU and Memory happens via these registers shown in the diagram. These
registers are given a unique address for each I/O controller.

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The address decoding logic is connected to the address bus. The value on the address
bus indicates the register to be accessed. The decoding logic converts this as an
address selection signal to one of these registers.

The control circuitry is connected to the control signals of the system bus. These
signals are MEMW, MEMR, IOR, IOW, INTERRUPT, BREQ, etc. These signals
ensure the synchronization and validation of address and Data on the bus, demanding
the Bus for data transfer, sending interrupt after the normal or abnormal end operation.

The Data Registers take care of Data Transfer. There may be Data In and/or Data
Out Registers depending on the device. Also, fast devices like Disk will have a Buffer
so that the fast bulk data from the disk is stored and then sent to Memory when the
system bus is available.

The Control Register has information like:

 Which is the device to be accessed? (Address of the device)

 What is the Operation (Command) to be carried out on the device?

 Printer Commands – Form Feed for a new page, Print, Line Feed, status
check, etc.
 Disk – Seek, Write, Read, Reset, status check

 How this operation is to be carried out?

 Number of Bytes in case of Data Transfer

 What communication is expected by CPU after data transfer to memory

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 Mode Settings applicable to devices, etc.

The purpose of Status Register is:

 To have the information about the device being selected

 Whether the device is online and ready?

 If not online have the information about the error from the device. Example -
a) Printer may not have a cartridge or paper. This error status is collected in
the status register. b) The Disk may not be getting ON

 The status of the data transfer on the device side is stored as a flag in the Status
Register.

 Whether the data transfer was successful?

 Data Overrun or Underrun may occur with fast devices like DISK. The
buffer operates on PUSH – PULL mode. So in case of an error in PUSH or
PULL side Data Overrun or Underrun occurs.
 The status register keeps track of the Word Count pending to be transferred
from/to Memory. A Counter is maintained in the I/O controller for this
purpose. When Word Count becomes ZERO, it is implied that the data
transfer is successfully done.
 Interrupt bit is part of the Status Register. An Interrupt is reasoned with the
content of the status register.

8.8. Serial Communication

 A data communication processor is an I/O processor designed for
communication with remote terminals through data communication
networks.
 It handles tasks like distributing and collecting data from various
devices connected through communication lines.
 The computer appears to serve many users simultaneously in a time-
sharing environment by interspersing fragments of each network
demand efficiently.

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 Unlike I/O processors communicating through a common bus, data

communication processors communicate with each terminal through a
single pair of wires.
 Data and control information are transferred serially, resulting in a
slower transfer rate compared to common bus communication.
 The data communication processor communicates with CPU and
memory similar to any I/O processor.

Connecting Remote Terminals:

 Remote terminals connect to a data communication processor via

telephone lines or other communication facilities.

 Conversion devices like data sets, acoustic couplers, or modems are

used to convert digital signals to audio tones for transmission over
telephone lines.

 Different modulation schemes, communication media, and transmission

speeds are employed.

Transmission Methods:

 Communication lines may be connected to synchronous or

asynchronous interfaces based on the remote terminal's transmission
method.

 Asynchronous transmission uses start and stop bits in each character,

while synchronous transmission sends a continuous message without
start-stop bits.

 Synchronous transmission is more efficient but requires continuous

messages to maintain synchronism.

Error Detection

 Data communication processors check for transmission errors using

methods like parity checking in asynchronous transmission and

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techniques like longitudinal redundancy check (LRC) or cyclic

redundancy check (CRC) in synchronous transmission.

 LRC checks are calculated at the end of a block, and the receiving
station compares it with the transmitted LRC.

Transmission Modes:

 Data can be transmitted in three modes: simplex (one-way

communication), half-duplex (two-way, but one direction at a time),
and full-duplex (simultaneous two-way communication).

 Simplex is rarely used in data communication. Half-duplex requires a

turnaround time, and full-duplex can use either a four-wire link or
frequency spectrum subdivision in a two-wire circuit.

Data Link and Protocols

 The communication lines, modems, and equipment form a data link,

and orderly data transfer is governed by a protocol.

 Data link control protocols ensure the orderly transfer of information,

establish and terminate connections, identify sender and receiver,
handle error-free message passing, and manage control functions.

 Protocols are categorized into character-oriented and bit-oriented

protocols based on the framing technique used.

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Conclusion
Input-Output (I/O) organization facilitates communication between the CPU and
peripheral devices, involving hardware and software components. Key aspects include:
peripheral devices for input/output; interfaces for data translation; asynchronous data
transfer for concurrent CPU operation; various transfer modes like programmed I/O,
interrupt-driven I/O, and DMA for efficient data movement; priority interrupts for
timely handling of critical events; DMA for offloading CPU during data transfers;
Input-Output Controllers (IOCs) for simplified I/O management; and serial
communication for transmitting data bit-by-bit. Effective I/O organization is crucial
for maximizing system performance and responsiveness.

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Reference
1. COMPUTER SYSTEM ARCHITECTURE, MORRIS M. MANO, 3RD EDITION,
PRENTICE HALL INDIA.
2. HTTP://NPTEL.AC.IN/COURSES
3. Geeks for geeks tutorial: https://www.geeksforgeeks.org/io-interface-interrupt-
dma-mode/
4. M. Mano & W. Stallings: https://jagdishkapadnis.wordpress.com/wp-
content/uploads/2018/08/chapter7-input-output-organization.pdf

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