‫بسم هللا الرمحن الرحيم‬

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Introduction to Microprocessor

by

Dr. Ayman Mohamed

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 Goals for Today
 Today we want to learn about the microprocessor of a computer
- Pipeline and Non-pipeline microprocessor Architecture
- 8086 Microprocessor Features
- 8086 Microprocessor Architecture
- The 8086 Microprocessor Architecture Diagram
- An Execution Unit (EU)
- A Bus Interface Unit (BIU)

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Pipelining VS. Non-Pipelined Microprocessor Architecture
 Two ways to make CPU process information faster:
o Increase the working frequency (clock speed) – technology dependent.
o Change the internal architecture of the CPU
 Pipelining: It allows the CPU to fetch and execute at the same time. CPU
Fetching the next instruction while executing the current instruction is called
pipelining. This is done to speed up the program execution.
 Pipelining increases the efficiency of the microprocessor.

Wait

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

8086 Microprocessor Features:
 16-bit Arithmetic Logic Unit (ALU).
 16-bit internal and external data bus.
 Control bus and address bus, 220 = 1,048,576 = 1 MB, (20 is
called Address width). physical memory.
 The address refers to a byte in memory or I/O device.
 Memory is divided into segments of up to 64K bytes each.
 It can support up to 64K I/O ports.
 It provides 14, 16-bit registers.
 It has multiplexed address and data bus AD0- AD15 and A16 –
A19.
 It requires +5V power supply.
 A 40 pin dual in line package (DIP).
 Pipelined Microprocessor.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

The 8086 Microprocessor Architecture Diagram
The simplified block diagram is organized as two separate processors (functional unit) :

The8086 Processor Architecture block diagram

Introduction to Microprocessor ( Lecture 2 : 8086 MP)
The 8086 Microprocessor Architecture Diagram
The simplified block diagram is organized as two
separate processors (functional unit) :

The8086 Processor Architecture block diagram

Introduction to Microprocessor ( Lecture 2 : 8086 MP)
8086 Microprocessor Architecture
 The 8086 CPU logically has been partitioned into two functional units:
o Bus Interface Unit (BU).
o Execution Unit (EU).

 EU and BIU work in parallel, with the BIU keeping one step ahead.
 The major reason for this separation is to increase the processing speed
of the processor.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

8086 Microprocessor Architecture
1. Bus Interface Unit (BIU): handles all transfers data and addresses on the buses
required by the execution unit.
 It provides the interface of 8086 to external memory and I/O devices.
 It responsible for performing Operand Fetch & storage.
 It reads data from ports (I/O devices) and memory and writes data to
ports and memory.
 Bus control. It transfers of data and addresses on the buses for the execution
unit.
 It accesses memory and peripherals. i.e. Responsible for performing external
bus operations.
 It fetches instructions, instruction Queuing. It fetches instruction from
memory and stores them in the queue.
 Address Relocation. It generates the 20 bit physical address for memory
access.
 It sends out addresses.
 Bus Interface Unit (BIU) consists of:
 Instruction queue.
 Instruction pointer (IP).
 Segment register.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU:
The main components of the BIU are as follows:
 The Instruction queue:
o It is a 6 byte first in first out (FIFO) RAM used to implement pipelining. BIU
fetches the next six instruction bytes from the Code Segment and stores them into
the queue.
 to increase the execution speed of microprocessor (fetch and execute are
taking place concurrently (Pipeline).
o The queue is initially empty at the start up time only of microprocessor.
 Execution Unit (EU) removes instructions from the queue and executes them.
The queue is refilled when at least two bytes are empty as 8086 has a 16 bit
data bus.
o Pipelining fails when a branch occurs as the pre-fetched instructions are no longer
useful. It clears the entire queue.
 Now, the next six bytes from the new location (branch address) are fetched
and stored in the queue and pipelining continues.
o It operates with respect to bus cycles (machine cycles).
o This means it performs various machine cycles such as memory read, I/O read etc.
to transfer data with memory and I/O devices.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU (Cont.)
The main components of the BIU are as follows: PhysicalAddress
 Instruction pointer (IP): 00000H
o Common name for IP is PC (Program Counter).
o IP is 16-bit register contains the address of the next
instruction to be executed. 7000H 0000H
o It contains the offset address or displacement from Segment

….
address 64 K
the current code segment for the next instruction
that will be executed by the CPU. FFFFH

 The value in the CS register is added to the

value in the IP to obtain the real (or the
physical) address of an instruction.
o IP gets a new value whenever a branch occurs.
o The IP register cannot be directly modified.
o IP is not the operand of any instruction.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU (Cont.)
 Segment register: It holds the addresses of
Contains the
instructions and data in memory, which are used beginning
by the processor to access memory locations. address of
 It used to store the start address (the lowest each segment
addressed byte), base address of the segment, It is
16 bit registers. SS Register Address Stack
 There are four segments: segment
 Code Segment (CS) register: it holds the DS Register Address Data
program instruction codes. segment
o It is used for addressing a memory location
CS Register Address Code
in the code segment of the memory, where segment
the executable program is stored.
o CS holds the starting address of the code Segment
segment which contains the instructions, register
and the operating system links to that (in
CPU) memory
location to begin program execution. (MM)

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU (Cont.)
 Segment register: It holds the addresses of
Contains the
instructions and data in memory, which are used beginning
by the processor to access memory locations. address of
 It used to store the start address (the lowest each segment
addressed byte), base address of the segment, It is
16 bit registers. SS Register Address Stack
 There are four segments: segment
 Code Segment (CS) register: holds the DS Register Address Data
program instruction codes. segment
o It is used for addressing a memory location
CS Register Address Code
in the code segment of the memory, where segment
the executable program is stored.
o CS holds the starting address of the code Segment
segment which contains the instructions, register
and the operating system links to that (in
CPU) memory
location to begin program execution. (MM)

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU (Cont.)
 Segment registers:
 Data Segment (DS) register: stores data for
the program.
o It consists of data used by the program and
is accessed in the data segment by an offset
address or the content of other register that
holds the offset address.
o It is a 16-bit register containing address of
64KB segment with program data (where
variables are defined, constants are stored).
o By default, the processor assumes that all
data referenced by general registers (AX, BX,
CX, DX) and index register Source index
register (SI) and Destination index register
(DI) is located in the data segment.
o Data are accessed in the data segment by an
address or the contents of other registers
that hold the offset address.
o The address in DS register will be added with
the value in the address field to obtain the
real/physical address in data segment.
Introduction to Microprocessor ( Lecture 2 : 8086 MP)
 The main components of the BIU (Cont.)
 Segment registers:
 Stack Segment (SS) register: is used to
store interrupt and subroutine return
addresses.
o It handles memory to store data and
addresses during execution.
o It defines the area of memory used for the
stack (Last-in first-out). i.e. it is a section of
memory used by the CPU for temporary
storage of data and addresses for used by
the subroutines.
o It is used to hold the starting address of
the stack segment.
o The register content will be added with the
content in the Stack Pointer (SP) register to
obtain the top of the stack.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the BIU (Cont.)
 Segment registers:
 Extra Segment (ES) register : is an extra
data segment (often used for shared data)
o It is a 16-bit register containing address of
64KB segment, usually with program data.
o It is additional data segment, which is used
by the string to hold the extra destination
data.
o Used by some string (character data)
operations to handle memory addressing
o It is associated with the Data Index (DI)
register.
 By default, the processor assumes
that the DI register references the ES
segment in string manipulation
instructions.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

8086 Microprocessor Architecture
2. Execution Unit (EU) functions:
o It gives instructions to BIU stating from where to fetch the data and instructions
then decode and execute those instructions.
o It controls the operations on data using the instruction decoder & ALU.
o It performs arithmetic, logic and internal data transfer operations within the
microprocessor.
o It has no direct connection with system buses, it performs operations over data
through BIU.
o It sends request signals to the BIU to access the external module.
o It operates with respect to T-stats (clock cycles) and does not depend upon which
machine cycle is being performed by the BIU.
o It contains the complete infrastructure required to execute an instruction .

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The main components of the EU
 Execution Unit (EU) contains:
o Control unit.
o Instruction decoder.
o Arithmetic and logic unit (ALU).
o Registers.
 General Purpose registers.
 Special purpose Registers.
 Pointer and Index register.
 Flag register.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Main Components of Execution Unit (EU)
 The Execution Unit (EU) consists of:
o Control unit: is responsible for the co-ordination of all other units of the
P system. It generates different internal or external control signals
required to perform the operation.
o Instruction decoder: translates the instructions fetched from the
memory to generate different internal or external control signals required
to perform the operation that are carried out by the EU.
o Arithmetic and Logical Unit (ALU): A 16-bit performs various
arithmetic and logical operations over the data and performs shift and
rotate operations that may either be arithmetic or logical in nature.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 Main Components of Execution Unit (EU) (Cont.):
 Register: is a set of internal storage locations within the CPU with a high-
speed (a high-speed memory locations in the CPU).
 General registers: 8086 microprocessor has four 16 bit general purpose
registers AX, BX, CX and DX. These are available to the programmer for
storing values during programs execution for temporary storage and
manipulation of data and instructions.
Each of these can be divided into two 8 bit registers such as AH, Al;
BH, BL; etc. they are:

Register Special Purpose

AX Multiply/divide
BX Index register for move instruction
CX Count register for string operations
DX Port address for IN and OUT

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 Main Components of Execution Unit (EU) (Cont.):
 General registers:
o Accumulator register (AX): consists of two 8-bit registers AL and AH,
which can be combined together and used as a 16-bit register AX. It can be
used for I/O operations and string manipulation. it often holds the temporary
result after an arithmetic and logic operation.
o Base register (BX): consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX. It is used to store the
starting base address of the memory area within the data segment. It register
usually contains a data pointer/ memory address (offset address) used for
based, based indexed or register indirect addressing mode of memory.
o Count register (CX): consists of two 8-bit registers CL and CH, which can
be combined together and used as a 16-bit register CX Count register can be
used as a counter in string manipulation and shift/rotate instructions.
o Data register (DX): consists of two 8-bit registers DL and DH, which can
be combined together and used as a 16-bit register DX. It can be used as a
port address in I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high order word of the initial or resulting
number

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Main Components of Execution Unit (EU) (Cont.):
 The pointer (SP,BP) and index registers (SI,DI) are four 16-bit registers
unlike the data registers, cannot be accessed as a low or high byte.
 They are used to index or point to the memory location holding the
operand data for many instructions.
• Both are used in string manipulation instructions and it is associated
with the ES register.
 They are:
o Source Index (SI): It is used for indexed, based indexed and
register indirect addressing, as well as a source data addresses in
string manipulation instructions.
o Destination Index (DI): It is used for indexed, based indexed and
register indirect addressing, as well as a destination data addresses in
string manipulation instructions.
o Stack Pointer (SP): It stores the displacement value that will be
combined with the value in the SS register to obtain the top of the
stack.
o Base Pointer (BP): it points to data in stack segment.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Execution Unit (EU): Flag Register
Process Status Word Auxiliary Carry Flag Carry Flag

This is set, if there is a carry from the lowest This flag is set, when there is a carry
nibble, i.e, bit three during addition, or borrow for out of MSB in case of addition or a
the lowest nibble, i.e, bit three, during subtraction. borrow in case of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the result of This flag is set, if the result of the This flag is set to 1, if the lower byte of the
any computation is negative computation or comparison performed result contains even number of 1’s ; for
by an instruction is zero, else it is set to 0. odd number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor enters the
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
single step execution mode by generating
enough to accommodate in a destination register. The result is of more than 7-bits in
size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit
internal interrupts after the execution of
sign operations, then the overflow will be set. each instruction (Debugging Mode).

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto Causes the 8086 to recognize external mask
incrementing mode. Otherwise, the string is processed from the highest address interrupts; clearing IF disables these interrupts.
towards the lowest address, i.e., auto incrementing mode.
Introduction to Microprocessor ( Lecture 2 : 8086 MP)
 Processor Status Word: FLAG Register

 Flag register: is a 9-bits of its 16 bits contains bits that show the status
of some activities of the microprocessor.
 Zero flag (ZF) : Set if result of arithmetic or logical of the most recent
instruction was zero; cleared otherwise
 Sign flag (SF): Set if result of arithmetic of the signed numbers or logical
has a negative sign; cleared otherwise (i.e. the most significant bit - the
sign bit is 1).
 overflow flag (OF): set if there was an overflow for signed operations
(a carry/borrow from the second most-significant bit)
 Cary flag (CF): Set if there was a carry from or borrow to the most
significant bit during last result calculation
 auxiliary carry flag (AF): set if there was a carry from or borrow to bits 0-3
in the AL register; cleared otherwise. It is used by instructions that
perform binary coded decimal (BCD) arithmetic.
Introduction to Microprocessor ( Lecture 2 : 8086 MP)
 FLAG Register

 Interrupt enable flag (IF): set this bit to enable external interrupts (such as
keyboard entry) are to be processed or ignored; Clear otherwise.
 Single-step (Trap Flag TF) causes the 8086 to execute a single-step mode i.e.
one instruction at a time for “debugging” process. TF is cleared by the single-
step interrupt.
 Direction flag (DF): Determines left or right direction for moving or comparing
string (character) data. When it is cleared (DF=0), the string operation is
performed from left to right data transfer, and when it is set (DF=1), the
string operation is performed from right to left data transfer (auto –
decrement ).
 Parity flag (PF): Set if low-order 8 bits of result contain an even number of 1
bits; (set if parity (the number of "1" bits) in the low-order byte of the result
is even) cleared otherwise.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Execution Unit - Flags

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

8086 Microprocessor Architecture
The EU and BIU are connected through the system buses:
 Data Bus:
o It is bi-directional the data signals that travel out of and into the P.
o The number of wires in the data bus depends on the word size that the
P operates with.
o An 8-bit P will have a data bus consisting of 8 wires and a 32-bit P will
have a data bus with 32 wires.
o It is 16-bit size in 8086 P.
 Control Bus:
o It consists of wires, some of which carry signals from the CPU to
external devices, while others carry signals from external devices to the
CPU.
o It is the number of wires present in the control bus.
o It varies from one P to another.
o Examples of control bus signals are READ, WAIT, READY, and HOLD.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

8086 Microprocessor Architecture
 Address Bus:
o It is the wires that carry the CPU generated address signals out to
memory and to I/O devices.
o The address signals only travel outwards from the CPU (unidirectional)
to the destination.
o The number of address lines that a microprocessor has determines the
size of the memory space that it can access.

No of Add. lines Size of memory space

Fetch Time of instruction
or operand depends on 8 28 = 256
 Access time of primary 16 216 = 65 536 = 64 K
memory
 Activity on System Bus 20 220 = 1 048 576 = 1 M
24 224 = 16 777 216 = 16 M
32 232 = 4 294 967 296 = 4 G

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 8086 Microprocessor Memory Segments:
 The CS,SS,DS,ES segments registers contain a 16-bit
base address that points to the lowest addressed byte
of the segment.
 So that the segment registers cannot store 20 bits, they
only store the upper 16 bits.
 Thus the CS, DS, ES, SS segment registers,
respectively contain the segment addresses for the
Code, Data, Extra and Stack segments.

How is a 20-bit address obtained if there are only 16-

bit registers?

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 The 8086 Memory Segmentation
 Memory Segmentation is the process in which the main
memory is divided into different segments and each segment has
its own base address.
 The segment position in the memory is not fixed and can be
determined by the programmer.
 They may or may not be physical separated.
 Segmentation is used to increase the execution speed of
computer system so that processor can able to fetch and execute
the data from memory easily and fast.
 It allows the memory capacity to be 1 MB although the actual
addresses to be handled are of 16-bit size address width registers
 It allows the placing of code data and stack portions of the same
program in different parts (segments) of memory, for data and
code protection.
 It permits a program and/ or its data to be put into different
areas of memory each time program is executed.
 Segments allow two processes to easily share data.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

 8086 Microprocessor Memory Segments:
 Segments are special areas in the memory that
includes up to 64KB = 216 B.
 The 8086 architecture uses the concept of
segmented memory.
 It can able to access a memory capacity of up
to 1 megabyte.
 This 1 megabyte of memory is divided into 16
logical segments.

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

The main components of the BIU (Cont.)
The main components of the BIU are as follows:
 Address Adder or Address Generation Circuit:
o The BIU has a Physical Address Generation Circuit. It generates
the 20 bit physical address using Segment and Offset addresses
using the formula:
Physical Address = Segment Address x 10H + Offset Address

 All memory locations within a segment are relative to the segment’s

starting address (base address, also is called segment address).
 The distance in bytes from the segment address to another location
within the segment is expressed as an offset (or displacement).

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

The segment and offset address:

Introduction to Microprocessor ( Lecture 2 : 8086 MP)

Questions?

Introduction to Microprocessor ( Lecture 2 : 8086 MP)