ADVANCED PROCESSOR ARCHITECTURES

AND MEMORY ORGANISATION –

Lesson-3: ARM

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 1. ARM ARCHITECTURE

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 The ARM architecture processors
popular in Devices and Mobile systems

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 ARM Features
 32-bit architecture but supports 16 bit
or 8 bit data types also.
 Programmable as little endian or big
endian data alignment in memory.

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 ARM Features
 Advantage of using a CISC in terms of
functionality, along with the advantage
of an RISC in terms of faster program
implementation as well as reduced code
lengths.

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ARM7, ARM9 and ARM 11 microprocessors
 ARM processor has an RISC core for
processing
 Combination of RISC and CISC
features─ ARM supports to a complex
addressing modes based instruction set

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 In-built compilation unit

 Compiles the CISC instructions into

RISC formats, which are then
implemented by the RISC core of the
processor.
 Internally the implementation for many
instructions is like in an RISC (without
the micro-programmed unit)

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 Jazelle technology

 Faster Java codes execution

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 ARM Thumb 16-bit instructions
 Thumb Set designed for 16-bit word
lengths and instructions, which
internally executes by same 32-bit
core.
 Instruction fetch of 2 bytes in Thumb
mode in place of 4 bytes in ARM
mod.

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 ARM Thumb 16-bit instructions
 Data alignment at steps of 2 bytes in
Thumb mode in place of 4 bytes ARM
mode
 Memory savings up to 35%, over the
equivalent 32-bit code, while retaining
all the benefits of a 32-bit system (such
as access to a full 32-bit address
space).
 Enables 32-bit performance at the
8/16-bit system cost in terms of
memory needs.
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 Thumb and 32-bit ARM modes
 Switch from one mode to another
 No overheads (in terms of time and
memory) in moving between Thumb
and the normal ARM state of the
codes. Two states are compatible on a
normal basis.
 Gives code designer complete control
over performance and code-size
optimisation
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 ARM7 versions
 ARM7TDMI® (Integer Core)
 ARM7TDMI-S™, (Synthesisable
version of ARM7TDMI)
 ARM7EJ-S™ (Synthesisable core with
DSP and Jazelle technology)

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 ARM7 versions
 ARM720T™ (cached processor
macrocell , 8K Cached Core with
Memory Management Unit (MMU)
supporting operating systems1
including Windows CE, Palm OS,
Symbian OS and Linux)
 130 MIPS using Dhrystone 2.1
benchmark in typical 0.13µm process

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 ARM9 versions
 ARM920T (Dual 16k caches with MMU support
multiple OSs.
 ARM922T (Dual 8k caches for applications
support multiple OSs1.
 ARM940T™ (Dual 4k caches for embedded
control applications running a RTOS)
 32-bit RISC processor core Super scaling 5-stage
integer pipeline. 8-entry write buffers to avoid
blocking the processor on external memory writes
 Achieves 1.1 MIPS/MHz, 300 MIPS (Dhrystone
2.1) in a typical 0.13µm process

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 ARM11 versions
 Families with ARMv6 instruction set architecture
that includes the Thumb® extensions for code
density, Jazelle™ technology for Java™
acceleration, ARM DSP extensions, and SIMD
media processing extensions. MMU) supporting
operating systems1 and palm OS
 32-bit RISC processor core with 8-stage integer
pipeline, static and dynamic branch prediction,
and separate load-store and arithmetic pipelines to
maximize instruction throughput
 Targets a performance range of Dhrystone MIPS
400 to 1200
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 Memory Architecture
• ARM7 has Princeton memory
architecture.
• ARM9 processor has Harvard
architecture

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 Faster implementation and Reduced code
lengths
 Due to the instant availability of the
register word to the execution-unit.
 Reduced code lengths─ Most
instructions use registers as operands.
 Few bits in the instruction specify a
register as operand. 8, 16 or 32 bits
specify a memory address as operand
and the displacement bits in the
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instruction.
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 ARM registers
 R0 to R15.
 R15 also function as program
counter.
 R14 function as link register.
 R13 may be used as stack pointer
 CPSR (current program status
register)
 SPSR (saved program status register).
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32-bit bus
ARM Architecture

Barrel
IR
Shifter
r0 ID ALU,
to
r15
Execution
CPSR unit
SPSR
Hardwired
32-bit r15 circuits for
functions each
as PC instruction
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 ARM Codes
 ARM Codes─ Forward compatible with higher
versions.
 ARM7 codes ─ Forward compatible with
ARM9, ARM9E and ARM10 processors as well
as Intel XScale micro-architecture.
 ARM9E and ARM 10 families use a Vector
Floating Point (VFP) ARM coprocessor, which
adds full floating point operands.
 VFP also provides fast development in SoC
design when using tools like MatLab®.
 Applications are in image processing (scaling),
2D and 3D transformations, font generation and
digital filters.

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 ARM Intelligent Energy Manager (IEM)
technology
 Advanced algorithms to optimally
balance processor workload and energy
consumption.
 Maximizes system responsiveness.
 IEM works with the operating system
and mobile OS.
 Application running on a mobile phone
dynamically adjusts the required CPU
2015 performance level.
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 ARM processors AHB (AMBA Advanced
High Performance Bus) interface

 AMBA an established open source

specification for on-chip interconnects.
 AMBA serves as a framework for SoC
designs and development of the IP
library.
 AHB support in all new ARM cores.

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 AHB
 Provides a high-performance and fully
synchronous back plane. (Back plane means
additional set of controllers, which can access
another common bus, which is distinct from
system bus in a multilevel buses in the system.)
 Multi-layer AHB in version ARM926EJ-S and all
members of the ARM10 family represents a
significant advancement. It reduces access
latencies and increases the bandwidth available to
multi-master systems

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 3- stage pipeline in ARM7
Successive Clock Intervals
Stages
Fetch I1 I2 I3 I4 I5 I6

Decode
Read I1 I2 I3 I4 I5
Operands

Execute
Write I1 I2 I3 I4
back

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 Pipeline and Latch

Decode Execute In,

Fetched an In and and mem-ory
Latch Latch inputs I and
instruction In read n
operands address and
Write Result
In

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 5- stage pipeline in ARM 9
Successive Clock Intervals
Stages
Fetch I1 I2 I3 I4 I5 I6

Decode I1 I2 I3 I4 I5
Read I1 I2 I3 I4
Operands
Execute I1 I2 I3

Write I1 I2
back
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 Super scaling in ARM

Stages Pipeline1 Pipeline 2

Fetch I3 I’3
Decode
Read I2 I’2
Operands

Execute
Write I1 I’1
back
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 2. ARM Instruction Set

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 Features

• Two Instruction Sets─ 16-bit Thumb

and 32-bit ARM mode instructions
• Operations on 8-bit or 16-bit or 32-bit
data types
• Data alignment in memory: Two byte
words in Thumb set and Four in 32-bit
ARM mode

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 ARM7 instruction set: Data Transfer
Instructions
 Register-load a byte (LDRB).
 Register- byte store (STRB).
 Register Half Word store (STRH). [A
word in ARM is of 32 bits].
 Register-load Half Word as such or
signed (LDRH or LDRSH).

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 ARM7 instruction set: Data Transfer
Instructions
 Instructions for transfer between the
register-memories. The memory
address is as per a register used as
index or index-relative or post auto-
index addressing mode.
 Register-load a word (LDR)


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 ARM7 instruction set: Data Transfer
Instructions
 Register-word stores a word (STR).
 Set a memory address into a register
(ADR). Address is of 12 bits.
[Alternative for 16 bits address setting
in a register is using any register or r15
in an arithmetic operation].

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 Word transfer between registers:

 Move (MOV).
 Move after Negating (MVR).

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 Load or move or store instruction
conditionally implementation

 Conditions─ signed number LT, GT ,

LE, EQ, NE (not equal), VS (overflow),
VC (no overflow), GE
 Conditions─ unsigned number HI
(higher), LS (lower), PL (plus, nor
Negative), MI (minus), CC (carry bit
reset), and CS (carry bit set).
 Example: MOVLT r3, #10.
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 Load or move or store instruction
conditionally implementation

 Immediate operand 10 to r3 provided a

previous instruction for comparison
showed the first source as less than the
second.

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Bit Transfer or Manipulation Instructions

 Register- bits Logical Left Shift

(LSL).
 Register- bits Logical Left arithmetic
Shift (ASL).
 Register- bits Logical Right Shift
(LSR).
 Register- bits Logical Right
arithmetic Shift (ASR).

2015
Register- bits Rotate Right (ROR).
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 Arithmetical Instructions
• Three operands from the registers.
• One source may however, be by immediate operand
addressing in addition and subtraction .
 Add without carry two words and the result is in the
third operand (ADD).
 Add with carry two words and the result is in the
third operand (ADC).
 Subtract without carry two words and the result is in
the third operand (SUB). [Carry bit used as borrow.]
 Subtract with carry two words and the result is in
the third operand (SBC).

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 Arithmetical Instructions

 Subtract reverse (second source with the first)

without carry two words and the result is in the third
operand (RSB). [Carry bit used as borrow.]
 Subtract reverse with carry two words and the result
is in the third operand (RSC).
 Multiply two different registers and the result is in
the destined register (MUL).
 Multiply two source registers and add the result with
the third source register and accumulate the new
result in a destined register. (MLA).

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 Logic Instructions
 Bit wise OR two words and the result
is in the third operand. (ORR).
 Bit wise AND two words and the
result is in the third operand. (AND).
 Bit wise Exclusive OR two words
and the result is in the third operand.
(EOR).

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 Logic Instructions
 Clear a Bit (BIC). [There is one
source for the bits; a second source
for the mask and the result is at the
third operand.]

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Arithmetical or logical instruction conditional
implementation
 Example, SUBGE r1, r3, r5. The
operand from r3 is subtracted from r5
if the GE condition resulted earlier (N
and V status bits equal on comparison
of two signed numbers).
 Conditions can be the results of a
comparison or test

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 Compare and Test Instructions

 The result destines to CPSR, which

stores the four condition bits, N, V, C,
and Z.
 Bit wise Test two words (TST).
 Bit wise Negated Test between two
words (TEQ).

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 Compare and Test Instructions

 Compare two words and the result is at

the CPSR condition bits (CMP).
 Compare two negative words and the
result is at the CPSR condition bits
(CMN).

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 Program-Flow Control Instructions
 Branching (B) or Branch conditional
operations.
 Branch to an address relative to PC
word in r15 (B) 'B #1A8' means add
in PC 1A8 and change the program
flow.

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 Program-Flow Control Instructions
 'BGE #100' means that if a GE
condition resulted on a compare 0
test, add in PC 1A8.
 Similar instructions for different
conditions of the processor status
flags

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 Software Interrupt instruction
 SWI has 8-bit opcode and remaining bits
are not used by processor
 Give single vector address of the ISR for
SWI.
 Remaining bits in SWI backtracked by
programmer to compute ISR and ISR
parameter pointers

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 Software Interrupt instruction
 Remaining bits in SWI backtracked by
programmer to compute ISR and ISR
parameter pointers
 This feature permits handling large
number of SWIs required in the OS and
application functions or threads or tasks

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 Summary
We learnt
• ARM Architecture
• 32- address bus and 64-bit data bus
• Programmability as Little endian or
Big endian
• Princeton Memory in ARM7 and
Harvard in ARM9

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 Summary

We learnt
• 16 Registers with R15 as Program
counter
• 16-bit Thumb set for 16-bit
instructions to reduce external memory
requirement

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 Summary

We learnt
• 3 stage pipeline in ARM7 and 5 in
ARM9

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 End of Lesson 3 of Chapter 4
on
ARM Architecture and Instructions

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