78 3.

Testable Combinational Logic Circuit Design

I tty pres erving concLr-

J. Vasudevamurthy. "The testa b·1·
3.6 R8J·ski• J. R. ' and
. . . . . \
reot decoropos1t1on and factonzauon of Boolean express1o • ns,. ,. IEEE Trans.
',
on CAD, 778-793 (June 1992). . ,
n. •
3.7 Barek, M. J., and J. P. Hayes, • 'Test set pre erving logic transfonnat,o .
Proc. Intl. Test Conf. 454-458 ( 1993).
3.8 Krasniewski, A., "Can redundancy enhance testability?" Proc. Intl. TeSr
Conj., 483-491 (1991). . .
3.9 Krasniewski, A., «Logic synthesis for efficient pseudoex.hausnve testabil-
ity,·• Proc. Intl. Test Conf. 66-72 (1991).
3. IO Kundu, S., and A. K. Pramanick, ..Testability preserving Boolean trans -
fonnation for logic syntbesis." Proc. IEEE VLSI Test Symp., 131-1 3 8
(1993).
3. 1 I Lin, C. J., and S. M. Reddy, • 'On delay fault testing in logic circuiLc;,'' I£EE
Trans. on CAD, 694-703 (September I 987).
3. 12 Ostapko, D., and S. J. Hong, "Fault analysis and test generation for p ro­
grammable logic arrays,"' IEEE Trans. Comput., 617-626 (September
1979).
3.13 Cha, C. W., "A testing strategy for PLAs," Proc. 15th Design Automation
Conf, 326-334 (1978).
3.14 Smith, 1., "Detection of faults in programmable logic arrays," IEEE Trans.
Compur .. 845-853 (November 1979).
3.15 Agarwal. V., "Multiple fault detection in programmable logic arrays,"
Proc. Symp. Fault-Tolerant Computing, 227-234 (1979 ).
3.16 Fujiwara. H., K. Kinoshita, and H. Ozaki, "Universal test set for program­
mable logic arrays," Proc. Symp. Fault-Tolerant Computing, 137-142
( I 980).
3 . .17 Bose, D., and J. Abraham, • ·Test generation for programmable logic ar­
rays," Proc. 19th Design Automation Conj., 574-580 (1982).
3. J 8 Law, H. F., and M. Shoji, "'PLA design for the BELLMAC-32A micro­
processor," Proc. Intl. Conf on Circuits and Components, 161-164 (1982).
3. 19 Hong, S. J., and D. L. Ostapko, ''RT-PLA: A programmable logic array
for function independent testing." Proc. Symp. Fault-Tolerant Comp
uting,
131-136 (1980).
3.20 Fujiwara, H., "A new PLA design for universal testability
," IEEE Trans.
Comput., 745-750 (August 1984).
3.21 Khakbaz, J., "A testable PLA design with low overhead
and high fault
coverage," IEEE Trans. Comput., 743-745 (August 1984).
3.22 Bozo�g�i-Nesbat, S., and E. J. McCluskey
, '•Low.er overhead design for
tcstab1hty of programmable logic arrays," IEEE
Trans. Comput., 379-383
(April 1986 ).
 Chapter 4 Test Generation for
\ ·eqoential Circuits

r
\

� logic circuit the output of which !_�nds not only on the present values of the
mputs but also on the past value of the inputs is known as a sequential circuit.

Ir
The mathematical model of a synchronous sequential circuit is usual\)' re erre
to as_ a sequential machine or a ftnire stare machine. Hencefonb, a, ynchronou
sequential circuit will be referred to as a sequential circuit. Figure 4, l show the
general model of a synchronous sequential cfrcuit. As-can be seen from the dia­
gram, sequential circuits are basically combinational circuits with memory to re­
membi; past inputs. The co�bi�ational part of the circuit recci�; two �ts ·of
inpuf signafs:__pii_mary (coming from the external environment) �nd_secondary
(coming from the �irlory elements). The particular combination of secondary
--------:-·- --- ·---- -
--
input variables at a given time is called the present stare of the circuh; the sec-
ondary input variable;�so k.nown asTtac;-;;;fables. 1f there are m secondary
�_bles in a sequentiif circuit, then the circuit can be in any one of 2"'
different present states. The outputs of the compinational pan of the circuit are
c!!,vided into two sets. The primary outputs are available to conl!��o egt_ions in
the �ircuit enviro�ment. wh�is the �nda.ry outputs a� ·used to . -pecify the

---
next sit1te to be assumed by the memory .
.....

4.1 Testing of Sequential Circuits

as Iterative Combinational Circuits

Te-8t &rJler,ation for SC<J_���.��ts is extremelr_c!!.f c t becaus� the �ha�ior

of a sequential circuit depends both on e resent and on ��g�t m uts. It tak�s
- • - - ·--- ·---- • sequenttal
an entire sequence o(foputs to detect many of the possible faults m a

t
 •
80 4. Tes �cncr1Hlon for �c<111cntlol Clrcuii
r, •
·'
,)
,) ' 'I Pr'imnry Primary
\
,iriput�· ourput
, r' ombi national
,. ( " lo ,j c
''
' ·- .,..
"'
\ . •..· ,,,,
,./ 1· ()
Pre cm
lita.te
Next
liHILC
"· ,.

·- '
"�,, ;

FF
' �- ,_
( CJock
,\.
., Figure 4.l Synchronous i-equential circuit
r ) /' ,,
C

circuit. Ooe of the earliest approaches for denying tests for sequentfal circuits
involves conver ion of a �l!..CllJ:iatc·rc,uitJo.to..a one-dimensional array of iden­
tical comoinaiionaJcf;;uils. Most techniques for gene�ating 'i.est�-for ;��bi�;.·:
�uilS can then be";pplied.
Figure 4.2 shows how n copie of the same sequential circuit are intercon­
nected so that the state of the first is communicated to the second, the state of the
second copy is communicated to the third, and so forth. I,!!_t,be dia_sram x(i).,l(D.!,...
_____..._ - ·---
and ::(i), associated with the ith co y of the circuit, correspond to the input, the
-�,..,
).
'or u,ne. -- -- - • --
next state, and the output respectively, of the sequential circuit at the ith instant

The circuit of Fig. 4.2 js a com inp.tignaLnet_w..ork, �-�y_se it consists of a

casca.de of identical cells, each lfuving-apalf ot inputs (to receive input signa1s

.r( I) z( I) x(2) :(2) x(n)- z(11)

Combinational tombinat.ionol •••••••• Combinational

logic logic Jog.ic
Initial ,v(2) y(n)
stare /1
I I
I I
I I
I I
I I
I I
"-----'t I
I I
I I
._______, I

Figure 4.2 Ilerative model of the sequential network

 4.2 State 'fable Verlfkation 81

left) 31Jg_3 pair of outpu t � (to supply

and informa tion from its neighh<>r cell on the
info rma tion (o its neig hbor on rhe right
and to the network ou�purs). Thu,;, the
t he prob lem of te14ti ng synchron U'1
t runs form ution indi cated in Fig. 4.2 replace,
for the i terat ive combina tional
Rcqucntla l circu it� by rhe problem of find ing te ts
network .
ri al faultcs in t� i �ati v_c
each fault in t he sequ cntia J n.et�1ork Jea�:h l to ...n i£kn �
nctwo r.k'; ond no the.pro�� f@1� £C_!ec tipn in a sy� �
hr nous seq �enc: al c1rcu1t
1n a comb mauo nal ne:
-ca,1-bc treat.cd..Alh, problem of mult iple-fa ult de{e£t1on
complex ity
work. Thc i��rcased numbe r of fault, to be considered and the extra
rcuits. More­
ofth;rcpl, cated logic make this �h?Jaue unrealutic for �lex �
over, ii is necessary to derive test sequencej that can detect a fault mdependently
of the initial state of a circuit. Thfa requi re� dp-jyi9J!.Q!]_Qf_�st �eocei f.CJ.r .�II
possible initial �tat.es, and then constructing a 5e9u,ena !h!t �IJ ��!� fault
i.;'aii �cases. ·However, this may not be computatio,naJJy feasible.
-�--
4.2 State Table Verification

ln this approach, a sequential �i!cuit is tested by performing an !,_Xperimenr on it,

t!1 at is, by_�,elying an input signal,.,a� observing. the oatpot [4. l ,4.2J. Hence, the
testing problem may be stated as follows: Given the sta:te table of a
---------,.� ----
�achin:.!. find an i nput/OU,lpJJ1 ��. e�ir {K,.� umthat the: (e5J;i)�fl. the
jaJ

m,�ghine 10 ,X w.il!J>e Z if and onl if � f?.3Chlne_ls_o�atin £�rrectJy. The

application of this input sequence X and the observ�tion of the response. to see
if it is Z, is called a ca1cJ...jng e,xperimep: the sequence pair (X, Z) is referred to
I
as a c':!_���!LG.,!equence.
• �-

Checking experiments are clc!5sifi� either as ' 'adaQtive ' ' or · ' R!eset' • In adap-
ti_y� e�P._Cfi!U�Js, the �9Jc� of_t)le input symbols is based on the output ymbols
p_i:_od1:1��d.by .�_'!1achjf�! �arlie__1 Jn th� e�r.iment. In preset experiments, the entire
input seque�� i..:� _c <2..mpl�_tely �ci tied in advance. A measure oiTfficiency of an
-
C?(periment is its le11�rh. which is the total number of input sy mbols applied to
the machine during the execution of an experiment. The deriva.lion of checking
- .. --... .
sequence is based on the folJowing assumptions: --
-� _____....
..,............
......... ..........,..,.
I . Th...e ne1warkjtfi!!!Y ��c! fied and ?� ��rmj�i:'> �c. ln a deterministic ma­
chine, the next state is detennine<.J uniquely by the present state and the
present input.
2. 12!,e •;etwork i� stronglx conn�ct�. that is, for every pa ir of stales q; and
,
Q; of the ne1work, there exists an input sequence that takes the network
- --- ---��- ••
-·-
from q, to q1 .
... ___..,,
 4. Test Generation for Seq uential Circuits
82
� -tho ��l is ted
3. The network in the presence of faults has no more stat s �-
e

: f i ll in�ease the num� r of

�!fi_1::�tion:-inotber words no � _
states.
w t he initial stare of t he
To d.esign checking exr>(;rimen� i t is nece ary to kno
homing seQ1!._ence.,
netw�rk . which is determined by a distinguishing or a
� inpu r sequence is said Lo be a, homjJJg ,!equence Jor a_�i!£P.i�e i f
e !f
sponse t2.;�e.!.C:-S�n;e !s..aJ�Y�.s�ffi cieJ!l �2, d�t��� �_n• u��.Y.�tc;
�achi���-r:, It has a homJng
final state. For an example, conside r the machine of Fig. 4.3.
se<JUe';-; 1 0 1 , for, as indicated in Fig. 4.4, each of the output sequenc es that
e. A
might result from the application of 1 0 I is associated with just one fi!!_a}_ ��at
homing sequen� need not a_! way� leave a mach · e i n..,!�ame finf:!_L�ta_j,e ; it is
cmly necessary that the final s�e c� be identj_fi� fr.£!11 th;_ �;��quence •.
A cl/stinguishiag sequence is an i n ut seq uence that. when ae.P.lie� t,? ,a 1!!_a­
cbine. wiJJ produce
.... ... - -- -· -- --
a different output sequence for each choice
....... _.,, . .. __ --- - - _,. -
For e xample, 1 01 is also a disting_uishin_g_seg{!Cn� for - �_achine �of Fig. 4.3.
of initial state .
--,-----�· ·......,.._,�

As shown io Fig. 4.4. the output sequence that the machine produces in response
to J O I uniquely specifies its initial state. Evert,?-isting2 ishin$�uen� is ¥so a
��-;:9uence because the know1 e o•f the initial ;"tate and the inJ>!U.§AAYeJJ�
is �l�ays su�ficient !?--2.e!:ED .J!ie h l!E".9�eft_ �� ���'- sEt� �.�eJ!· �!,he other
hand, nor every homing uence is a distinguishing sequence. For example the ,

machine of Fig. 4.5(a) has a homing sequence 0 1 0. As shown in Fig. 4.5(b), the
- ,.--.,,, - ------- .. . _,,.....
�-""'-- ,,,.._..,.,_,_ -· ...
.,, ..,, ,. ,.,1. ..... - ,... _

output sequence produced in response to 0 1 0 u�uely specifies the final state of

Machine N but cannot distinguish between the initial states C and D. &X�,O' �::... _
_
duced sequential machine . ssesses a homing sequence. whereas only a limited
nur,nber o machines have distinguish ing sequences. - -- • � -- ·-· - - • • •
At the start of an experiment a machine can be in any of its n states. In such
a case, th<; initial uncertainty regarding the state of the machin e is the· set that
< _____,....... -·-� - ..
Input
Present state x=0 x= 1

A C, J D,O
B D.O 8,1
C 8,0 C, I
D c,o A ,O
ext state. output
Figure 4.3 State table of Machine M
 •
4.2 State Table Verification 83

Initial state Output stquence Final state

A 0 0 l C
B 0 0 A
C I 0 B
D 0 C
Figure 4.4 Response of M chine M to homing sequence 101

�own to contam
-
contains all the states of the machine. A collection of states of the machine that
TJ(eseo state is referred to as the unc;rtainty. the u-ncer-
.
---- - --------
ra,niyof-;-ruc.hiru:- s ...thus an�subset of the state of the machine: For example.
- --
Machine M of Fig. 4.3 can !!!itially be in any o its four tates; hence, tbe_initial
uncenainty is (ABCQ). H an inpot I is applied to the machine. the successor
uncertainty will be .�Dl .or -� depending on whether the output is O or l ,
_ A
respectiv,ely. The uncertainties (CXDBC) are the 0-snccessors of (BCD). A suc­
cessor tree, which is defined
_.__
for a �citied macliine
"'"- � -- __.., ,_,... _,,.__ _
and a �ven --
- - .... initial oncer-
�-r:1�'!- �cture that displays gra-phicall)'.- the .x,-successoT uneertaimies. for
•

�YS!Y. ssible inp� �uence _x,. _ _

A collection of unccrtaj.!!,�es � rt;f�rr��--�.. as_3!1_ UJZCe aiJ:tl::i. e'=!,O.k tne i di­
- ,
�_& uncertajn�s contained in the vectoT arc called the_co . onenls of the
vector. � uncertainty vector the components of which contam a single tate each
is said to be a trivial uncutainzy vecto� An uncertainty vecto:r the components
of which cont.Jn cithcr single states or identical rel)Cated states is aid to be a
homogeneous uncercain.ty vector. For example. the vectors (M) B)(C). and
(A)(B)(A) C) are homogeneous and trivial, respectively.
'-!:: 4=P" seq�
A/fi'oiing
===-
is obtained from the homing tree� a homing tree is a
- -=- --·

Present Input Present Response F"mal

state x=O X =l state to 010 state

8,0 D.O A 0 0 0 A
B A,0 B,O B 0 0 l D
C D,l A,0 C 0 D
D D.l c,o D \ 0 l D
(a) (b)
Figurt 4.5 (a) Machine ; (b) response of Machine to 1 0 1
84 4. Test Generation for Sequeniial Circuits

successor tree in which a node becomes-·terminal

-
if one of the following conditions
.-
-·---
occurs:
--.. ..
I . The node is associated with an uncertainty vector the nonhornogeneous
components of which are associated with the same node at .� preceding
, '- • . " ,,• •"' ,, , I '1
level. � t'- •• ...
, ;'
•
�- "
� •
•• ! { � :\ • I
.-

2. The node is associated with a trivial or a homogeneous vector. .:,., • i,· •. I ''
�o!
Tbe patb from the 1Eitial uncertain_ry t<?. a node in which the ve_ctor i{tri _
omogeneous efin� a homin� _seque�ce.
---A distinguishing tree is a successor tree in which a node becomes terminal i f
one of the following conditions occurs:
I . The node is associated with an uncertainty vector the ponhomogeneo�
components of which are associated with the same node at a preceding
ievel.
2. The node is associated with an uncertainty vector containing a homoge-
. . ---�-- ---- - ·····--- · ·--·- - -1
neous nontnv1al componenL
3. The node is associated with a trivial uncertainty vector.
The path from the initial uncertainty to a node associated with a trivial uncertainty
d�� a disti� gu�shiE_S�-�- ue��e. As an example, the horning sequence 0 1 0 is
-- _
obtained as shown in Fig. 4.6 by applying the tenninal rules to Machine N of
Fig. 4.5. The derivation of the distingwshing sequence 1 0 1 for Machine M of
Fig. 4.3 is shown in Fig. 4.7.
... ·-·-
During ,m e design of check�!_ ���-�- iL .i1i. gft�[l . Jl��� �o�-�ke the
_--::.;• ---· -- -....

machine in�� a pre�etermined state, after the homing s�g�e!1C£. .h� ��n apP.li,e�.
This is done with the help of a rransfer:.JW,e.nce, which is the shortest input
sequence that takes a machjne fro':i,''�ate S; to state Si . The pro�ed·�;�·-i; an

y· �
(ABCD) ---

Y �-
(AB}(D} (ABCD)

;.y �
(AB)(D) JJD)(C )

(A)(D} (D) . 4I .,'-

(BC)(A )

Figure 4.6 Homjng tre.e for Machine N

 •
4.2 State Table Verification 85

y
(A BCD)

(C)(D BC )

y y�
(C)(BC)( A ) A)(BC)
(B)(DBC)

(C)(C � )

y ��
(B)(BO) (C) (C)( BC) (D) (AD)(BC)

(B)(B)(CD) (C)(C) t(A)

Figure 4.7 Distinguishing tree for Machine M

adaptive one, because the transfer sequence is determined by the response of the
homing seq•Jence. As an example, let us derive the transfer sequence that will
take Machine M of Fig. 4.3 from state B to state C. To accomplish this, we ass ume
that the mac.bine 'is in state B. We fonn the transfer tree as shown in Fig. 4.8: it
can be seen from the successor tree that the shortest transfer sequence that will
take the machine from state B to state C is 00.
Instead of a homing sequ:�ce, a �?f,PJli;L�g �f'isuence may be use,d at !he
�Pinning of thecne� experimebt; �- !D�Shin� ti�Pe§Jiwnn&�tar�:)
regardless
.
of the output or the initial state of the machine. Some machines'posscss
•......, . -.:Z:::s.::..:.:r3:n_ ...£. ii.;&.!;:.z::e w)w,.aa-
synchronizing sequences -others do not. For a machine, one can construct a
synchronizing tree by associatin g wiLJ.?.��h n�� !!Jl�Q�e ru;din _ e ,
...fu!a! state� {re�J!!.:--- ---- ·---·-·-....
ss of tJ:ie output) that results from the application of the input
sx�122!§.- For example, if the initial.......... -----
u:ncertamty of Machine P of ig. 4.9(a) is
(ABCD), the 0-successor uncertainty is (ABC); it is not necessary to
write down
 86 4. Test C'.-eneration for Sequential Circuits

In put
Present state x= O x= I

A B. l c.o
B A ,0 D. I
C 8,0 A,O
D C, 1 A , 1
Next state. output
(a)

___.g--- �
(ABCD )

1/ '\
(ABC)

Y '\
;/ (ACD)

(AB) (A CD) (BC ) (AC)

1/ \
(AB) (CD) (AB)
o/ \ 3/ \ (A D ) (8) (AC)
(b)
Figure 4.9 (a) Machine P; (b) synchronizing tree for Machine P

·,, -"".,.r ....

,
the repeated entries(@ABC}. A node becomes terminal whenever either of the
fol lowing conditions occ�:
1 . The node is associated with an uncertainty that is also associ::J.ted with the
same node at a preceding level.
2. A node in the nth level is associated with an uncertainty containing just a
single element.
The synchronizing tree for Machine P of Fig. 4.9(a) is shown in Fig. 4. �(b).
A synchronizing sequence is described b>:_ � �h )�. .th:���!! 1��$ . fr.2 .!1}, ..! ��
initial uncertaint to a sin leton uncertaint . For Machine P, 1 1 0 is the synchro- •
...� ..,

nizing sequence that, when applied to the machine, synchronizes it to state B.

..,_ .. ..---- ,..__,..,. -. ,;-_ ·- ... .....,, � ' w 'j •..,. - -- - ""'

• �. �� . flJi .,,��

Designing Checking Experiments

Basic ally, the purpose of a checking experiment is to verify that the state table
of a finite state machine accurately describes the behavior of the machine. If
during the execution of the experiment the machine produces a response that is
different from the correctly operating machine, the machine is defini tely faulty.
 : )L..1 � \ I
11
•. • r 1I .f' l•
\ r
,
I , / 4. I t , , •. ,/J" /�
f..,,l · . ¥,I _, •
,· ,... j ✓•

,.. , (. 1 , •
( \
tf I
;.3 Test Generation 8a�ed on Circuit Structure 87

Such experiment,; can be used only to determine whether or not something is

wrong with a machine; it is not possible to conclude from these experiments what
is wrong with the machine.
We will now show how to design a checkin ex riment for any st:�!Y
connected, diagnosable sequential machine. A diqgnosable mac me the prop­
-�r.tY �Vi.!)g.it..ie.ait o;e disti�u�hi;;-g ;eqoence. Th�ecking exl)erim�nt c'an
-----.__,.._____.. --. . ...,,...
be divided into three phases:
1. j!;�i�{aJiJ.qtjan phase. Daring t�e initialization phase, the machine under
test is taken from an unknown ),!lltiaL state to a fixed state. A reduced,
strongly connected machine can be maneuvered into some fixed state s
by the following method:
(a) Apply a homing sequence to the machine and identify the current
state of the machine.
(b) If the current state is not s, al)ply a transfer sequence to move the
machine from the current state to s. -
It is apparent that the initial:ization phase is adaptive; however, it can be
·--
preset if�ac�ine has �i'mchrqnizin&,§�gue,ri�-
2. J!..a!e i�entiJz.cation ehase. During this. phase. an input sequence is al)plied
so as to cause the machine to visit each of its_ states and display its re­
sponse ··- -""-... ___
to the distin
-�
uishing
, sequence.
.�
3. Transition verification phase. Du ing this phase, the machine is made to
r

go
through every state transition; each state transition is checked by using
the distinguishing sequenc� .
.. � I -..��"•l"
�#-C► ......._ ;. ii!�

Although these three phases are distinct, in practice the subsequences for state
_identification and traI!_sjtio ve.!!&_£ati��are combined whenever possible, in order
to shorten the length of the experiment
The state table verification approach can be considered as a form of functional
testing. The maj.2! limitation of this technique is that it results in excessively long
tesf. ��_guences, and it is therefore o'nly ot theoretical interest However, the con­
cept of employing state tables for test generation and testability enhancement of
sequential circuits has been used in several recent techniques ( ee Sec . 4.5).

4.3 Test Generation Based on Circuit Structure

Several test generation techniques for sequential circuits have been proposed in
�cent years. In this section we will consider some of these�c hni ues that gen­

.
erate test sequences from the c ircuit structure. Agarwal er al. [4.3] have proposed
.._..._,__,,.,................,..----..-·......---, - ..,,,..,,.,.,... .._.,, ..__.
 8 4. Test Generation for equential ·rcuil

n�ra-
a simulation-based a Jroach called CO,\TTES'[� �q�cntial �ircuit Le t ge
• tion. It� s.es a concurrent fault simulator tha t al1ows it to generate te ts. for a group
;ffaulL:JAn initiitl1iatlon- �ecto� -bring the fault-free circuit to a known late
itderived first usina the fault simulator. For each input vector, a cost function
defined as the number of flip-Aops �tJ;t;.e in an unknown state is compute d. Thi
vector is modified til•, l the cost becomes zero. After the circuit has been initialized ,
an input vector is applied and its cost, defined a t he number of logic gates on
the path from the effect of a faul t to any primary output, is calculated. The input
vector is modified by the fault simulator till the effect of a fault reaches a primary
output, that is, until the cost of the input vector is zero. The input vector is then
included in the set of test vectors. For test generation of a single fault, the weighted
··s um of costs for two objectives-sensitization of the fault and the propagation
of the fault-is considered as the cost function. The cost of the first objective is
the dynamic controllabi lity measure computed from the current circuit slate de­
term ined by the simulator. The cost function for the second objective is the dy­
namic observability measure of the fault through all paths from the fault site to
the primary outputs. The minimizations of the first cost and the second cost lead
to the activation of the fault and subsequent selection of test vectors for detecting
the fault, respectively.
_Ghose er. qJ.:. 11:1L.��ve proposed a test generation technique based on the
co11cept'of path sensitization used in combinational circuit test generation algo­
rithms, for example, PODEM. This technique takes into account both the structure
and the state table of a sequential circuit. It is assumed that the circuit under test
has a resel srate. A test sequence is applied to the circuit with the reset state as
the starting state. The test generation process consists of the following steps:
1 . Generate a test vector for the assumed single stuck-at fault such that the
effect of the fault is propagated to the primary outputs or to the second­
ary outputs, that is, the outputs of the flip-flops. Each primary output as
well as each secondary output is considered an independent output of a
combinational circuit. A test vector for a fault is identified as an excita-
1ion vector, and the present state pan of an excitation vector is called the
e..xcitation stare.
2. Derive an input sequence to take the circuit from the reset state to the
excitation state; this input sequence is called the justification sequence.
Obviously, a justification sequence is not necessary if the excitation state
part of a test vector is the reset state. If the effect of a fault can be propa­
�ated to the primary outputs by the derived test vector, and rhe justifica­
tion sequence can take the faulty circuit from the reset to the exciLation
state, then the test vector is valid. However, if the test vector can propa-
 4..3 Test Generation Based on Circuit Structure 89

gate che effect of the fau lt only to the outputs of the flip-flops, that is. the
nex t ,tale is di fferent from the one ex pected, the following step is also
ncce�::rnry for :uccessful test generation for the assumed fau lt.
3. Derive an input sequence such that the last bit in the sequence produces a
d i ffe,c nt output for the fault-free and the fau 'lty states of the circu it unde r
test. uch an input sequence is called the diffin·entiating sequence.

A test sequence for the fault under test is obtained by coocacenating the jus­
tification sequence, the exc itation vector. and the di fferentiating sequence. This
test sequence is simulated in the presence of the fault to check i f the fault is
detected. If the fault is not detected, the di fferentiating sequence is not valid.
Also, a valid differentiating sequence cannot be obtained if the fault-free and the
fa u lty states are equivalent i n the fau lt-free sequential circuiL
Let us ill1 1slrate the technique by deri ving a test sequence for the fauJt a stock­
at-0 in the seq uential circuit shown in Fig. 4. l O(a); the state table of the fau lt­
free circuit is shown i n Pig. 4. 1 O(b).

i
\'
•I
Y,
•

x : O .r = I

A C, 1 8.0
B A.O D. l
C D,O B. l
D C, l A,O

X­
Y, r--i D Q
yr •V'.!
A 0 0
B 0
.r -•-- ,____
C I
Y2 -
D l 0
(a) (b)
Figu re 4• 10 (a) A ·equential circ uit; (b) the stnre
tabl e of the circuit
 90 4. Test Creneration for Sequential Ci rcuits

A partia l test vector for the fault is first derived:

X ,.
- 2

0 I

The value of Y2 has to be cho en such that the effect of the fault is propagated to
the primary output. If Y2 = 0, the fault i s neither propagated to the output nor
does it affect the next state. On the other hand, y 2 = I affects the next state
variable Y , . Therefore, the excitation vector for the fault is
X

0 1
and the excitation state is 1 1 (i.e., state C).
Next, we derive the justification sequence that can take the fault-free machine
from the reset state A to the excitation state C. It can be verified from the state
table that the justification sequence needs to contain a single bit only, which is
0. Thus, the test sequence derived so far consists of
0 0
and the corresponding fau lt-free output sequence and the next st.ates are

In the presence of lhe assumed stuck-at fault, the next state/output sequence is

Because the output sequence is the same as in the fault-free case, the fault is not
detectable. However, the final st.ate in the presence of the fault is A i nstead of
expected D; in other words, the effect of the fault a propagated on! y to the outputs
of the flip-flops. Therefore, a differentiating sequence that produc'.!S a different
output sequence for state A and state D has to be concatenated with che previously
derived test sequence. The differentiating sequence is deri ved as follows:
( DA )

(CC) (AB)

�
(A )(C) (B)(D)
...-

4.3 T t Generation Based on ircait Structure 91

Either 1 0 or 1 1 can be used as the di fferentiating equence. The choice of 1 1

results In the following test sequence for the assumed s uck-at fault in the circujt
of Pig. 4. 1 0(a):

0 0

The corresponding next Late/output equence for the fault-free circuit is

and for the faulty circuit

0 0 ,""' l ,. I .-
A � C ➔ A ·-+ 8 -4· D
l O !I O • 1

Thus, the fault is detected by the derived fst equence.

Kelsey el al. [4.5] have prol)O ed a. se-queocial circuit test eneration algorithm
c�at works strictly in forward time. tn other words, aU asstgn­
ments are m ade at primary inputs; any ssignment of te t value that requires
justification is avoided. 1t uses a nine-valued logic model, 0, 1, x, D, D. GO (good
zero), GJ (good one), FO {faulty zero)� and FI (faulty one). pro-po ed by Muth
[4.6]. The nine-valued model takes into ccount the repeated c cts o a fault
during the sequential circuit test generation process.
The input to FASTEST con ists of the description of the circuit under test, and
a fault list for which the test equence has to be derived. For ench f ult in the H ·t.
the excirarion time frame and the rota/ time frame are erive-cl by u ing an algo­
rithm called the initial time frame algorithm. The excitation time frame i the
minimum number of time frames needed to excite fault, and the minimum of
time frames needed to observe the fault i� the total time frame. Obviou 1y. the
total time frame cannot he maUer than the excitation time frame, becau�e this
might be the minimum number of time frames thac are nece sary to te ·t the fault.
The initial time frame algorithm fir t initializes the excitation time frame and
the total time frame to l . lf the selected fault i not excited in I.be current e, citation
time frame, the excitation time frame is incremented. This proces.s is continued
till the fault is excited, or the maximum number of ti.me frames is utilized without
success, io which case the fault is assumed to be untestable. Once the fault is
excited, the total time frame is set equal to the excitation rime frume. If the fault
i not observable at ome primary output, Lbe total time frame is incremented to
check whether the excited fault is observable. In case the fault is still not observ­
able, the total time frame is incremented till either the fault is observable or the
92 4. Test Generation for Sequential Circuits

maxi.mu � number of time frames has been u ed. If the total time frame reaches
the maximum time frame, a test is performed to detemline whether the excitation
time frame is equal to the maximum time frame. The fault is undetectable if the
test is successful. Otherwise, the excitation time frame is incremented and the
algorithm is continued.
O□ce the initial time frame algorithm provides FASTEST with the number of
excitation time frames for a fault and the total number of time frames. the test
generation algorithm determines an initial objective to excite the fault and prop­
agates it to an output The nine-valued logic model is used for this purpose. The
initial objective is GJ (GO) if the fault is stuck-at-0 (stuck-at- 1 ). The initial ob­
jective for propagating the faulty value depends on the gate type and the faulty
value. lf it is not possible to move the circuit to a state closer to detecting the
fault, the primary input value assigned last is complemented (assuming the com-
•
plemeot value has not been tried).
The test generation algorithm starts backtracing after an initial objective has
been determin ed. This is continued until a primary input or a flip-flop is reached
in the first time frame. The fault is untestable if a flip-flop is reached, because it
is not possible to assign value to a flip-flop in the first time frame. If a primary
inpul is reached during the backtrace process, it is assigned a value that is most
likely to satisfy lhe initial objecrjve. ext, the circuit is implicare.d, that is, the
effect of the given values of primary inputs on the internal lines of the circuit is
detem1ined. lf there is an inconsistency, ctifferent values are assigned to a set of
primary inputs, and tbe circuit is reimplicated and checked for inconsistencies.
The primary outputs assume a D or D if the reimplicated circuit is consistent;
otherwise, the rest generation process is restarted with a new initial objective.

4.4 Functional Fault Models

Test generation of �ential circuits based on th.e traditional stuck-at fault model
--�--� ..___ ·..

rs extremely complicated and time <:On�si�tl'l_g ��'!se the effect of a stuck-at

., ,,,... _,. _"-...._,,..,,............,
��--..
-· .... <: • - -
..._::.....-----

Tau t �1� �rop_a�!�� ��o the circuit 9�_tQ_Ut after ���l ti'?� Jr�i- Bymodeling­
·of faults at the state table, tl1at_2�.!he -- e c�-g��!�Uests _for _,.
�� �
�}t
a sequential circu.it before t11$,..cirs, i� �., , �- - �nt_ed .
:!E:
Cheng and J9u [4.7] have shownihat 'fesfsgenerated at the stateJfll>le ley..eJ
�!.
pro�u��e:,h ig�_.f�Q��i�_ &!uck-at f��}J� a! the g_at� �e��l. They have pro­
-posed -��--
a functional fault model, called the single transition fault model, to model
.....,.. - ' - ,,.,..... .,, ..,,.,,,,� - ,,
the faults in sequential circuits. In this model, any stuck-at fault in a circuit is
...
_ ,

.-- � .. -
assumed to result in an erroneous state transition. lo other words, a fault may
"
 4.4 Funct ional FauJt Models 93

A C.O 8,1
B C, I A,0
C AO B.O

Figure 4. 1 1 A . late !able

force the sequential ci � i_t ,!_�v�� P.!���s�te t9 a o_exJ s�t�!_h�r ,than

that specified in the state table of the circuit. To illastrate, let as consider the state
table sbo;n-rn Pig. 'f T1--:-An unplem eotalion of the state table assuming the state
assignment y ;y 2 = fB , 1 1 , and 00 for state A. B, and C, respecti vely, is shown
in Fig. 4. 1 2. Let us next assume that a is stuck-at-0 in Fig. 4. 12. The state table
corresponding to the faulty circuit is shown in Fig. 4. 1 3. As can be seen in the
state table , the destination states for present states A � C when input x = I
have changed (from expected.... - B to- A).- Note
- that there is no change in the output
value.
.,,,. �

The main problem with the single transition fault model is that the number
of faults to be considered in �te entia! circnit will be equal__!O n_ �
(n - 1 ) X 2\ where x is the number of inputs to the circuit. For example, the
�ber of· p'o'sill>Je'·single transition faults in the slate· table of Fig. 4. 1 3 is
•
1 2 ( = 3 X 2 x 2). ;c 1 "-

�omeranz and Reddy [4.8] have proposed a fault model tha� unlike the single
s�ate trnnsition m�consid:rs oajy_ �g£e tf!l!.le f�lf!..that result from ihe pres­
ence of stuck-at f�ults in the �w9:level implementation of the combinati� nal lo gic
part of,a sequentjal cifsH!!_. Thus, composite states of the form S 1 /S 2, where S 1
-�-· .... . . �-----i-• -..

and S 2 belong to the fault-free and the faulty machine, respectively. are consid­
ered. For example , the state table of a sequential circuit with state table fault

X D Y1 -
}'1
l ''

-
1.,

\
\
D Y2

\ 0 A \ l'

c� -...\
I
t,· (
Y2
i"!
C ""

Figure 4.12 An implementation of the state table of Fig. 4. 1 1

 4. Test Generation for SequcntiaJ Circuits
94

.r = O x = l

A C.O A.J
B C. J A ,0
C A,O 1to
Figure 4. 1 3 Faulty state table

A ! CID is shown in Fig. 4. 1 4 . This fault forces the circuit to move from state
---·---
A to state D instead o state C, when t he input x = 0.
- -- -- - - - � - -.. ,..._..,.__...
?,,.••-- -· - ��

'--Tfit number of faults under the state table fault model does not c xceed the
total number of stuc�-�t fau lts in the two-lev�l circuits. However, a multilevei
rather than a two-level combinational logic is more likely to be used in the actual
implementation of a sequential circuit. Some of the stick-at
. faults
,, � in the mul ti level
logic may not be covered by the state table faults deri ved from the two-level
implementation.

4.5 Test Generation Based on Functional Fault Models

Chen� and Jou [4.7] have proposed a test generation technique for sequential
circuiLS that considers a selected subset of,2:ll single transition faulls The selected
subset covers the remaining transition faults. The test procedure fu:st inj.rfalizes
ih-e -���nder test from a p;;;; state to an originating state for a faulty
Ifan siti_on . After the circuit moves into a wrong destination state, a state-group
differemiating (SGD) sequence is appl ied LO differential� between the expected
��and the faulty sta�. A reduced n-state sequential circui t has a col lection ·o f
�-:::...2._ SG D .s�uegces1 eac�� c���!i.Ei�l1�-��lt. aJ t�t.e ,t,.an �
o r state in the��':�tj the SGD sequences form_�_§CD �49#f¥Jf.!: set for state
_ ���

x=O x= l

A C/D.O 8,0
B o·.o C,O
C A,l D, l
D B,O A . I
Figure 4. 14 Sta.te table with fau l ty and fault-free transi tions
 4.5 Test Generation Based on
•
Functional Fault Models 95

--
A
B
8,0; C.0
C,O D, 1
C A.I 0, 1
D 8,0 A.I
Figure 4. 1 5 State table

J.:__ The state table shown in Fig. 4. 1 5 does no�ave a distii:igui shing sequence.
The input x = l can distinguish between states A and states B 9__,_aI}_d P, �c!.. !he
input x = 0 can distinguish between st�te A and state C. The SOD sequences
-��---
�(A , C) = ,0 and T(A_, {B, C, Dl) = l constitute a SGD eqaence set for state A.
Sirrularly, sequences T(B, C) = 0 and T(B. A) = l form the SOD sequence set
for state B; sequences T(C, {A, B. D' I ) = 0 and T(C, A ) = l form a SGD sequence
set for state C; and sequences T(D, C) = 0 and T(D, A) = l form a SGD sequence
set for state D.
Pomeranz and Reddy [4.8} have proposed an algorithm, based on state table
fault model, that generates a mmimal length test sequence for a fau lt in a se­
quential circuit. Both the fault-free and the faulty circuits arc used during the test
generation pr5>cess; it is assumed th�t both circuits can be initi alized tg lcoa!o
reset states, which may be dilierent Tests are generated by simultaneously trans­
ferring the fault-free and r.he faulty circuits from the reset state to a fault-detection
state. A composite state R 1/R 2 is a fault-detection state if different output e­
quences 'are obtained in response to an input sequence applied to the fault-free
-
circuit in state RI and the faulty __ -
circuit .-.,_
.... ___ in tate � 2. In other word� , the applied
input sequ� is a.dis.tmgJJisb.wg_ sesuence f�r ��s-R_L a�d R 1•
-

state
- P IP --
-·-------
A composite state Q i/Q 2 is considered tO be reachable from another compo .ite
--
if there ex.i t an mput sequence that can transfer the circuit from P ifP2
t'o Q ,/Q 2. The rearhability inde.:c of a composite state is assigned a value of l if
this is reachable at time i tarting from the initial composite state S0/S� at time
O; otherwise, the reachability index is 0. The reachability indices of all states in
a sequential circuit can be calculated u ing a procedure that. we illustrate using
th� sequenti{ll circuit of Fig. 4. 1 6(a). Let us as .ume that the initial state of each
of the fault-free circuit and the faulty c ircuit is A. At time i = 0, only the initial
state has a reachability index of l ; all other states have reachability indices of 0.
The next state entries for A corresponding to x = 0 and x = l are C/D and B,
re pectively. Therefore, ar time i = l the reachability index for CID is l , and that
 96 4. Tc. L Generation for cquen t ial ircu it!

\.
x= 0 x= I �� -
i B D CID A.ITJ DIA
A CID:-0 B,O
B JJ.O c.o 0 1 0 0 0 0 0 0
C A, I 12{A�� 0 J 0 0 1 0 0
D B.O A. I 2 0 0 I 0
(a) (b)

Figure 4. 1 6 (a) Sequential circuit; (b) reachability ind·ices for the equential circuit
in (a)

c)e
for B i also J . In other word . only states B and A/8 are reachable a t time i =
l ; all other states are unreachable. A l i = 2, states D and C can be reached from
state B, and states AIB and DIA can be reached from CID. . Thus, both A/B and
DIA have reachability indices of 1 i n Fig. 4. J 6(b). No_te t��t DIA is a fau lt detection
0
_
state. Therefore, i C is not necessary to derive additio'aaJ re�"chabi] ity indices. Any
siare,-;ot necessarily the reset state, can be used for con:ip_1;1_!in� reachability in­
dices. A lso, if no fault detection state is found while computing reachabi1Tty • -
inclic�s. tests can���edfor -the s�e table faults.
Once the reachability indices of a sequential ci rcuit have been derived, the test
sequence for the seq uential circuit is generated by setting the state of the circuit
to the fault detection stale R JR 1 that was reached at time I: :f,-n i �g�! ��ieg
,
such that the outpur response obtained when the circuit is at R I is different from
rhat obtained when the circuit is a!_ R2. Next, a predecessor state of R .IR 2 , for
example, Q ,IQ 2 , is identified at time unit r - I . The input value req uired co move
the circuit from Q i/Q 2 to R J IR 2._,is obtained from the state table. Predecessor
states and input values are derived in a similar manner till the time unit is 0. At
time unit o.,the reset stare is reach��-a;d-there-;t -;;�nc: gene����!1J?£��e�s is
_ #
completed.
, · - We iti'usriate the test sequence generation process for the state table fault

fdetectio
-+ Q/1 in Fig. 4. l 6(a). ll can be verified from 5ig.�_,4- J 6(� d�t DIAjs a fau!,t.-
n state; other faulr-deteccion states are AJC, AID, B/C, BID, CIA , CIB , CIP,
D/8� and D/C. Fjgure 4. I 6(b) indicates that at time unit i = 2 the index of the
_
fault detection sta_te D.IA is I . An input of 1 at state DIA produces different outputs
for the faulty and the fauh-free circuits. The only predecessor state of DIA having
an index I at time i = 1 is C/1):Therequired input to move from CID to Dt4 is
1 . The lone predecessor state of CJD havi ng an index J at time i = 1 is CID. The
required i nput to move from CID to DIA is 1 . The sole predece ssor state of CID
 4 �t G n ration Bas d on Functional Fault Models 97

having index I at 1im i = 0 i A : he input neces ary to move from A to CID is

0. Th refore, th min imum I n th of a Le t sequence i 3, and the sequence is
0 I' I
CID DIA --+ AIB
0 I 1/0

Nex t, le u, derive the te t sequence for the state Eble fault A ---') CID. From
Pig. 4. 1 1 ,(b) i t can be seen that CID is a,..fault detection sta1e with an mcle-x. I at
------ --- -
tiqle i = J . A n inpat of 0 di tingui he between the fault-fre�-��al� � ?11d the
fau l ty state D. The only predece or cate of CID at time i = 0 is A. Input 0
c h ange late A to CID. Th u s, the length of the test sequence needed to detect the
0
slate table fault A � CID i s 2: the equence is
0 0
A ---+ CID --+ AIB
110
As mentioned previoosly, this method for test equence generation is based
on the assumption that a ingle . :tuck-at fault i n a sequential cm:ui1 will marriiest
itself as d state table faulL It has been suggested in Ref. 4.8 that equivalent state
t;b"i·; fau!LS-for �ll -s-i nft1e ruck-at faults i n a sequential circuit can be extracted
from the_J!.s..eudo-implemrn1atia1t g1at is, two-level AND-OR implementation. of
the combinational logic part of the sequential circuit. Because in prnctice multi­
level logic is more L ikely to be used, realistic fault coverage can only be achieved
by deriving state table equivalent faults of the stuck-at faults in the multilevel
circuit. This state table fault derivation approach, although very simple in prin­
ciple, may r uire unacce tablr..bi --··
0h imulation
-·--- · - -� --time.
•- -
Sheu and Lee [4.9) have prol'_?sed a technique for synthesizing sequentiaJ
circuits that have built-in '1f!!Y
.. �h;c?@�� !_O detect single state transition faults.
A state tr!ln ition fault can only be detected by propagating its effect to the pri­
mary out 1mts. However, the effect of a fault cannot be detected at the outputs if
the circuit produces the ame output for the correct and the erroneous states and
then moves to the idemical next state . . f}� encodjn� fbe stares af a sequential
fi!cuit with a particula r pa1ity, it is possible to differentiate a correct state tran- -
• ition from an erroneou one. The state encoding proc�-ss ��nsist�-�f-the foUow i.ng
-
steps:
I . Cor,struct a diI!in s.uishing table from the tale table of the sequenti al
circ uir.
2. Compu te the tt!!!:!!.:stinguishabiliry value for each state pair in the di tin-
• •• • · ·· · -
gu i !:hing t ab l e. ---- • -
--
•

I
98 4. Test Generation for Sequential ircu its

3. Arrange the state pairs in the form of a fo,t with decreasing order of un­
distinguishable value: that u, a state pair with the largest undistinguisha­
bility value is placed at the head of the li t, followed by the pair with the
next highest undistinguishable value, and so on. 1
To ill ustrate the state encoding proces , let us consider the state table hown
in Fig. 4. 1 7. The associated distingui hable table is shown in Fig. 4. 1 8(a). A state
pair is indistinguishable if they produce the same ou uts_fp_r_ jJle same i9p_uts,
aJ tJ,o �_gh -�h�Y...�AY move_ LO 2ifferent next t�t�s. Each cell of the table corresponds
to a state pair defined by the intersection of tbe row and the 5olumn headings.
The distinguishability of a state pair is recorded by placing a X in the correspond­
ing cell. If a state pair _(p,q) is indistinguishable for an inpbt, the resulting next
state pair is entered in the cell (p,q ).
for the state table of Fig. 4. 1 7 , the state pair (A ,C) is totally distinguishable
because states A and C move to different states with different output:, for both
inputs. Also, state pairs (B,D) and (D,.£ ) are totally distinguishable. States B and
£ move to the same next state B with output O when the input is 1 , and they move
respectively to states C and D with output O when the input is 0. Thus, the state
pair (B,E) is partially equivale,u, and it may become equivalent if (CJ)) is equiv­
alent The entries in cell (B,£) are * and (C J)).
The undistioguishability of a state pair (p,q) can be computed from the distin­
guishable table, and it is
= number of next state pairs in cell (p,q)
+ number of (p,q) in the distinguishable table + xN,
where N is Lhe number of states in the sequential circuit with L outgoing edges,
and x ( 1 < x < L) is the number of transitions from (p,q) that result in the same
next st.ate and the same output for an input. For example, undistinguishabiJity of
(B.C) = I + 2 + 0 = 3, because there is one state pair i n cell (B ,C), and {B,C)
appears in cell (A .B) and cell (A ,£); there is no transition from (B,C) with the
same next state. The undistioguishability of (B,E) = 1 + 1 + 5 , because there

x=O x=l

A 8, 1 C,O
B D.0 B,O
C A,0 D, 1
D £. I B,1
E C,O 8,0

Figure 4. 1 7 A scare table

 4 T G neration Ba.'led on Fun •fional Fault Models 99

R BC B I

C X AD 0 3

" BE X BD D I 0 I

F, B C• D AC X £ I 7 I 0

A lJ C D o C D
(a) (b)
late Code Parity

I A 010 Odd
8 011 Even
C 1 Odd
D Even
£ Odd

.
(C)

Figure 4. 1 8 (a) Distinguishable e: ndislingui hable v lue. ; nd (c) parity n-

coding of stat

is one state pair in cell (8£). Also, (B.£) al)pears ooly in cell (A.D). x ,... I . nd
N = 5. The undistinguisb.ability values or all ate arc ho n in the table in
Fig. 4. l 8(b). From this table. an ordered list of tate pairs i o tained:

(8.£) B.C) .B) ,D) £) C.D) C.£).

The state pairs (B,£) and (B,C) occupy the first and the econd po ition in the
l ist because tbey ha e undistinguisbabiliry value of 7 and 3, re pectively� the re. l
of the state pairs ha e undi tingui hability value of l nd can be arranged in any
order. The tate pair (B.E) hould get signed to different parity first, followed
by pair (B,C), and o on. possible rate encoding for the circuit, with tares A,
C, and £ being a igned odd parity codes and r re B and D being signed even
parity code , is shown in Fig. 4. 1 8 ).
A . equential circuit in which the parity code are � igned as just di ussed
can be te ted for single tace transition faults by in orporaring a parity checker

I
a shown in Fig. 4. 1 9. An input equenee is derived that makes a equential circuit
- to go through all the states, starting from an initial siate. The parity bits resulting
from the application of thi input equence constitute the reference output se­
quence. A state transition fault will re ult in erroneous parity bits in the sequence,
and it will therefore be deLected.
 i rcuits
J OO 4. Te I Gen era lion for Seq uen t ial

0 u I pu l
lnpul

...
J Combinational
logic

A
Flip-flop!i ...

� Parity code

Figure 4.19 Parity-encoded sequential circuit

References

4. 1 Kohavi, Z. Switchinf? and Finite Automata Theory, Chap. 1 3, McGraw-Hi ll

( 1 970).
4.2 Hennie, F. C., Pi.uite State Modelsfor Logical Machines, Chap. 3, John Wiley
( 1 968).
4.3 Agrawal, V. D., K. T. Cheng, and P. Agrawal, "CONTEST: A concurrent
test generator for sequential circuits, " Proc. 25th Design Automation Con/,
84-89 ( 1 988).
4.4 Ghose, A., S. Devadas, and A. R. Newton, ' 'Test generation and verification
for highly sequential circuits," IEEE Trans. on CAD, 652-667 (May 1 99 1 ).
4.5 Kelsey, T., K. K . Saluja, and S. Y. Lee, "An efficient algorithm fgr sequential
test generarion,' ' IEEE Trans. Comput., 1 36 1 - 1 37 1 (November 1 993).
4.6 Muth, P., "A nine-valued circuit model for test generation," IEEE Trans.
CompUI., 630-636 (June 1 976).
4.7 Cheng, K. T., and J. Y. Jou, "Functional test generation for finite state ma­
chines,•· Proc. Intl. Test Co11f , 1 62- 1 68 (J 990).
4.8 Pomeranz, I . , and S. M. Reddy, "On achieving complete fault coverage for
sequentia.l machines," IEEE Trans. Comput., 378-385 (March 1 994 ).
4.9 Sheu, M.-L., and C. L. Lee, "Simplifying sequential circuit test generati on,"
IEEE Design and Test, 28-38 (Fall 1 994).
 1 43 2
C h a pter 5 Desi g n of Testable Sequential Circu its

l Several techniques for synthesizing testable combinatio nal circuits have been pro­
posed in recent years (see Chap. 3):. however, not much has been reponed on
synthesis techniques for testable sequential circuits. As discussed before. test
generation for sequential circuits is significantly moTe complex than that for com­
binational circuits. Many design guidelines have been proposed to improve the
testability of sequential circuits by adding extra test points; however, the e involve
nonsystematic (i.e., ad hoc) design modifications and depend heavily on a de­
signer's ingenuity. A well-established approach to solve testability problem for
sequential circuits is to constrain the design in a way that provides direct access
to the memory elements in a circuit This is known as the scan design method­
ology, and it is widely used in designing sequential circuits with enhanced test­
ability. ln this chapter, we will discuss some of the ad hoc design rules. evcral
variations of the scan methodology, and some other techniques for improving
•
sequential circuit testability.

�-1 Controllability and Observability

There are two key concepts in designing for resrability: controllabi/iry and ob­
servability. Controllability refers to the ability to apply test patterns to the inputs
of a subcircuit via the primary inputs of the circuit. For example, in Fig. 5. 1 (a)
i f the output of the equality checker circuit is always in the state of equal, it is
not possible to test whetber the equality checker is operating correctly or no1. If
a control gate is added 10 1he circuit (Fig. 5. 1 (b)). the input of the equaliry checker

IOI
 1 0� 5. Design of Testa ble Sequential Circuits

Equality checker
EquaJit checker

Logic
block
Logic
block l
(a) (b)

Figure 5 . 1 Control lability

and. hence, the operation of rbe ci:rcuil can be controlled. Therefore, to enhance
the controllability of a circuit, the state tbar cannot be controlled from its primary
inputs has to be reduced.
Observability refers to the ability to observe the response of a subcircuit via
the primary outputs of the circuil or ar some other output points. For example, in
Fig. 5.2 the outputs of aJJ three AND gates are connected to the inputs of the OR
gate. A stuck-at-0 fault at the output of the AND gate 3 is not detectable because
the effecr of the faulr is masked and cannot be observed at the primary output.
To enhance the observability. we m ust observe the output of th.e gate separately
as shown.
In general, the controllability/observability of a circuit can be enhanced by
incorporating some control gates and input lines (controllabi l ity), and by adding
some output fines (observabiJiry).

a b

C f

Figure 5.2 Observabi lity

1
 --------- .

S.2 A d Hoc Design Rules for Improving TestabiJity l 03

5.2 Ad Hoc Design Ru les for Im proving Testa bility

Ad hoc ru les are used to improve te.1 tabiliry of pecific cirC\Jits. One of the sim-.
plesl ways of achieving thic; i to incorpoT-ale additional control and observation
points in a circuit. For example, the faol a stuck-at- 1 in the circuit of Fig. S .3(a)
is undetectable at the circuit oulput. The addition of an extra output line in the
circuit makes the fault detectable (Fig. 5.3 b)).
The usefulness of inserting a control point can be understood from the circuit
• shown in Fig. 5 .4(a). The ou put of the OR ga e is always 0: therefore, it is not
possible to determfoe whether the gate i functioning correctly or not. If a control
point is added to the circmt as shown in Fig. 5.4{b). e OR gate can be easily
t ested for single stuck-at fau lt.
Another way of improving testabil ity is to insert multiplexers o increase the
number of intemaJ points that can be controlled or observed from the external
pins. For example, in the circuit of Fig. 5 .5(a) the faolt a stuck-at-0 is undetectab\.,;
at the primary output Z. By incorporating a multiplex.er as shown in Flg. 5.5(b),
input combination 0 1 0 cm be applied to detect the fault via the mulriplexer omput.
A different way of achieving access to internal points is to use tristate drive
as shown in Fig. 5.6. A test mode signal could be used o put e ·veT into he
high impedance state. lo this mode� the internal poim could be used as a control
point. When the driver is activated. the imemal point becomes t point .
Another approach to imp-rove testability is to permit access to a su' et of the
logic as shown in Fig. 5.7 [S. l .5.21. rtodule B is physi y embedded between
the two modules A and C. A set o ga es G and H i insened into ch of the
inputs and outputs, respectively, of module B. ln normal operation� rhe re t contTol
signal is such that modules A, B. and C are connected and the com-plete ne OL
performs its desired fu:ncrion. In the test mode, the r, t control input i changed�

a a
C C

a
f b f

b b
C C

(a) (b)

Figure 5.3 (a) Circuit with an und tectable fault� ) addition of an extra output line
 J 04 5. Design of Testable Sequential Circuit!

(1
I
C

0 d
r,
(a)

Control signal
a
j
Jl
b
l
a
ii
C t

1
f j
..

d t
( b)

Figure 5.4 (a) NOR gare nor 1esrable; (b) improvement in testability using a control
point

module B is connected to the pri mary inputs and outputs of the board. Jn this I
-1
I-f
mode, the control signal also causes the outputs of module C to assume a high
impedance state, and hence C does not interfere with the test results generated by
B. Basically, this approach is similar ro the previously di scussed technique of
using multiplexers to improve resrability.
The test mode signals required by the added hardware such as multiplexers.
tristate drivers, and so forth cannot always be applied via the edge pins, because
there may nor be enough of them. To overcome this problem, a "Lest state reg­
ister" may be incorporated in the design. This could in fact be a shift register
that is loaded and controJJed by just a few signals. The various testability hardware
in the circwt can -then be conrrolled by the parallel outputs of the shift register.
 5.2 Ad Hoc Design Rules for Improvin g Testabili ty

X2 2-to. \
Xi Mux
z SELECT

Test mode
control
Xi
,(3
(b)
(a)
Figure 5.5 (a) Circuit with fau lt; (b) use of multiplexer to enhance observ abil ity du r.
ing t�sting

Test mode signal

--► Control or observ ation point

Figure 5.6 Improvement in testability using tristate drivers

Board Module Module Module Board

input A B C ourput

Test control point

Figure 5.7 Testing of embedded modules (adapted from Ref. 5. l )
 J 06 5. Design of Testable Sequenlial Circuils

Flip-flop Flip-flop

RESET RESET

From tester

Figure S.8 Circuit initialization

Frequently, flip-flops, counter, shift registers. and other memory elements as­
sume unpredictable states when power is applied, and they must be set to known
states before testing can begin. Ideally. aJI memory element-; should be reset from
rhe external pins of the circuit, whereas in some cases additional logic may be
required (Fig. 5.8). With complex circui ts it may be desirable to set memory
elements in several known stares. This not only allows independent i nitialization,
it also simplifies generation of certain inlemal states required to cest the board
adequalely.
A Jong counter chain presents another practical tesr problem. For example, the
counter chain shown in Fig. 5.9 requires thousands of clock pulses to go through
all the states. One way to avoid this problem is to break up the long chain into
smaller ones by using a multiplexer. When the control input c of the m ultiplexer
is ac logic 0, the counter functions normally. When c is at logic 1 , the original
counter is partitioned into two smaller counters.
A feedback loop is difficult LO test, because it hides the source of a fau lt. The
source can be located by breaking the loop physically and bringing both lines to
external pins that can be short-circuited for nonnal operation . When not short-

c 4 bit 4 bit : 4 bit

c 4 bit c <
counter count.er counter cou nter

Clock

Figure 5.9 Use of a mul tiplexer to simpl ify testing of long counter chains
 •

S.J Design of Diagnosable Seq1H!l1tial Crtcuit� 1 07

ExtemaJ control

Logic Logic

Figure S. 1 0 Breaking of feedback loop using on e�tra gate

circuited, the separated lines provide a control point and a test point. An alter­
native way of breaking a feedback loop. rather than using more costly test/control
points, is to add to the feedback path a gate that can be interrupted by a signal
from the tester (Fig. 5. 1 0).

5.3 Design of Diagnosable Sequential Circuits

The use of checking experiments to detennine whether a sequential circuit rep­

resents the behavior specified by its state table yields good results provided that

I . The circuit is reduced and srrongly connected.

2. The circuit has a distinguishing sequence.
3. The actual circuit has oo more 51ates than the correctly operating circuit.
For circuits that do not have any distinguisb:ing sequences, the checki:ng expe�
ments are very long and consequently hard to apply in any practical siruarion.
One approach to this problem is to modify a given circuit by adding ex.tra outputs
so that the modified circuit has a distinguishing sequence. A sequential circuit
which possesses one or more distinguishing sequences is said to be diagnosable.
A procedure for modifying a sequentiaJ circuit to possess a distinguishjng
sequence if it does not already do so has been presented by Kohavi and Lavelle
(5.3]. Let us explain the procedure by considering the state table of Circuit M
shown in Fig. 5 . 1 1 (a); Circuit M does not have a distinguishing sequence. The
procedure begins with the construction of the testing table of the circui� the
testing table for Circuit M is shown in Fi. g . 5. 1 1 (b). The column headings consist
of all input/output combinations, where the pair X/Z corresponds to input X and
output Z. The entries of the table are the • ' next state." For example, from state
A under input I the circuit goes to state B with an output of 0. This is denoted
 1 08 5. Design of Tc table � eq ucntial ircuiu

Pr ·enl stale 0/0 0/ 1 1 /0 J/J

A A B
8 A
C A D
D - A A
Ne�'t state/out pu t
Present state .r = 0 x = 1
AB
AC
@ --BC -
BD -
A A,O B.O AD - AB -
8 A .0 c.o BC - CD -
C A,I D,O BD - AC -
D A,I A .0 CD - @ AD -
(a) (b)
Figure 5. 1 1 (a) State table of Circuit M; (b) tesLing table for Circuit M

by entering B in column 1 /0 and a dash (-) in column 1/1 . In a similar manner,

the next st�tes of A are entered in the upper half of the table.
The lower balf of the table is derived in a straightforward manner from the
upper half. lf the entries in rows Si and Sj , column X,JZ 1 of the upper half are S,,
and Sq respectively, the entry in row SiSj, column X,JZ 1 , of the lower half, is
S1,S,r For example, because the entries in rows A and B, column 1/0, B and C,
respectively, the corresponding entry in row AB, column 1/0, is BC and so on.
If for a pair S, and S1 either one or both corresponding entries in some column
Xt lZ , are dashes. the corresponding entry in row S;S1, column Xk !Z i , is a dash.
For exampJe, the entry in row BD, col umn 0/0, is a dash, becau� the entry in
row D, column 0/0, is a dash. Whenever an entry in tb_e testing table consists of
a repeated state (e.g., AA in row AB), that entry is circled. A circle around AA
implies u-1'.r both states A and B are merged under input O into stale A and hence
are indistinguishable by any experiment starting with an input 0.
The next step of the procedure is 10 foJTD the testing graph of the circuit. The
testing graph is a directed graph with each node corresponding to a row in the
lower half of the resting table. A directed edge labeled X 1,/Z I is drawn from node
S,S1 to node SpSq , where p ::/= q, if there exists an entry in row S;S1 , column
XJ Z 1 of the testing table. Figure 5. 1 2 shows the testing graph for Circuit M.
A circuit is definitely diagnosable if and onJy if its testing graph has no loop
and tbere are no repeated st.ates, that is, oo circled entries in its testing table.
Circuit M is therefore not definitely diagnosable, because AA exists in its testing
rabJe and its testing graph contains tow loops: AB-BC-CD-AD-AB and AC-BD-
 s.J Design or Diagnosable Sequential C ircui ts l O'J

Figure 5. 1 2 ·resting gtaph fo r Circuit M

AC. To make the circuit definitely diagnosable. additional output variables are
req uired to eliminate aJI repeated entries from its testing table and to open all
loops in its testing graph. The maximum number of extra output terminals re­
quired to make a 2t stare circuit definitely diagnosable is k; however, tbe addition
of one output terminal is sufficient to make Circuit M definitely diagnosa ble. The
modified state table of Circuit M is shown in Fig. 5 . 1 3; this version possesses the
dis • 1guishing sequences O and 1 1 . The checking experiment for a de fin itely di­
agnosable circuit can be derived as follows:
I . Apply a homing sequence, followed by a transfer sequence (S;, S0) is
necessary, to bring the circuit into an initial state S0.
? Choose a distinguishing sequence so that it is the shorter one of the se­
quences of all Os or all I s. (For the purpose of clearer presentation of the
procedure, assume that the distinguishing sequence has been chosen as
1he all- I s sequence.)
3. Apply the distinguishing sequence foll'owed by a 1 . (If the all-Os e­
quence has been chose� apply a O instead of a 1 .)
4. If S 0 1 • that is, the I -successor of S 0, is different from S 0, apply another !
to check the transition from S 0 1 under a l input. Similarly, if s 0 1 1 � S0,
and So, , * So, apply another 1 . Continue to apply 1 inputs in the ame
manner as long as new transi tions are checked.

Next state/out put Z,Z:

Present state X=O X= 1
A A ,00 8,0 1
B A,01 C,00
C A,10 D,00
D A. I I A,0 1
l''igure 5. 13 Cfrc uil M with additional outp ut Z2
 1 JO 5. Design of Testable Sequential Circuits

5 . When an additional 1 input does not yield any nev,, transition, apply an
input of O followed by the distinguishing sequence.
6. Apply inputs of 1 s as long as new transitions can be checked. Repeat
steps 5 and 6 when no new transiti ons can be checked.
7 . When steps 5 and 6 do not yield any new transiti ons and the circuit,
which is in state S;, is not yet completely checked, apply the transfer se­
quence T(S;, S1.), where S1,: is a state the transition of which has not been
checked, such that T(S;, S,.J passes through checked transitions only.
8. Repeat the last three steps until all transition have been checked.
The checking experiment for the definitely diagnosable circuit of Fig. 5 . 1 3 has
been designed using the foregoi ng procedure. I t required only 23 symbols and is
illustrated here:
Input l 1 1 1 0 I l O 1 1 l l l 1 1 0 1 1 0 0 I 1
State A B C D A B A B C A B C D A B C D A 8 C A A 8 C
Outpu t Z 1 0 0 0 0 0 0 0 0 I O O O O O O O 1 0 0 J O O 0
Z2 I O O 1 1 1 1 0 0 1 0 0 1 1 0 0 I I O O O 1 0
For an n-state, m-input circuit, this procedure gives a bound on the length of
checking sequences: approximately mn3 .

5.4 The Scan-Path Technique for

Testable Sequential Circuit Design

The testing of sequential circuits is complicated because of the difficulties in

setting and checking the states of the memory elements. These problems can be
overcome by modifying the design of a general sequential circuit so that it wilJ
have the following two properties [5.4]:
I . The circuit can easily be set to any desired internal state.
2. It is easy to find a sequence of input patterns s uch that the resulting out­
put sequence will i ndicate the internal state of the circuit. In other words:
the circuit has a distinguishing sequence.

The basic idea is to add an extra input c to the memory excitation logic in order
10 conrrol the mode of a circuit. When c = 0, the circuit operates in its nonnal
mode, but when c = 1 , the circuit enters into a mode in which the elements are
connected together to form a shift register. Thi s facility is incorporated by in­
serting a double-throw switch in each input lead of every memory element. A l l
 5.4 'l'he 'can-Path Technique for Te table Sequential Circuit Design 111

Y,
D Q t-+--t-------4 z
Q �----1-
-------'-'

.x D Q i----+-+--......

__Q ----
_,

Clock
Figure 5.14 A sequential circuit

these switches are grouped together, and the circuit can operate either in its normal
mode or shift register mode. Figure 5.14 shows a sequential circuit using
D flip-flops; the circuit is modified as shown in ng. 5 . 1 5 . Each of the double­
throw switches may be realized as indicated in Fig. 5 . 1 6. One additional input

Scan-in input C

Q l-+--+------1

Q i--...--+--.
'-----"'-'

X D Q �._+-+---------P
Scan-out output
,______,Q 1-4--

Clock

Figure 5. 15 Modified sequential circuit

 1 1. 2 5. Design of Testable Sequential Circuits

A
Ac + cb

B
Figure 5.16 A realization for the double-throw switch

connection to the modified circuit is req uired to supply the signal c lo control all
the switches.
In the shift register mode, the first flip-flop can be set directly from the primary
inputs (scan-in inputs) and the output of the last flip-flop can be directly monitored
on the primary output (scan -oul output). This means that the circuit can be set to
any desired state via the scan-in inputs, and that the internal state can be deter­
mined via the scan-out output. The procedure for testing the circuit is as follows:
I . Set c = I to switch the circuit to shift register mode.
2. Check operation as a shift register by using scan-in inputs, scan-out out-
put, and the clock.
3. Set the initial state of the shift register.
4. Set c = 0 to return to normal mode.
5. Apply test input pauem to the combinational logic.
6. Sec c = 1 to return ro shift register mode.
7. Shifr our the final state while setting the starting state for the next test.
8. Go to step 4.
With this procedure a considerable proportion of the actual testing time is spent
in setting the stare, an operation rJ1ar requires a number of clock pulses equal t?
the length of the shift register. This time may be decreased by fanning several I
short shift registers rather than a single long one; the time needed to set or read
the state would then be equal to the length of the longest shift register. The extent
to which the number of shift registers can be increased is determined by the
number of input and output connecLions available to be used to drive and sense
1he shift registers.
The main advancage of the scan-path approach is that a sequential circuit can
be transformed into a combinational circuit, thus making test generation for rhe
circuit relatively easy. Besides, very few extra gates or pins are required for this
transformation.
Another implementation of the scan-path technique has been described by
Funatsu et al. [5.5). The basic memory element used in this approach is known
 5.4 The Scan - Path Tech n ique ror Testable Sequential Circui t Design
I 13

as a rocelc.u D-type flip-flop with scan path [5.6] Figure 5. l 7(a) s how s such a
memory element, which consists of two latches ll and L2 . The two clock si gna1 s
•
C / and C2 operate exclusively. Ounng norma I operation, • C2 remains at log
jc 1
and c / is set to logic 0 for sufficient time to latch up the data at the dat� inp
ut
D I . The output of Ll is latched into L2 when Cl returns to logic 1 .
Scan-in operation is real i zed by clocking the test input value at D2 into the
latch LI by setting C2 ro logic 0. The output of the LI latch is cloc ked into L2
when C2 returns to logic I .
The configuration of the scan-path approach used at logic card level is shown
i n Fig. 5. l 7(b). A ll rhe flip-flops on a logic card are connected as a shift register,
such that for each card there is one scan path. In addition, there is provision for
selecting a specified card i n a subsystem with many cards by X-Y address signals
(Fig. 5. 1 7(b)). J f a card is not selected, its output is blocked; thus. a number oi
card outputs in a subsystem can be put together with only a particular card havinQ
control of the test output for that subsystem. The Nippon Electric Company ir
Japan has adopted this version of the scan path approac·h to improve the testabiliL·
<Jf their FLT-700 processor system.

c2 -----------.
D2 --+--,
Scan-in
D I ---+--1
Output
r-1...;'-�- Scun-ou t

CJ
L2
(a)
•
X
y Scan-out
Scan-in
Ff l FF2 FFn
C2 C2 C2

C2
(b)
Figure 5.17 (a) Raceless fl ip-flop with sca n path; (b) configurati on of logic card
(adapted from Ref. 5.5)
l I4 5. Design of Testable Sequential Circuits

5.5 Level-Sensitive Scan Design (LSSD)

One of the best known and the most widely practiced methods for synthesizing
testable sequential circuits is the IBM LSSD (level-sensitive scan design) [5.7-
5.l O] . The level-sensitive aspect of the method means that a sequential network
is designed so that the steady-state response to any input st.ate change is inde­
pendent of the component and wire delays within the network. AJso, if an input
state change involves the changing of more than one input signal. the response
must be independent of the order in which they change. These conditions are
ensured by the enforcement of certain design rules, particularly pertaining to the
clocks that evoke state changes in the network. Scan refers to the abil ity to shift
into or out of any st.ate of the network..

5.5.J CWCKED HAZARD-FREE LATCHES

In LSSD, all internal storage is implemented in hazard-free polarity-hold latches.

The polarity-bold latch has two input signals as shown in Fig. 5 . 1 8(a). The latch
cannot change state if C = 0. If C is set to I , the internal state of the lc:tch takes
the alue of the excitation input D. A flow table for this sequential network, along
with an excitation table and a logic implementation, is shown in Fig. 5. 1 8 .

CD
00 0 1 1 1 10 L
A A B A 0
Data (D) ---r;-L_ State ffl
Clock (C) � - L
B B B B A 1

(a) { b)

00 0 1 11 10 L L
CD

:v o � o
l � l

(c) ( d)

Fiourc 5.1 8 Hazard:free polarity-bold latch: (a) symbolic representation; (b) 1low
t.able; (c) excitation table; (d) logic implementation (from E. B. Eichel­
berger and T. W. Williams, "A logic design structUTC for l..Sl Les :abil­
ity," Proc. 14th Design Automation Conf., June 1978. Copyright 0 1978
IEEE. Reprinted with permission).
 5.5 Level-Sensitivt Saa Design (LSSD) I 15

Data (D)
System clock (C)
Scan-in (/) LI +Li
Scan clock A

.....
L2 - +l2
Scan clock 8 --------1

Figure 5.19 Polarity-hold shjft register latch (from E. B. Eichelberger and T. W. Wil­
liams, "A logic design structure for LSI testability." Proc. 1 4th Design
Automation Conf.., June 1 978. Copyright 0 1978 IEEE. Reprinted with
perm ission).

The clock signal C will nonnally occur (change from O to J ) after the data
signal D has become stable at either a 1 or a 0. The output of the latch is set to
the new value of the data signal at the time the clock signal occurs. The correct
changing of the latch does not depend on the rise or fall time of the clock signal.
only on the clock signal being l for a period equal to or greater than the time
required for the data signal to propagate through the latch and stabilize.
A shift register latch (SRL) can be formed by adding a clocked input to the
polarity-hold latch LI and including a second latch 1.2 to act as intermediate
storage during shifting (Fig. 5.19). As long as the clock signals A � B are both
0, the LI latch operates exactly like a polarity-hold latch. Terminal / is the scan­
-in input for the shift register latch and +U is the output. The logic impfernen�
tation of the SRL is shown in Fig. 5.20. 'When the latch is operating as a shift

Da� (D) ---�

Scan clock A ____,

Scan clock 8 ------------
Figure 5.10 Logic for the shift-register lntch (from E. B. Eichelberger and T. , • Wil­
liams, "A logic design structure for LSI tcsmbiliry," Proc. 14th Design
Automation Conf.. June I 978. Copyright 0 1 978 IEEE. Reprinted with
permission}.
 J 16 5. D ·i1•11 of T ta ble , cqutntiul ircuit.

I I B +U I A B +l2

I
B +U.

I
I I I J
IL A
•
_fl_ B
+l.2 ,:;

Figure S.21 Linka,ge of e,reral Ru (from E. B. Eichelberger and T. \ •. Wil liam ,

• A lo�c d ign ·truclure for LST resr:ibilit , . . Proc. 1 4th o, ign Auto­
mation Conf.. June 1 97 . Copyright © 1 97 IEEE. Reprinted wiLh per­
mission ).

regisrer, data from the preceding ·tage are gated into the polarity-hold switch v ia
/, through a change of the clock A from O to 1 . After A has changed back to 0.
clock B gates the data ia· the latch LI into the output latch l2 Clearly, A and B
can never both be I at the same time if the shift register latch is to operare
properly.
The SRLs can be interconnected to form a shift register as shown in Fig. 5.2 1 . o
The input / and the output +L2 are trung together in a loop, and the clocks A
and B are connecLed in parallel.

5S.2 LSSD DESIG RULES

A pecific er of design rules has been defined to provide level-sensitive logic
subsystem with a scannable design that would aid testing [5.8].

Rule 1 All inLemaJ storage is implemented in hazard-free polarity-hold latches.

Rule 2 The larches are control led by two or more nonoverlapping clocks such
that

(a) Two latches. where one feed. the other, cannot have the same clock (see
Fig. 5.22(a)).

ID Q D Q ---
X y
-C � C C C
Clock (CJ CJock (C,,)
Clock (A) -+-------1
,..._________J"-
(violation) Violarion
(aJ (b)
Figure 5.22 (a) Checking Rule 2(a); lbJ checking Rule 2(b)
 S.5 Level•Sensitive Scan Design (LSSD) 1 17

Clock
input
RL OK here SRL

X.
Clock
Clock 2
OFF = 0 � .input
Cannot tum off SRL
clock (v iolatioo)
(a)

Clock
i nput
SRL OK here SRL

Clock
Clock 2 ------�
OFF = 0 input
Violates Rule 3(c) SRL

(b)

Figure 5.23 (a) Clock OFF tesL (b) clock Or test (from Funatsu. et al .. "Test gener­
ation sy terns in Japan:· Proc. 1 2th Design Automation Conf.. 1975.
Copyright 0 1 97 IEEE. Reprinted with permission).

(b) A latch X may gate a clock C, to produce a gated clock C;s, which
drives another latch Y if and only if clock Ci 1: does not clock latch X,
where C,, is any clock deri ed from C; (see Fig. 5.22(b)).

Rule 3 It must be possible to identify a set of clock primary inputs from which
the clock input to SRL are controlled either through simple powering trees or
through logic that is gated by SRLs and/or nonclock primary inputs (see
Fig. 5.23). Given this tructure, the following rules must hold:
(a) AJI clock inputs to all SRL mu t be ac their OFF states when all clock
pri mary inputs are b.e ld to their OFF states (see Fig. 5 .23(a)).
(b) The clock signal that appears at any clock input of any SRL must be
controJlable from one or more c lock primary inputs. such that it is possi­
ble to set the clock inpul of the SRL to an ON state by turning any one
 1 18 5. Design of Testable Sequential Circuits

of the corresponding dock primary inputs to its ON state and also set­
ting the required gating condition from SRLs and/or nonclock primary
inputs.
(c) No clock can be ANDed with either the true value or the complement
value of another clock (see Fig. 5.23(b)).

Rule 4 Clock primary inputs may not feed the data inputs to latches either
di rectly or through combinational logic, but they may only feed the clock input
to the latches or the primary outputs.
A sequential logic network designed in accordance with Rules 1 -4 would be
level-sensirive . To simplify testing and minimize the primary inputs and output�.
it must also be possible to shi ft data into and out of the latches in the system.
Therefore, two more rules must be observed:

Rule 5 All SRLs must be interconnected into one or more shift registers, each
of which has an input, an output, and clocks available at the terminals of the
module.

Rule 6 There must exist some primary input sensitizing condition (referred to
as the scan state) such that
•
(a) Each SRL or scan-out primary output is a function of only the preceding
SRL or scan-in primary input in its shift register during the shifting op­
eration.
(b) All clocks except the shift docks are held OFF at rhe SRL inputs.
(c) Any shift clock to an SRL may be turned ON and OFF by changing the
corresponding clock primary input for each clock.
A sequential logic network that is level-sensitive and also has the scan
capability as per R ules I to 6 is called a level-sensitive scan design (LSSD).
Figure 5.24(a) depicts a general structure for an LSSD system in which all system
outputs are taken from the L2 latch; hence, it is called a double-latch design.
In the double-latch connguration, each SRL operates in a master-slave mode .
Data transfer occurs under system clock and scan clock B during normal opera­
tion, and under scan clock A and scan clock B during scan-path operation. Both
latches are therefore required -during system operation. In the single-latch con­
figuration, the combinational logic is partitioned into two disjoint sets, Comb I
and Comb2 (Fig. 5 .24(b)). The system clocks used for SRLs in CombJ and
Comb2 are denoted by Clock I and Clock2, respectively; they are oonoverlapping.
The outputs of the SRLs in Comb I are fed back as secondary variablr- inputs to
Comb2, and vice versa. This configuration uses the outpur of latch lJ as the
 y

Combinational
Input �
logic

System clock
Scan cloclc A
Scan-in ---
Scan clock B ------�
(a)

Output (l)

Scan-out
Input ( I ) Comb!

Y( I )

Clock .I

1
Output (2)

Y(2)
Input (�) Comb2

Clock 2
Scan clock A
Scunrin ___.
Scan clock 8 -------'
(b)
Figure 5.24 (a) Doble-latch LSSD; (b) single-latch LSSD (adapted from Ref. 5.7)
 1 20 S. Design of Testable Sequential Circuits

System dota (DJ )

System clock (C / ) Lntch -
Scan-in (/) L1
Scan clock A
-
Scan clock B ______, Latch
System data (D2) U*
� u ·�
System clock (C2) ---�--'
(a)

b---+-----------P LJ

o---..-• l2*

(b)
Figure 5.25 (a) LI /L2* SRL; (b) implementation of Ll /I.2* SRL using NA.ND gar.es
(adapted from Ref. 5.9)

system output; the U latch is used only for shifting. In other words, the L2 latches
are redundant and represent an overhead for testability. However, the basic SRL
design can be modified to reduce the overhead. The modified latch called the
LI/l2* SRL is shown in Fig. 5.25. The main difference between the basic SRL
aad the Ll /l2* SRL is chat l2* has an alternative system data input D2 clocked
in by a separate system clock C2. The original data input D in Fig. 5 . 1 9 is also
available and is now identified as DJ in Fig. 5.25. DJ is clocked in by the original
system clock, which is now called CJ . Clock signals CI and C2 are nonoverlap­
ping. The single-latch configuration of Fig. 5.25(b) can now be modified to the
configura1i�n of Fig. 5.26, in which the system output can be taken from either
the LI output or the L2* output. In other words, both LI and l2* are utilized,
which means fewer latches are required in the system. As a result, there is a
significant reduction in the sil icon cost when Ll /L2. * SRLs are used to implement
the LSSD. Although both latches in Li /l.2 "' SRLs can be used for system func­
tions, ir is absolutely essential, as in conventional LSSD, that both LI and L2*
outputs do not feed the same combinational logic.
 5.5 Level•Seositive Sc.an Design (LSSD) 121

L:::)
.
� - )Outpur ( I )
,--.

LI
lnpul { I ) ⇒ Comh l ...-
Y(2)
•

...-
,-...--
lf
1�
II
Y( l )
Clock l -

Scan- In
Scan clock A -
II
,,_,._,
� '
• .,)Output (2)

12• ...-
⇒
Scan-
Input (2) Comb2 out
-
r=.?
. -- l2*

Clock 2
Scan clock B

Figure 5.26 Single-latch LSSD des·ign using SRL Li/U* (adapted from Ref. 5.9)

5.5.3 ADVANTAGES OF THE LSSD TECHNIQUE

The LSSD approach is very s-imilar to the scan-path approach used by the NEC,
except that ii has the level-sensitive attribute and requires two separate clocks to
operate latches LI and L2. The use of LSSD alleviates the testing problems in
the following ways:
I . The correct operation of the logic network is independent of a.c. charac•
teri tics such as clock edge rise time and fall time.
2. Network is combinational in nature as far as test generation and testing is
concerned.
3 . The elimination of al l hazards and races greatly simplifies both test gen•
eration and fault simulation.
1 22 5. Design of Testable Sequentinl Circuits

The ability to test networks as combinational logic is one of the most important
benefits of the LSSD. This is done by operacing the polarity-hold latches as SRLs
during testing.
Any desired pattern of l s and Os can be shifted into the polarity-hold latches
as inputs ro the combinational network. For example. the combinational network
of Fig. 5.24(a) is tested by shifting part of each required pattern into the SRLs,
with the remainder applied through the primary inputs. Then the system clock is
rurned on for one cycle, the test pattern is propagated through the cc mbinational
logic, and the result of the test is captured in the register and at the primary
outputs. The result of the test captured in the register is then scanned out and
compared with the expected response. The shift register must also be tested, and
this is accomplished by shifting a short sequence of 1 s and Os through the shift
register l atches.
In general, most functions designed in an unconstrained environment can be
designed using the LSSD approach with little or no impact on performance. How­
ever, the requirement of level-sensitive flip-flops demand custom-designed chips:
hence. the LSSD approach would be difficult to apply to a board- level circuit
bui1r using off-the-shelf JCs.

5.6 Random Access Scan Technique

The design methods discussed in Secs. 5.4 and 5.5 use sequential access scan-in/
scan-out techniques to improve testability; that is, all flip-flops are connected in
series during testing to form a shift register or registers. In an alternative approach,
known as random access scan , each flip-flop in a logic n.etwor� is selected in­
dividually by an address for control and observation of its state [5. 1 1 ]. The basic
memory element in a random access scan-in/scan�:mt network is an addressable
larch. The circuit diagram of an addressable latch i� shown i n Fig. 5 .27 . A latch
is selecled by X-Y address signals, the state of which can then be controlled and
observed through scan-in/scan-out lines. When a latch is selected. and its scan
clock goes from O to 1 , the scan data input is transferred through the network to
the scan data . outpu.t, where the inverted valu.e of the scan data can be observed.
The input on the DATA line is trdllsferred to the latch output Q during the neg­
ative transition ( I to 0) of the clock. The scan data out lines from all latches are
ANDed together to produce the chip scan-out signal; the scan-out line of a latch
remains at logic I unless the latch is selected by the X-Y signals.
A different type of addressable latch-the set/reset rype-is shown in
Fig. 5 .28. The ' 'clear" signal clears the latch during its negative transition. Prior
 5.6 Random Acce.�s Scan Technique 1 23

Dllla -------1

can data in -----i

---
o---- Scan data. out
X -+-+----'
y -_..--'--------'
Figure 5.27 An addressable latch (from H. Ando. • 'Testing of VLSl with random ac­
cess scan," Proc. COMPCON Spring 1 980. Copyri ght @ 1 980 IEEE.
Reprinted with permission).

to scan-in operation, aD latches are cleared. Then. a larch is addressed by the X-Y
lines and the preset signal is applied to set the latch state.
The basic model of a sequential circuit with random access scan-in/scan-out
network is shown in Fig. 5.29·. The X- and Y-address decoders are used to access
an addressable latch-like a ce11 in random access memory. A tree of AND gates
is used to combine all scan-out signals. Clear input of all latches are tied together
to form a master reset signal. Preset inputs of all larches receive the same scan­
in signal gated by the scan clock; however, only the latch accessed by the X-Y
addresses is affected.

Data -----t

D--- Scan-out

X--+-+-----------'
y --+-----------------'
Figure 5.28 Set/reset lype a<ldressuble latch (fTQm H. Ando, "Testing of VLSI with
random access scan," Proc. COMPCOM Spring 1980. Copyright � 1980
lEEE. Reprinted with permission).
 1 24 S. Design of Test able Sequen tial 'ircuits

Input ⇒ Combinational
circuit
Ourput
Scan data in

Clear and Clock �

Scan clock Presel
Addressable
memory clements
t--_,
can addres. Y-Decoder

X-Decoder

Figure 5.29 Sequential circuit designed with addressable latches (from H. Ando,
' 'Testing of VLSI with random access scan, ' ' Proc. COMPCON Spring
1 980. Copyright © 1980 IBEE. Reprinted with permission).

The test procedure of a network with random access scan-in/scan-out network

is as follows:
I . Set test input to all rest points.
2. Apply the master reset signal to initial ize all memory elements.
3. Set scan-in address and data. and then apply th.e scan clock.
4. Repeat step 3 until all internal Lest inputs are scanned in.
5. Clock once for normal operation.
6. Check states of the output points.
7. Read the scan-out states of all memory elements by applying appropriate
X-Y signals.
The rand.om access scan-in/scan-out technique has several advantages:
1 . The observability and controllability of all system latches are allowed.
2. Any point in a combinational network can be observed with one addi­
tional gate and one address per observation point.
 5.7 Partial Scan 1 25

tested through a scan -in/scan-

3. A mem ory array 1· n ",, logic netwo rk can be . .
� e ,scan address, inpu ts are apph ed directly to the memory
out network . 'fh
array. The data input and the write -enab le input of the array receive the
scan data and the scan c lock, respectively. The outp ut of the mem ory
array is ANDed into the scan -out tree w be observed.
The technique has also a few disadvantages:

1 . Extra logic in the foTITI of two address gates for each m�mory element,
plus the address decoders -ar:1d output AND treesr result m 3-4 gates
overhead per memory element.
2. Scan control, data, and address pins add up w 1 0-20 extra pins . By using
a serially loadable address counter. the n u m ber of pins can be reduced to
around 6.
3. Some constrain ts are imposed on the logic design, such as the exclusion
of asynchronous latch operation.

S. 7 Partial Scan

In full scan, all fli p-flops in a circuit are coID1ected into one o� more shift regjsters;
thus, the states of a circuit can be controlled and observed via the primary inputs
and outputs, respectively. In partial scan. only a subset of the circuit flip-flops are
included i n the scan chain in order to reduce the overhead associated with full
scan design [5. 1 2]. Figure 5.30 shows a structure of partial scan design. This
structure has two separate clocks: a system clock and a scan clock. The scan clock
controls only the scan flip-flops. Note that the scan clock is derived by gating the
system clock with the scan-enable signal; no external clock is necessary. During
the normal mode of operation. namely. scan-enable signal at logic 0, both scan
and nonscan flip-flops update thei r states when the system clock is applied. In
the scan mode operation, only the state of the shift register (constructed from the
scan flip-flops) is shi fted one bit w ith the application of the scan flip-flop; the
nonscan flip- flops do not change their states.
The disadvantage of two-clock partial scan is that the routing of two separate
cl0<.:ks with small skews is very difficult to achieve. Also, the use of a separate
scan clock does not allow the testing of the circuit at its normal operating speed.
Cheng [5. 1 3] proposed a partial scan scheme, shown in Fig. 5.3 1 . in which the
system clock is also used as the scan clock. Both scan and nonscan flip-flops
 1 26 S. J>esign of Te table Sequent ial · ·ircult4l

Sysr m clock ------.

Scan enable -----

.-+----1 D Q
Scan fl ip-nop.
......,____, D Q

---->
Primary .i opucs
Com b'in:itJona
logic
. 1 Combinational
logic

D Q
/ Nonscan flip-nops

D Q

Figure 5.30 Partial scan.

move to their next states when the system clock is applied. A test sequence is
derived by shifting data into the scan flip-flops. This data together with the con-
tents of nonscan fl ip-flops constitute the starting state of the test sequence. The 'II
other patterns in the sequence are obtained by single-bit shifting of the contents
of scan flip-flops, which form part of the required circuit states. Tot remaining
bits of the states, that is, the contents of nonscan flip-flops, are detenn ined by the
fu nctional logic. Note that this form of partial scan scheme allows only a limited
number of valid next states to be reached from the starting state of the test se­
quence. Thi s may limit the fault coverage obtained by using the technique.
The selection fli_p-flops to be included in the partial scan is done by heuristic
methods. Trischler [5. 1 4] has used testabil ity anaJysis t.o show that the fault cov ­
erage in a circuit can be significantly increased by incl uding .1 5-25% of the flip-
 5.8 Te table 'equential lrcui D ign sing onscan Te.chniques 1 27

Sy�t m clock
Scan enable

.
'D
-t> QI V Scan flip-flops
,,
I
'D
,/ Q I .I
-
�
L..A..
.,
'D
of Combinational
>
Primary inputs V
logjc logic
>
Combinational �
y

•
QI
�D
.. v r onscan ip-flops
�
/
---
/

-
uo Q I
Figure 5.31 Partial scan using the ·ysrem cloc

flops in the partial scan. Agrawal et al. (5 . 1 5] have hown that the fault coverage
can be increased to as high as 95% by including les than 65% of the flip-flop
in the partial scan.

5.8 Testable Sequential Circuit Design Using

Nonscan Techniques

Full and partial scan techniques improve the controllability and observability of
flip-flops in sequential circuit, and Lherefore the test generation for such circujts
is considerably simplified. However, a scan-based circuit cannot be tested at its
normal speed, because test data have to be shifted in and our via the scan path.