DSP Pyq
DSP Pyq
UNIT-I
1. a) State the time shifting property of z-transform. [7M]
b) Determine the impulse response of the filter defined by y(n)=x(n)+by(n-1). [7M]
(OR)
2. a) State and prove the properties of convolution. [7M]
b) Give the frequency domain representation of discrete time signals. [7M]
UNIT-II
3. a) Determine IDFT of the following [7M]
(i) X(k)={1,1-j2,-1,1+j2} (ii)X(k)={1,0,1,0}
b) Find the DFT of the sequence x[n]={1,2,3,4,5,6,7,8} using DIT FFT. [7M]
(OR)
4. a) How is the FFT algorithm applied to determine inverse discrete Fourier [7M]
transform?
b) Derive the equation to implement a butterfly structure In DIFFFT algorithm. [7M]
UNIT-III
5. a) Explain the differences between Direct form-I and Direct form-II structures. [7M]
b) What is meant by frequency warping effect? [7M]
(OR)
6. a) What are the basic building blocks of realization structures? [7M]
b) Determine the cascade and parallel realization for the system transfer function [7M]
H(z) = 3(Z 2 +5Z+4) / (2Z+1)(Z+2).
UNIT-IV
7. a) Draw the frequency response of digital low pass and high pass filters. [7M]
b) Explain the frequency-sampling method of FIR filter design with an example. [7M]
(OR)
8. a) What conditions are to be satisfied by the impulse response of an FIR system in [7M]
order to have a linear phase?
b) Distinguish between IIR and FIR filters. [7M]
UNIT-V
9. a) What are the special addressing modes of DSP? Explain. [7M]
b) Draw the configuration of a pipelined MAC unit. [7M]
(OR)
10. a) Explain the purpose of six registers used in the TMS320C2X processor. [7M]
b) What are the limitations of pipelining in Digital Signal Processor? [7M]
1 of 1
|'''|'|'|''||'''||||
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32
|'''|'|'|''||'''||||
Code No: R203147A
R2031011
R2031351
R203135A
R203147C
R203105O
P2031051
R2032043 R20 SET
SET
RA--42
UNIT-I
1. a) State and prove final-value theorem of z-transform. [7M]
b) Determine the impulse response of the filter defined by y(n)=x(n)+by(n-1). [7M]
(OR)
2. a) What are the basic elements of a DSP system? Explain. [7M]
2
b) Test the following systems for time invariance y(n)=n x (n). [7M]
UNIT-II
3. a) Find the linear convolution of the sequences x[n]={ 1,4,0,9,-1} and h[n]= {-3,- [7M]
4,0,7}
b) Find the IDFT of Y (k) = (1, 1, 1, 0). [7M]
(OR)
4. a) What are the advantages FFT over DFT. [7M]
b) Find the DFT of the sequence x[n]={1,2,1,2,1,2,1,2} using decimation in time [7M]
algorithm.
UNIT-III
5. a) Obtain the direct form I, direct form II and Cascade form realization of the [7M]
following system functions.
Y(n) = 0.1 y(n-1) + 0.2 y(n-2) + 3x(n) + 3.6 x(n-1) + 0.6 x(n-2).
b) Compare Chebyshev Filter and Butterworth Filter. [7M]
(OR)
6. a) Obtain direct form I, direct form II and cascade realizations of system [7M]
described by the equation, y[n]=y[n-1]-(1/2)y[n-2]+x[n]-x[n-1]+x[n-2]
b) State and prove Parsvel’s theorem. [7M]
UNIT-IV
7. a) Explain the need for the use of window sequence in the design of FIR filter. [7M]
Describe the window sequence generally used and compare the properties.
b) Draw the indirect form realizations of FIR systems? [7M]
(OR)
8. a) Compare Chebyshev Filter and Butterworth Filter. [7M]
b) Explain the impulse invariance method of IIR filter design. [7M]
UNIT-V
9. a) What are the on-chip peripherals of programmable DSP? [7M]
b) Explain the difference between Von Neumann and Harvard architectures. [7M]
Which architecture is preferred for DSP applications and why?
(OR)
10. a) Explain what is meant by instruction pipelining. [7M]
b) What is the use of MAC unit in DSP architecture? [7M]
1 of 1
|'''|'|'|''||'''||||
Code No: R2032043 R20 SET -1
|'''|'|'|''||'''||||
Code No: R2032043 R20 SET -1
(OR)
8. a) Explain the need for the use of window sequence in the design of FIR filter. Describe [7M]
the window sequence generally used and compare the properties.
b) Determine the lattice filter representation for the following FIR filter: [7M]
H(z) = 1+ 7/8 z-1 + 11/16 z-2 + ¼ z-3
1 of 2
|''|'||||''|'''|||'|
Code No: R2032043 R20 SET -1
UNIT-V
9. a) Discuss the salient features and special addressing modes of Digital signal [7M]
processors.
b) Explain briefly the following for TMS320C5X: i) Flags available in status register ii) [7M]
Parallel Logic Unit.
(OR)
10. a) Explain in detail the architecture of TMS320C5X processor. [7M]
b) With neat block diagram, explain about the pipelining in DSP processors. [7M]
2 of 2
|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--22
b) Given a 3-stage lattice FIR filter with coefficients, k1=(1/4); k2=(1/2); k3=(1/3); [7M]
Determine the FIR filter coefficients for the direct form structure.
(OR)
8. a) Design a low pass filter using Hanning window with a cutoff frequency of 0.9 [7M]
radians/sec and N=6. Draw the filter structure and plot its spectrum.
b) Find the structural representation in direct and transposed form for system [7M]
described by the difference equation.
y(n) = x(n) – 0.3 x(n - 1) - 0.7 x(n - 2) + 0.6 y(n - 1) + 0.8 y(n - 2)
1 of 2
|''|'||||''|'''|||'|
Code No: R2032043 R20 SET - 2
UNIT-V
9. a) Explain in brief memory access schemes in DSP processors. [7M]
b) Draw the pipelined MAC configuration to perform convolution operation and [7M]
Explain with neat timing diagrams.
(OR)
10. a) Explain how the VLIW architecture is improving the performance of DSP [7M]
processor.
b) What is meant by bit reversed addressing mode? What is the application for [7M]
which this addressing mode is preferred?
2 of 2
|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32
UNIT-I
1. a) Define an LTI System and show that the output of an LTI system is given by the [7M]
convolution of Input sequence and impulse response.
b) Check the following filter for time invariant, causal and linear [7M]
i) y (n) = (n-1) (n+1) ii) y(n) = x (n-2)
(OR)
2. a) Explain the concept of stability and causality with examples. [7M]
b) An LTI system is described by the equation y(n)=x(n)+0.81x(n-1)-0.81x(n2)-0.45y(n- [7M]
2). Determine the transfer function of the system. Sketch the poles and zeroes on the
Z-plane
UNIT-II
3. a) Perform i) Linear Convolution ii) Circular Convolution for the following [7M]
sequence
x(n)= 1, n=0 h(n) = 0.5, n= 0
= 0.5, n=1 = 1, n= 1
= 0, otherwise = 0, otherwise
And Show when they are equal.
b) Develop a radix-2 DIT FFT algorithm for evaluating the DFT for N = 8. [7M]
(OR)
4. a) Explain how DFT provides an alternative approach to time domain convolution [7M]
through linear filtering.
b) Find the DFT of the given sequence by using DIF FFT. [5+5] x(n) = {0.5, 1.5, -0.5, - [7M]
0.5}
UNIT-III
5. a) Design an analog filter for the following specifications: [7M]
|''|'||||''|'''|||'|
Code No: R2032043 R20 SET -3
8. a) Using a Hanning window technique, design a low pass filter with pass band gain of [7M]
unity, cut-off frequency of 1000Hz and working at a sampling frequency of 5 KHz.
The length of the impulse response should be 7
b) [7M]
Realize the system function by linear phase FIR structure.
UNIT-V
9. a) Write about the architectural features of TMS320C5X DSP processor. [7M]
b) How much memory can be Interfaced to TMS320C5X? Explain in detail its [7M]
Memory mapping.
(OR)
10. a) Explain the special addressing modes of DSP with suitable examples. [7M]
b) Explain the i) Bus Structure ii) On-chip peripherals in a TMS320C5X DSP [7M]
processor.
2 of 2
|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--42
UNIT-I
1. a) Determine the impulse response h(n) for the system described by the second order [7M]
difference equation y (n) – 4 y (n-1) + 4 y (n-2) = x (n-1)
b) Establish the relation between DFT and Z-transform. [7M]
(OR)
2. a) Determine the stability of the following systems using Z-transform: [7M]
i) h(n) = 2n u(n) ii) h(n) = 5n u(3-n)
b) Determine the causal signal x(n) having the Z-transform [7M]
X(Z) = (Z2+Z )/[ (Z- ½)2 (Z-¼) ]
UNIT-II
3. a) Find the DFT of a sequence y[n)= { 1,2,3,4,4,3,2,1} using: [7M]
i) DIT algorithm ii) DIF algorithm.
b) Let x(n) be a real valued sequence with N-points and Let X(K) represent its DFT , [7M]
with real and imaginary parts denoted by XR(K) and XI (K) respectively. So that
X (K) = XR (K) + JXI (K). Now show that if x (n) is real, XR (K) is even and XI (K) is
odd.
(OR)
4. a) Compute 4-point DFT of a sequence x (n) = { 0,1,2,3} using DIT algorithm. [7M]
b) Draw the butterfly line diagram for 8 - point FFT calculation and briefly explain. Use [7M]
decimation -in-time algorithm.
UNIT-III
5. a) [7M]
Apply bilinear transformation to
b) For the given specifications design an analog Butterworth filter. [7M]
(OR)
6. a) Using the bilinear transform, design a high pass filter, monotonic in password with [7M]
cutoff frequency of 1000 Hz and down 10 dB at 350 Hz. The sampling frequency is
5000 Hz.
b) What are the steps to design an analog Chebyshev High pass filter. [7M]
UNIT-IV
7. a) Explain the design procedure of linear phase FIR filter using Fourier series method. [7M]
b) Consider a second order IIR filter with: [7M]
.
Find the effect on quantization on pole locations of the given system function in direct
form and in cascade form. Assume b=3 bits.
(OR)
8. a) Explain the type -1 FIR filter design procedure using frequency sampling method. [7M]
b) Explain how reduction of product round-off error is achieved in digital filters? [7M]
1 of 2
|''|'||||''|'''|||'|
Code No: R2032043 R20 SET -4
UNIT-V
9. a) Discuss various interrupt types supported by TMS320C5X processor. [7M]
b) Explain the memory access schemes in P-DSP’s. [7M]
(OR)
10. a) Explain the functioning of Multiplier and Multiplier Accumulator in DSP [7M]
processor.
b) Explain the functions of on-chip peripherals in a DSP processor. [7M]
2 of 2
|''|'||||''|'''|||'|