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DSP Pyq

The document outlines the examination structure for Digital Signal Processing for III B. Tech II Semester, including various units and questions related to LTI systems, FFT algorithms, IIR and FIR filter design, and DSP architectures. Each unit contains multiple questions from which students are required to answer five, with equal marks assigned to each question. The exam is scheduled for May/June 2024, with a maximum score of 70 marks.

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Eswar
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
43 views13 pages

DSP Pyq

The document outlines the examination structure for Digital Signal Processing for III B. Tech II Semester, including various units and questions related to LTI systems, FFT algorithms, IIR and FIR filter design, and DSP architectures. Each unit contains multiple questions from which students are required to answer five, with equal marks assigned to each question. The exam is scheduled for May/June 2024, with a maximum score of 70 marks.

Uploaded by

Eswar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

Code No: R2032043 R20 SET -1

III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) What is the condition for stability of an LTI system? [7M]
b) Find the impulse response ℎ[݊] of the system described by the difference [7M]
equation 8‫ ]݊[ ݕ‬+ 6‫ – ݊[ ݕ‬1] = ‫]݊[ݔ‬.
(OR)
2. a) What are the conditions for stability and causality of an LTI system? Explain [7M]
b) For a system described by 8‫ [݊[ ݕ‬+ 4‫ – ݊[ ݕ‬1[ + ‫ – ݊[ ݕ‬2[ = ‫ ]݊[ݔ‬Find the [7M]
response to a unit amplitude complex sinusoidal excitation at a DT cyclic
frequency Ω.
UNIT-II
3. a) Explain the significance of FFT algorithms. Draw the basic butterfly diagram [7M]
for radix - 2 DIT-FFT.
b) Find the DFT of x[n]={0.5,0.5,0.5,0.5,-1,-1,-1,-1} using decimation in time [7M]
algorithm.
(OR)
4. a) What is FFT? How many multiplications and additions are required to compute [7M]
N point DFT using redix-2 FFT?
b) State and prove convolution Properties of DFT. [7M]
UNIT-III
5. a) Compare direct form I and direct form II realization of IIR systems. [7M]
b) Realize the following IIR system functions in the direct form I and II and also [7M]
parallel form H(Z)=1/(1+aZ-1)(1-bZ-1).
(OR)
6. a) With an example explain the design procedure for Butterworth filter. [7M]
b) Give block diagram representation of linear constant-coefficient difference [7M]
equations.
UNIT-IV
7. a) Draw the spectrum of rectangular window function. [7M]
b) What are the characteristics of linear phase FIR digital filters? [7M]
(OR)
8. a) Design an FIR digital low pass filter with cutoff frequency 1.2 radian and length [7M]
ܰ = 7. Use frequency sampling method
b) What are the characteristics of FIR digital filters? [7M]
UNIT-V
9. a) What is meant by bit reversed addressing mode? What is the application for [7M]
which this addressing mode is preferred?
b) Draw the pipelined MAC configuration to perform convolution operation and [7M]
explain with neat timing diagrams.
(OR)
10. a) What do you mean by circular buffer? [6M]
b) What are the architectural features of TMS320C5x DSP? [8M]
1 of 1
|'''|'|'|''||'''||||
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--22

III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) State the time shifting property of z-transform. [7M]
b) Determine the impulse response of the filter defined by y(n)=x(n)+by(n-1). [7M]
(OR)
2. a) State and prove the properties of convolution. [7M]
b) Give the frequency domain representation of discrete time signals. [7M]
UNIT-II
3. a) Determine IDFT of the following [7M]
(i) X(k)={1,1-j2,-1,1+j2} (ii)X(k)={1,0,1,0}
b) Find the DFT of the sequence x[n]={1,2,3,4,5,6,7,8} using DIT FFT. [7M]
(OR)
4. a) How is the FFT algorithm applied to determine inverse discrete Fourier [7M]
transform?
b) Derive the equation to implement a butterfly structure In DIFFFT algorithm. [7M]
UNIT-III
5. a) Explain the differences between Direct form-I and Direct form-II structures. [7M]
b) What is meant by frequency warping effect? [7M]
(OR)
6. a) What are the basic building blocks of realization structures? [7M]
b) Determine the cascade and parallel realization for the system transfer function [7M]
H(z) = 3(Z 2 +5Z+4) / (2Z+1)(Z+2).
UNIT-IV
7. a) Draw the frequency response of digital low pass and high pass filters. [7M]
b) Explain the frequency-sampling method of FIR filter design with an example. [7M]
(OR)
8. a) What conditions are to be satisfied by the impulse response of an FIR system in [7M]
order to have a linear phase?
b) Distinguish between IIR and FIR filters. [7M]
UNIT-V
9. a) What are the special addressing modes of DSP? Explain. [7M]
b) Draw the configuration of a pipelined MAC unit. [7M]
(OR)
10. a) Explain the purpose of six registers used in the TMS320C2X processor. [7M]
b) What are the limitations of pipelining in Digital Signal Processor? [7M]

1 of 1

|'''|'|'|''||'''||||
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32

III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Explain the frequency response of discrete time system. [7M]
b) Determine the frequency response for the system given by [7M]
y(n)-3/4y(n-1)+1/8 y(n-2) = x(n)- x(n-1).
(OR)
2. a) Determine whether the following system given by y(n) = log10[{x(n)}] is [7M]
Casual or not.
b) Show that an LTI system can be described by its unit sample response. [7M]
UNIT-II
3. a) Explain the significance of FFT algorithms. Draw the basic butterfly diagram [7M]
for radix - 2 DIT-FFT.
b) Find the DFT of x[n]={0.5,0.5,0.5,0.5,-1,-1,-1,-1} using decimation in time [7M]
algorithm.
(OR)
4. a) Compute the DFT for the sequence (0.5,0.5,0.5,0.5,1,1,1,1) using DIF-FFT. [7M]
b) State and prove convolution Properties of DFT. [7M]
UNIT-III
5. a) Draw the direct form II structure for the given system [7M]

b) Explain Transposed forms. [7M]


(OR)
6. a) Prove that FIR filter has linear phase if the unit impulse response satisfies the [7M]
condition h(n)=h(N-1-n), n=0,1,……M-1. Also discuss symmetric and
antisymmetric cases of FIR filter.
b) Why IIR filters do not have linear phase? [7M]
UNIT-IV
7. a) Write some examples of multirate digital systems. [7M]
b) What is a Kaiser window? In what way is it superior to other window [7M]
functions?
(OR)
8. a) What is a Hamming window function? Obtain its frequency domain [7M]
characteristics.
b) What is the impulse invariant technique? [7M]
UNIT-V
9. a) Describe the multiplier/adder unit of TMS320c54xx processor with a neat [7M]
block diagram.
b) What are interrupts? What are the classes of interrupts available in the [7M]
TMS320C5xx processor?
(OR)
10. a) Explain the different types of interrupts in TMS320C54xx Processors. [7M]
b) Describe any four data addressing modes of TMS320C54xx processor. [7M]
1 of 1

|'''|'|'|''||'''||||
Code No: R203147A
R2031011
R2031351
R203135A
R203147C
R203105O
P2031051
R2032043 R20 SET
SET
RA--42

III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) State and prove final-value theorem of z-transform. [7M]
b) Determine the impulse response of the filter defined by y(n)=x(n)+by(n-1). [7M]
(OR)
2. a) What are the basic elements of a DSP system? Explain. [7M]
2
b) Test the following systems for time invariance y(n)=n x (n). [7M]
UNIT-II
3. a) Find the linear convolution of the sequences x[n]={ 1,4,0,9,-1} and h[n]= {-3,- [7M]
4,0,7}
b) Find the IDFT of Y (k) = (1, 1, 1, 0). [7M]
(OR)
4. a) What are the advantages FFT over DFT. [7M]
b) Find the DFT of the sequence x[n]={1,2,1,2,1,2,1,2} using decimation in time [7M]
algorithm.
UNIT-III
5. a) Obtain the direct form I, direct form II and Cascade form realization of the [7M]
following system functions.
Y(n) = 0.1 y(n-1) + 0.2 y(n-2) + 3x(n) + 3.6 x(n-1) + 0.6 x(n-2).
b) Compare Chebyshev Filter and Butterworth Filter. [7M]
(OR)
6. a) Obtain direct form I, direct form II and cascade realizations of system [7M]
described by the equation, y[n]=y[n-1]-(1/2)y[n-2]+x[n]-x[n-1]+x[n-2]
b) State and prove Parsvel’s theorem. [7M]
UNIT-IV
7. a) Explain the need for the use of window sequence in the design of FIR filter. [7M]
Describe the window sequence generally used and compare the properties.
b) Draw the indirect form realizations of FIR systems? [7M]
(OR)
8. a) Compare Chebyshev Filter and Butterworth Filter. [7M]
b) Explain the impulse invariance method of IIR filter design. [7M]
UNIT-V
9. a) What are the on-chip peripherals of programmable DSP? [7M]
b) Explain the difference between Von Neumann and Harvard architectures. [7M]
Which architecture is preferred for DSP applications and why?
(OR)
10. a) Explain what is meant by instruction pipelining. [7M]
b) What is the use of MAC unit in DSP architecture? [7M]
1 of 1

|'''|'|'|''||'''||||
Code No: R2032043 R20 SET -1

III B. Tech II Semester Supplementary Examinations, December -2023


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Perform addition and multiplication of the discrete time signals, x1(n) = {2, 2, 1, [7M]
2} and x2(n) = {-2, -1, 3,2}
b) State and prove final value theorem with regard to Z-transform? [7M]
(OR)
2. a) With suitable example, express the discrete time signal x (n) as a summation of [7M]
impulses?
b) What is BIBO stability? What is the condition to be satisfied for stability? [7M]
UNIT-II
3. a) Find the response of an LTI system with impulse response h(n) = {2,1,3} for the [7M]
input x (n) = {1,2} using DIT radix -2 FFT algorithm?
b) State and prove convolution theorem of DFT? [7M]
(OR)
4. a) Compute the eight point DFT of the sequence x(n) = {1/2,1/2,1/2,1/2,0,0,0,0} [7M]
using radix 2 decimation in time and radix 2 decimation in frequency algorithm.
b) What is twiddle factor? What are the phase factors involved in the third stage of [7M]
computation in the 8-point DIT radix-2 FFT?
UNIT-III
5. a) Determine the poles of low pass Butterworth filter for N=1. Sketch the location of [7M]
poles on s-plane and hence determine the normalized transfer function of low pass
filter?
b) Write the magnitude function of low pass Butterworth filter? How the order of the [7M]
filter affects the frequency response of Butterworth filter?
(OR)
6. a) Draw the basic structure of IIR system and explain inbrief? [7M]
b) Sketch the magnitude response of type-1 chebyshev filter? How will you [7M]
determine order N of chebyshev filter?
UNIT-IV
7. a) Derive the frequency response of linear phase FIR filter when impulse response is [7M]
symmetric with centre of symmetry at (N-1)/2 and N is odd?
b) Draw the structure of FIR lattice filter for Nth order and explain the same? [7M]
(OR)
8. a) Explain the design procedure of FIR Filters by Frequency Sampling Technique? [7M]
b) List out the different types of window sequences used in FIR filter? List the [7M]
characteristics of FIR filters designed using windows?
UNIT-V
9. a) Draw and explain the modified Harvard architecture employed in DSPs? [7M]
b) Briefly discuss about MAC unit in DSPs with neat diagram? [7M]
(OR)
10. a) What are the functional units of CPU of TMS320C5x processor? Explain [7M]
b) List out the features of the TMS320C5x family of digital signal processors? [7M]
1 of 1

|'''|'|'|''||'''||||
Code No: R2032043 R20 SET -1

III B. Tech II Semester Regular Examinations, July -2023


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Find the linear, invariance and casuality property of given system represented by : [7M]
y(n) = x(n) – ax(n - 1).
b) Find the convolution of the signals x(n) = i) (a)nu(n) and h(n) = (b)nu(n). [7M]
(OR)
2. a) Write the properties of ROC of X(z). [7M]
b) Find the magnitude and phase response for the system characterized by the difference [7M]
equation .
UNIT-II
3. a) State and prove the following properties of DFT [7M]
i) circular frequency shift ii)Parseval’s Theorem.
b) Develop a DIF FFT algorithm and draw its flow diagram. [7M]
(OR)
4. a) Find the DFT of i) x*(n) ii) x*(-n) iii) Re{x(n)} iv) Im {x(n)} [7M]
b) Find the IDFT of the sequence using DIF algorithm Y (k) = {10, -2-j2, -2, -2+j2} [7M]
UNIT-III
5. a) Determine the digital filter Transformation from the following analog T.F [7M]
Ha(s)= 1 / (s+0.5)(s2+0.5s+2) using Impulse Invariant Method .Assume Ts= 1
sec.
b) With an example explain the design procedure for Butterworth filter [7M]
(OR)
6. a) Design a digital Butterworth filter that satisfies the following specifications : [7M]
0.9< |H(jw)| ≤ 1, for 0 ≤ w ≤ π /2
|(H(jw)|< 0.2 , for ¾ π ≤w≤ π using BLT .Assume Ts= 1 sec
b) Explain basic structures and Transposed forms of IIR systems with suitable [7M]
examples.
UNIT-IV
7. a) Design a 7-tap linear FIR Digital filter with a cut-off frequency of ±3 π/4 rad [7M]
using hamming window.
b) Obtain the parallel realization of the system described by the difference equation [7M]

(OR)
8. a) Explain the need for the use of window sequence in the design of FIR filter. Describe [7M]
the window sequence generally used and compare the properties.
b) Determine the lattice filter representation for the following FIR filter: [7M]
H(z) = 1+ 7/8 z-1 + 11/16 z-2 + ¼ z-3

1 of 2

|''|'||||''|'''|||'|
Code No: R2032043 R20 SET -1

UNIT-V
9. a) Discuss the salient features and special addressing modes of Digital signal [7M]
processors.
b) Explain briefly the following for TMS320C5X: i) Flags available in status register ii) [7M]
Parallel Logic Unit.
(OR)
10. a) Explain in detail the architecture of TMS320C5X processor. [7M]
b) With neat block diagram, explain about the pipelining in DSP processors. [7M]

2 of 2

|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--22

III B. Tech II Semester Regular Examinations, July -2023


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Determine the Inverse Z-Transform of: X(Z)=1/(1-Z -1 )(1-Z -1 )2 . [7M]
b) Defne Disrete time systems ,explain the classification with suitable exampls [7M]
(OR)
2. a) Find the frequency response H(ejw) of the linear time-invariant system whose [7M]
input and output satisfy the difference equation:

b) A causal LTI system is defined by the difference equation: [7M]


2y(n)-y(n-2)=x(n1)+3x(n-2)+2x(n-3). Find the frequency response H (e jw),
magnitude response and phase response.
UNIT-II
3. a) Define DFT and then state and prove properties of DFT. [7M]
b) Given X(K) = { 36,-4+j9.565, -4+j4,-4+j1.656,-4,-4-j1.656,-4-j4,-4-j9.656} [7M]
find x(n) using FFT algorithm
(OR)
4. a) Show how the complexity of computing DFT can be reduced by Radix-2 DIF [7M]
algorithm with suitable diagrams.
b) [7M]
Determine the 8 point DFT of the sequence
UNIT-III
5. a) For the analog transfer function H(s) = 2/ {(s+2) (s+3)}. Determine H (z) using [7M]
impulse invariance method. Assume T = 1 sec
b) Determine the order and poles of type-I chebyshev low pass filter for the given [7M]
specifications:
αp = 1 dB, αs = 40 dB, Ωp= 1000Π rad/sec Ωs = 2000 Π rad/ sec.
(OR)
6. a) Design a digital second order Low-Pass Butterworth filter with cut-off [7M]
frequency 2.2KHz using Bilinear Transformation. Sampling rate 8 KHz
b) Compare Impulse invariant and bilinear transformation methods. [7M]
UNIT-IV
7. a) Design an FIR low pass filter satisfying the following specifications [7M]

b) Given a 3-stage lattice FIR filter with coefficients, k1=(1/4); k2=(1/2); k3=(1/3); [7M]
Determine the FIR filter coefficients for the direct form structure.
(OR)
8. a) Design a low pass filter using Hanning window with a cutoff frequency of 0.9 [7M]
radians/sec and N=6. Draw the filter structure and plot its spectrum.
b) Find the structural representation in direct and transposed form for system [7M]
described by the difference equation.
y(n) = x(n) – 0.3 x(n - 1) - 0.7 x(n - 2) + 0.6 y(n - 1) + 0.8 y(n - 2)
1 of 2

|''|'||||''|'''|||'|
Code No: R2032043 R20 SET - 2

UNIT-V
9. a) Explain in brief memory access schemes in DSP processors. [7M]
b) Draw the pipelined MAC configuration to perform convolution operation and [7M]
Explain with neat timing diagrams.
(OR)
10. a) Explain how the VLIW architecture is improving the performance of DSP [7M]
processor.
b) What is meant by bit reversed addressing mode? What is the application for [7M]
which this addressing mode is preferred?

2 of 2

|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32

III B. Tech II Semester Regular Examinations, July -2023


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) Define an LTI System and show that the output of an LTI system is given by the [7M]
convolution of Input sequence and impulse response.
b) Check the following filter for time invariant, causal and linear [7M]
i) y (n) = (n-1) (n+1) ii) y(n) = x (n-2)
(OR)
2. a) Explain the concept of stability and causality with examples. [7M]
b) An LTI system is described by the equation y(n)=x(n)+0.81x(n-1)-0.81x(n2)-0.45y(n- [7M]
2). Determine the transfer function of the system. Sketch the poles and zeroes on the
Z-plane
UNIT-II
3. a) Perform i) Linear Convolution ii) Circular Convolution for the following [7M]
sequence
x(n)= 1, n=0 h(n) = 0.5, n= 0
= 0.5, n=1 = 1, n= 1
= 0, otherwise = 0, otherwise
And Show when they are equal.

b) Develop a radix-2 DIT FFT algorithm for evaluating the DFT for N = 8. [7M]
(OR)
4. a) Explain how DFT provides an alternative approach to time domain convolution [7M]
through linear filtering.
b) Find the DFT of the given sequence by using DIF FFT. [5+5] x(n) = {0.5, 1.5, -0.5, - [7M]
0.5}
UNIT-III
5. a) Design an analog filter for the following specifications: [7M]

-1< |H(jΩ)|db ≤ 0, for 0 ≤ Ω ≤1404π rad/s


|(H(jΩ)|db< -60 , for Ω ≥ 8268π rad/s
b) Discuss the impulse invariant method and also explain its limitations. [7M]
(OR)
6. a) Explain the procedure for designing Analog filters using the Chebyshev [7M]
approximation.
b) Using Bilinear transformation, design a high pass filter, monotonic in pass band with [7M]
cutoff frequency of 1000 Hz and down 10dB at 350 Hz. The sampling frequency is
5000 Hz.
UNIT-IV
7. a) Explain the canonical form of digital filter realization with suitable examples. [7M]
b) Design a FIR digital low-pass filter with a cutoff frequency of 1 kHz and a sampling [7M]
rate of 4 kHz with 7 samples using Fourier series method.
(OR)
1 of 2

|''|'||||''|'''|||'|
Code No: R2032043 R20 SET -3

8. a) Using a Hanning window technique, design a low pass filter with pass band gain of [7M]
unity, cut-off frequency of 1000Hz and working at a sampling frequency of 5 KHz.
The length of the impulse response should be 7
b) [7M]
Realize the system function by linear phase FIR structure.
UNIT-V
9. a) Write about the architectural features of TMS320C5X DSP processor. [7M]
b) How much memory can be Interfaced to TMS320C5X? Explain in detail its [7M]
Memory mapping.
(OR)
10. a) Explain the special addressing modes of DSP with suitable examples. [7M]
b) Explain the i) Bus Structure ii) On-chip peripherals in a TMS320C5X DSP [7M]
processor.

2 of 2

|''|'||||''|'''|||'|
Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--42

III B. Tech II Semester Regular Examinations, July -2023


DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) Determine the impulse response h(n) for the system described by the second order [7M]
difference equation y (n) – 4 y (n-1) + 4 y (n-2) = x (n-1)
b) Establish the relation between DFT and Z-transform. [7M]
(OR)
2. a) Determine the stability of the following systems using Z-transform: [7M]
i) h(n) = 2n u(n) ii) h(n) = 5n u(3-n)
b) Determine the causal signal x(n) having the Z-transform [7M]
X(Z) = (Z2+Z )/[ (Z- ½)2 (Z-¼) ]
UNIT-II
3. a) Find the DFT of a sequence y[n)= { 1,2,3,4,4,3,2,1} using: [7M]
i) DIT algorithm ii) DIF algorithm.
b) Let x(n) be a real valued sequence with N-points and Let X(K) represent its DFT , [7M]
with real and imaginary parts denoted by XR(K) and XI (K) respectively. So that
X (K) = XR (K) + JXI (K). Now show that if x (n) is real, XR (K) is even and XI (K) is
odd.
(OR)
4. a) Compute 4-point DFT of a sequence x (n) = { 0,1,2,3} using DIT algorithm. [7M]
b) Draw the butterfly line diagram for 8 - point FFT calculation and briefly explain. Use [7M]
decimation -in-time algorithm.
UNIT-III
5. a) [7M]
Apply bilinear transformation to
b) For the given specifications design an analog Butterworth filter. [7M]

(OR)
6. a) Using the bilinear transform, design a high pass filter, monotonic in password with [7M]
cutoff frequency of 1000 Hz and down 10 dB at 350 Hz. The sampling frequency is
5000 Hz.
b) What are the steps to design an analog Chebyshev High pass filter. [7M]
UNIT-IV
7. a) Explain the design procedure of linear phase FIR filter using Fourier series method. [7M]
b) Consider a second order IIR filter with: [7M]
.
Find the effect on quantization on pole locations of the given system function in direct
form and in cascade form. Assume b=3 bits.
(OR)
8. a) Explain the type -1 FIR filter design procedure using frequency sampling method. [7M]
b) Explain how reduction of product round-off error is achieved in digital filters? [7M]
1 of 2

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Code No: R2032043 R20 SET -4

UNIT-V
9. a) Discuss various interrupt types supported by TMS320C5X processor. [7M]
b) Explain the memory access schemes in P-DSP’s. [7M]
(OR)
10. a) Explain the functioning of Multiplier and Multiplier Accumulator in DSP [7M]
processor.
b) Explain the functions of on-chip peripherals in a DSP processor. [7M]

2 of 2

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