FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

January 2000

FM27C040
4,194,304-Bit (512K x 8) High Performance
CMOS EPROM
General Description Features
The FM27C040 is a high performance, 4,194,304-bit Electrically ■ High performance CMOS
Programmable UV Erasable Read Only Memory. It is organized — 120, 150ns access time*
as 512K words of 8 bits each. Its pin-compatibility with byte-wide ■ Simplified upgrade path
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. —VPP is a “Don’t Care” during normal read operation
The “Don’t Care” feature on VPP during read operations allows
■ Manufacturer’s identification code
memory expansions from 1M to 8 Mbits with no printed circuit
board changes. ■ JEDEC standard pin configuration
— 32-pin PDIP
The FM27C040 provides microprocessor-based systems exten- — 32-pin PLCC
sive storage capacity for large portions of operating system and — 32-pin CERDIP
application software. Its 120ns access time provides high speed
operation with high-performance CPUs. The FM27C040 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C040 is manufactured using Fairchild’s advanced CMOS
AMG™ EPROM technology. *Note: New revision meets 70ns. Please check with factory for availability.

Block Diagram
Data Outputs O0 - O7
VCC
GND
VPP

OE Output Enable,
Chip Enable, and
CE/PGM Output
Program Logic
Buffers

Y Decoder
..

Y Gating

A0 - A18
Address
Inputs
.......

4,194,304-Bit
Cell Matrix
X Decoder

DS800033-1

AMG™ is a trademark of WSI, Inc.

© 1999 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Connection Diagrams
27C010 FM27C040 27C010

XX/VPP XX/VPP 1 32 VCC VCC

A16 A16 2 31 A18 XX/PGM
A15 A15 3 30 A17 NC
A12 A12 4 29 A14 A14
A7 A7 5 28 A13 A13
A6 A6 6 27 A8 A8
A5 A5 7 26 A9 A9
A4 A4 8 25 A11 A11
A3 A3 9 24 OE OE
A2 A2 10 23 A10 A10
A1 A1 11 22 CE/PGM CE
A0 A0 12 21 O7 O7
O0 O0 13 20 O6 O6
O1 O1 14 19 O5 O5
O2 O2 15 18 O4 O4
GND GND 16 17 O3 O3
DS800033-2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin.

Commercial Temperature Range Extended Temperature Range

(0°C to +70°C) VCC = 5V ±10% (-40°C to +85°C) VCC = 5V ±10%
Parameter/Order Number Access Time (ns) Parameter/Order Number Access Time (ns)
FM27C040 Q, N, V 90 90 FM27C040 QE, NE, VE 90 90
FM27C040 Q, N, V 120 120 FM27C040 QE, NE, VE 120 120
FM27C040 Q, N, V 150 150 FM27C040 QE, NE, VE 150 150

• All versions are guaranteed to function for slower speeds. Package Types: FM27C040 Q, N,V XXX
Q = Quartz-Windowed Ceramic DIP
Pin Names
N = Plastic DIP
A0–A18 Addresses
V = PLCC
CE/PGM Chip Enable/Program • All packages conform to the JEDEC standard.
OE Output Enable
O0–O7 Outputs
XX Don’t Care (During Read)

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FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1) All Output Voltages with
Respect to Ground VCC +1.0V to GND - 0.6V
Storage Temperature -65°C to +150°C
All Input Voltages except A9 with
Operating Range
Respect to Ground -0.6V to +7V
Range Temperature VCC Tolerance
VPP and A9 with Respect to Ground -0.6V to +14V
Commercial 0°C to +70°C +5V ±10%
VCC Supply Voltage with
Industrial -40°C to +85°C +5V ±10%
Respect to Ground -0.6V to +7V
ESD Protection >2000V

Read Operation
DC Electrical Characteristics Over operating range with VPP = VCC
Symbol Parameter Test Conditions Min Max Units
VIL Input Low Level -0.5 0.8 V
VIH Input High Level 2.0 VCC +1 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -2.5 mA 3.5 V
ISB1 VCC Standby Current (CMOS) CE = VCC ± 0.3V 100 µA
ISB2 VCC Standby Current CE = VIH 1 mA
ICC VCC Active Current CE = OE = VIL, f=5 MHz 30 mA
I/O = 0 mA
IPP VPP Supply Current VPP = VCC 10 µA
VPP VPP Read Voltage VCC - 0.4 VCC V
ILI Input Load Current VIN = 5.5V or GND -1 1 µA
ILO Output Leakage Current VOUT = 5.5V or GND -10 10 µA

AC Electrical Characteristics Over operating range with VPP = VCC

Symbol Parameter 120 150 Units
Min Max Min Max
tACC Address to Output Delay 120 150
tCE CE to Output Delay 120 150
tOE OE to Output Delay 50 50
tDF Output Disable to 45 55 ns
(Note 2) Output Float
tOH Output Hold from Addresses CE or OE , 0 0
(Note 2) Whichever Occurred First

Capacitance TA = +25°C, f = 1 MHz (Note 2)

Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN = 0V 9 15 pF
COUT Output Capacitance VOUT = 0V 12 15 pF

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FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs 0.8V and 2V
Outputs` 0.8V and 2V

AC Waveforms (Notes 6, 7, 9)

ADDRESSES 2V Addresses Valid

0.8V

2V
CE t CF
0.8V
(Note 4, 5)
t CE
2V
OE 0.8V
t DF
t OE
(Note 3) (Note 4, 5)
2V Hi-Z Hi-Z
OUTPUT Valid Output
0.8V
t ACC
t OH
(Note 3)
DS800033-4

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

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FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Programming Waveform (Note 13)
Program
Program Verify

2V
ADDRESSES 0.8V Address N

t AS t AH

2V Data In Stable Hi-Z Data Out Valid

DATA ADD N ADD N
0.8V

t DS t DH t DF

6.25V
VPP t VCS

12.75V
VCC t VPS

CE/PGM 2V
0.8V
t PW t OES t OE

OE 2V
0.8V
DS800033-5

Programming Characteristics (Notes 11, 12, 13, 14)

Symbol Parameter Conditions Min Typ Max Units
tAS Address Setup Time 1 µs
tOES OE Setup Time 1 µs
tDS Data Setup Time 1 µs
tVPS VPP Setup Time 1 µs
tVCS VCC Setup Time 1 µs
tAH Address Hold Time 0 µs
tDH Data Hold Time 1 µs
tDF Output Enable to Output Float Delay CE/PGM = X 0 60 ns
tPW Program Pulse Width 45 50 105 µs
tOE Data Valid from OE CE/PGM = X 100 ns
IPP VPP Supply Current during CE/PGM = VIL 30 mA
Programming Pulse
ICC VCC Supply Current 30 mA
TA Temperature Ambient 20 25 30 °C
VCC Power Supply Voltage 6.25 6.5 6.75 V
VPP Programming Supply Voltage 12.5 12.75 13.0 V
tFR Input Rise, Fall Time 5 ns
VIL Input Low Voltage -0.1 0.0 0.45 V
VIH Input High Voltage 2.4 4.0 V
tIN Input Timing Reference Voltage 0.8 2.0 V
tOUT Output Timing Reference Voltage 0.8 2.0 V

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the CE/PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.

5 www.fairchildsemi.com
FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION

PROGRAM ONE 50µs PULSE

INCREMENT n

NO

DEVICE YES
n = 10? FAIL VERIFY
FAILED BYTE

PASS

LAST INCREMENT
NO
ADDRESS ADDRESS
? n=0
YES

ADDRESS = FIRST LOCATION

VERIFY FAIL
BYTE

PASS PROGRAM ONE

INCREMENT
50 µs
ADDRESS
PULSE

NO
LAST
ADDRESS
?
YES

CHECK ALL BYTES

1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V
DS800033-6

Note: The standard National Semiconductor algorithm may also be used with it will have longer programming time.

FIGURE 1.

6 www.fairchildsemi.com
FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Functional Description supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
DEVICE OPERATION spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the data
The six modes of operation of the EPROM are listed in Table 1. It
output pins. The levels required for the address and data inputs
should be noted that all inputs for the six modes are at TTL levels.
are TTL.
The power supplies required are VCC and VPP. The VPP power
supply must be at 12.75V during the three programming modes, When the address and data are stable, an active low, TTL program
and must be at 5V in the other three modes. The VCC power supply pulse is applied to the CE/PGM input. A program pulse must be
must be at 6.25V during the three programming modes, and at 5V applied at each address location to be programmed. The EPROM
in the other three modes. is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
Read Mode pulses until it verifies good, up to a maximum of 10 pulses. Most
The EPROM has two control functions, both of which must be memory cells will program with a single 50 µs pulse. (The standard
logically active in order to obtain data at the outputs. Chip Enable National Semiconductor Algorithm may also be used but it will
(CE/PGM) is the power control and should be used for device have longer programming time.)
selection. Output Enable (OE) is the output control and should be
The EPROM must not be programmed with a DC signal applied to
used to gate data to the output pins, independent of device
the CE/PGM input.
selection. Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE). Data is Programming multiple EPROM in parallel with the same data can
available at the outputs tOE after the falling edge of OE, assuming be easily accomplished due to the simplicity of the pro-gramming
that CE/PGM has been low and addresses have been stable for requirements. Like inputs of the parallel EPROM may be con-
at least tACC -tOE. nected together when they are programmed with the same data.
A low level TTL pulse applied to the CE/PGM input programs the
Standby Mode paralleled EPROM.
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM
Program Inhibit
is placed in the standby mode by applying a CMOS high signal to Programming multiple EPROMs in parallel with different data is
the CE/PGM input. When in standby mode, the outputs are in a also easily accomplished. Except for CE/PGM all like in-puts
high impedance state, independent of the OE input. (including OE) of the parallel EPROMs may be com-mon. A TTL
low level program pulse applied to an EPROM’s CE/PGM input
Output Disable with VPP at 12.75V will program that EPROM. A TTL high level CE/
The EPROM is placed in output disable by applying a TTL high PGM input inhibits the other EPROMs from being programmed.
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRI-
Program Verify
STATE). A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
Output OR-Typing performed with VPP at 12.75V. VPP must be at VCC, except during
Because the EPROM is usually used in larger memory arrays, programming and program verify.
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple memory connections. The 2-line control
AFTER PROGRAMMING
function allows for: Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
1. the lowest possible memory power dissipation, and
prevent temporary functional failure due to the generation of photo
2. complete assurance that output bus contention will not occur. currents.
To most efficiently use these two control lines, it is recommended
that CE/PGM be decoded and used as the primary device select- MANUFACTURER’S IDENTIFICATION CODE
ing function, while OE be made a common connection to all The EPROM has a manufacturer’s identification code to aid in
devices in the array and connected to the READ line from the programming. When the device is inserted in an EPROM pro-
system control bus. This assures that all deselected memory grammer socket, the programmer reads the code and then
devices are in their low power standby modes and that the output automatically calls up the specific programming algorithm for the
pins are active only when data is desired from a particular memory part. This automatic programming control is only possible with
device. programmers which have the capability of reading the code.
Programming The Manufacturer’s Identification code, shown in Table 2, specifi-
cally identifies the manufacturer and device type. The code for
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM.
FM27C040 is “8F08”, where “8F” designates that it is made by
Initially, and after each erasure, all bits of the EPROM are in the Fairchild Semiconductor, and “08” designates a 4 Megabit (512K
“1’s” state. Data is introduced by selectively programming “0’s” x 8) part.
into the desired bit locations. Although only “0’s” will be pro-
The code is accessed by applying 12V ±0.5V to address pin A9.
grammed, both “1’s” and “0’s” can be presented in the data word.
Addresses A1–A8, A10–A18, and all control pins are held at VIL.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
Address pin A0 is held at VIL for the manufacturer’s code, and held
The EPROM is in the programming mode when the VPP power at VIH for the device code. The code is read on the eight data pins,
O0 –O7 . Proper code access is only guaranteed at 25°C ± 5°C.

7 www.fairchildsemi.com
FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Functional Description (Continued) be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Program-
ERASURE CHARACTERISTICS mers, components, and even system designs have been errone-
ously suspected when incomplete erasure was the problem.
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter SYSTEM CONSIDERATION
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths The power switching characteristics of EPROMs require careful
in the 3000Å–4000Å range. decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
The recommended erasure procedure for the EPROM is expo- current level, the active current level, and the transient current
sure to short wave ultraviolet light which has a wavelength of peaks that are produced by voltage transitions on input pins. The
2537Å. The integrated dose (i.e., UV intensity X exposure time) for magnitude of these transient current peaks is dependent of the
erasure should be minimum of 15W-sec/cm2. output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
The EPROM should be placed within 1 inch of the lamp tubes
decoupling capacitors. It is recommended that at least a 0.1 µF
during erasure. Some lamps have a filter on their tubes which
ceramic capacitor be used on every device between VCC and
should be removed before erasure.
GND. This should be a high frequency capacitor of low inherent
An erasure system should be calibrated periodically. The distance inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
from lamp to device should be maintained at one inch. The erasure should be used between VCC and GND for each eight devices. The
time increase as the square of the distance from the lamp. (If bulk capacitor should be located near where the power supply is
distance is doubled the erasure time increases by factor of 4.) connected to the array. The purpose of the bulk capacitor is to
Lamps lose intensity as they age. When a lamp is changed, the overcome the voltage drop caused by the inductive effects of the
distance has changed, or the lamp has aged, the system should PC board traces.

Mode Selection
The modes of operation of the FM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL
levels except for VPP and A9 for device signature.

TABLE 1. Modes Selection

Pins CE/PGM OE VPP VCC Outputs
Mode
Read VIL VIL X 5.0V DOUT
(Note 15)
Output Disable X VIH X 5.0V High Z
Standby VIH X X 5.0V High Z
Programming VIL VIH 12.75V 6.25V DIN
Program Verify X VIL 12.75V 6.25V DOUT
Program Inhibit VIH VIH 12.75V 6.25V High Z

Note 15: X can be VIL or VIH

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F
Device Code VIH 12V 0 0 0 0 1 0 0 0 08

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FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.660 MAX

32 17

R 0.025

0.585
MAX

1 16
UV WINDOW SIZE AND
R 0.030-0.055 CONFIGURATION DETERMINED
TYP BY DEVICE SIZE

0.050-0.060
TYP 0.10 0.590-0.620
0.005 MIN Glass Sealant MAX
TYP
0.175
0.225 MAX TYP MAX

0.125 MIN 0.015 -0.060

TYP 90° - 100°
TYP
TYP 0.008-0.012
86°-94°
TYP 0.150 MIN TYP
0.090-0.110 TYP
0.060-0.100 0.015-0.021 +0.025
TYP 0.685
TYP TYP -0.060

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number FM27C040QXXX
Package Number J32AQ

9 www.fairchildsemi.com
FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495
[12.32-12.57]
-H-
0.106-0.112 Base
0.007[0.18] S B D-E S [2.69-2.84] Plane

0.449-0.453 0.023-0.029
[11.40-11.51] [0.58-0.74] 0.015
-A- [0.38] Min Typ
0.045 0.007[0.18] S B D-E S
[1.143]

°
60
0.000-0.010 0.002[0.05] S B
[0.00-0.25] 0.490-0530
-D- 0.400
Polished Optional ( [10.16] ) [12.45-13.46]
4 1 30
0.541-0.545 0.015[0.38] S C D-E, F-G S
[13.74-13-84]
5 29

0.549-0.553
[13.94-14.05] -G-
-B-

0.585-0.595
[14.86-15.11] 0.013-0.021
TYP
-F- [0.33-0.53]
See detail A
-J- 0.007[0.18] M C D-E, F-G S
13
21
0.078-0.095
0.123-0.140 [1.98-2.41]
14 20 0.050

;;
[3.12-3.56]
-E- -C-
0.002[0.05] S A
0.004[0.10] 0.005 Max
0.007[0.18] S A F-G S
0.020 [0.13] 0.0100
0.007[0.18] S A F-G S [0.51] [0.254]

0.118-0.129
0.045
[3.00-3.28]
[1.14]
0.010[0.25] L B A D-E, F-G S 0.025 0.030-0.040
[0.64] Min
Detail A R
[0.76-1.02]
B 0.042-0.048 Typical
45°X [1.07-1.22] 0.025
0.021-0.027 Rotated 90°
[0.64]
[0.53-0.69]
Min

B
0.065-0.071
[1.65-1.80]

0.053-0.059
[1.65-1.80]

0.031-0.037
0.006-0.012 [0.79-0.94]
[0.15-0.30]
0.027-0.033
0.026-0.032 0.019-0.025 [0.69-0.84]
Typ
[0.66-0.81] [0.48-0.64]

0.007[0.18] S H D-E, F-G S Section B-B

Typical

32-Lead PLCC Package (V)

Order Number FM27C040VXXX
Package Number VA32A

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FM27C040 Rev. A
 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.64 – 1.66
(41.66 – 42.164)
32 17

0.062 TYP
(1.575)
RAD 0.490 – 0.550
(12.446 – 13.97)

1 16
Pin No. 1 IDENT

0.580
(14.73)
MIN 0.050
0.125 – 0.165
0.600 – 0.620 (1.270)
(3.175 – 4.191)
(15.240 – 15.748) TYP

0.145 – 0.210
(3.683 – 5.334)

86°- 94° 0.015

90°–105°
TYP (0.381)
0.008 - 0.015
(0.203 – 0.381) 0.040 - 0.090 0.120 – 0.150
0.018 ±0.003
(1.016 – 2.286) 0.100 ±0.010 (3.048 – 3.81)
(0.457 ±0.078)
(2.540 ±0.254)
0.035 – 0.07
(0.889 – 1.778)

32-Lead PDIP Package

Order Number FM27C040NXXX

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) support or system whose failure to perform can be reasonably ex-
or sustain life, and whose failure to perform, when properly pected to cause the failure of the life support device or system,
used in accordance with instructions for use provided in the or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant
injury to the user.

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FM27C040 Rev. A