Download Full Version ebook - Visit ebooknice.

com

(Ebook) RTL Modeling with SystemVerilog for

Simulation and Synthesis using SystemVerilog for
ASIC and FPGA design by Stuart Sutherland ISBN
9781546776345, 1546776346
https://ebooknice.com/product/rtl-modeling-with-
systemverilog-for-simulation-and-synthesis-using-
systemverilog-for-asic-and-fpga-design-10537592

Click the button below to download

DOWLOAD EBOOK

Discover More Ebook - Explore Now at ebooknice.com

 Instant digital products (PDF, ePub, MOBI) ready for you
Download now and discover formats that fit your needs...

Start reading on any device today!

(Ebook) ASIC and FPGA Verification: A Guide to Component

Modeling by Richard Munden ISBN 9780125105811, 0125105819

https://ebooknice.com/product/asic-and-fpga-verification-a-guide-to-
component-modeling-927438

ebooknice.com

(Ebook) Digital Design: With an Introduction to the

Verilog HDL, VHDL, and SystemVerilog by M. Morris R. Mano,
Michael D. Ciletti ISBN 9780134549897, 0134549899
https://ebooknice.com/product/digital-design-with-an-introduction-to-
the-verilog-hdl-vhdl-and-systemverilog-11743038

ebooknice.com

(Ebook) Advanced ASIC chip synthesis: using Synopsys

Design Compiler, Physical Compiler, and PrimeTime by
Himanshu Bhatnagar ISBN 9780792376446, 0792376447
https://ebooknice.com/product/advanced-asic-chip-synthesis-using-
synopsys-design-compiler-physical-compiler-and-primetime-1107740

ebooknice.com

(Ebook) PLD Based Design with VHDL: RTL Design, Synthesis

and Implementation by Vaibbhav Taraate (auth.) ISBN
9789811032943, 9789811032967, 9811032947, 9811032963
https://ebooknice.com/product/pld-based-design-with-vhdl-rtl-design-
synthesis-and-implementation-5741912

ebooknice.com
(Ebook) Digital Logic Design Using Verilog: Coding and RTL
Synthesis - 2nd Edition by Taraate, Vaibbhav ISBN
9789811631986, 9789811631993, 9789811632013, 9811631980
https://ebooknice.com/product/digital-logic-design-using-verilog-
coding-and-rtl-synthesis-2nd-edition-36019132

ebooknice.com

(Ebook) Digital Logic Design Using Verilog: Coding and RTL

Synthesis by Taraate, Vaibbhav ISBN 9789811631993,
9789811632013, 9789811631986, 9811631999, 9811632014,
9811631980
https://ebooknice.com/product/digital-logic-design-using-verilog-
coding-and-rtl-synthesis-36149158

ebooknice.com

(Ebook) Designing Digital Systems With SystemVerilog

(v2.1) by Brent E. Nelson ISBN 9788727537467,
9798727537466, 8727537463
https://ebooknice.com/product/designing-digital-systems-with-
systemverilog-v2-1-34395010

ebooknice.com

(Ebook) Introduction to Digital Systems: Modeling,

Synthesis, and Simulation Using VHDL by Mohammed
Ferdjallah ISBN 9780470900550, 0470900555
https://ebooknice.com/product/introduction-to-digital-systems-
modeling-synthesis-and-simulation-using-vhdl-55139888

ebooknice.com

(Ebook) RTL Hardware Design Using VHDL: Coding for

Efficiency, Portability, and Scalability by Chu, Pong P.
ISBN 9780471720928, 0471720925
https://ebooknice.com/product/rtl-hardware-design-using-vhdl-coding-
for-efficiency-portability-and-scalability-55138114

ebooknice.com
 RTL Modeling with

SystemVerilog
for Simulation and Synthesis
using SystemVerilog for ASIC and FPGA design

6/15/17
 Other books authored or co-authored by Stuart Sutherland:

Verilog and SystemVerilog Gotchas: 101 Common Coding Error and How to Avoid
Them
Common coding mistakes and guidelines on how to write correct code. Co­
authored with Don Mills.
System Verilog For Design: A Guide to Using System Verilog fo r Hardware Design
and Modeling, Second Edition
Describes what SystemVerilog-2005 added to the Verilog-2001 language for RTL
modeling. Assumes the reader is familiar with Verilog-2001. Written by Stuart
Sutherland, with advice and contributions from Simon Davidmann and Peter
Flake. Includes an appendix with a detailed history of Hardware Description
Languages by Peter Flake.
Verilog-2001: A Guide to the New Features in the Verilog Hardware Description
Language
Describes what Verilog-2001 added to the original Verilog-1995 language.
Assumes the reader is familiar with Verilog-1995.
The Verilog PLI Handbook: A Tutorial and Reference Manual on the Verilog Pro­
gramming Language Interface, Second Edition
A comprehensive reference and tutorial on Verilog-2001 PLI and VPI program­
ming interfaces into Verilog simulation.
Verilog HDL Quick Reference Guide, based on the Verilog-2001 Standard
A concise reference on the syntax of the complete Verilog-2001 language.
Verilog PLI Quick Reference Guide, based on the Verilog-2001 Standard
A concise reference on the Verilog-2001 Programming Language Interface, with
complete object relationship diagrams.
 RTL Modeling with

SystemVerilog
for Simulation and Synthesis
using SystemVerilog for ASIC and FPGA design

Stuart Sutherland

published by:
Sutherland HDL, Inc.
Tualatin, Oregon, USA
sutherland-hdl.com
printed by:
CreateSpace, An Amazon.com Company
eStore: www. Create Space, com/7164313
ISBN-13: 978-1-5467-7634-5
ISBN-10: 1-5467-7634-6
Copyright © 2017, Sutherland HDL, Inc.
All rights reserved. This work may not be translated, copied, or reproduced in whole
or in part without the express written permission of the copyright owner, except for
brief excerpts in connection with reviews or scholarly analysis. Use in connection
with any form of information storage and retrieval, electronic adaptation, computer
software, or by similar or dissimilar methodology now known or hereafter developed
is forbidden.
The use in this work of trade names, trademarks, service marks, and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as
to whether or not they are subject to proprietary rights.

Sutherland HDL, Inc.

22805 SW 92nd Place
Tualatin, OR 97062-7225
E-mail: [email protected]
Phone: +1-503-692-0898
URL: sutherland-hdl.com
 V

Dedication

To my wonderful wife, LeeAnn, and my children, Ammon, Tamara, Hannah, Seth and
Samuel, and each o f their families — Families are forever!
Stuart Sutherland
Portland, Oregon, USA
 VII

About the Author

Stuart Sutherland provides expert instruction on using SystemVerilog and Ver-

ilog. He has been involved in defining the Verilog and SystemVerilog languages since
the beginning of IEEE standardization work in 1993, and is a member of the IEEE
SystemVerilog standards committee, where he has served as one of the technical edi­
tors for every version of the IEEE Verilog and SystemVerilog Language Reference
Manuals (LRMs). Stuart has more than 25 years of experience with Verilog and Sys­
temVerilog, and has authored and co-authored numerous papers on these languages
(available at www.sutherland-hdl.com). He has also authored “The Verilog PLIHand­
book”, “Verilog-2001: A Guide to the New Features o f the Verilog HDL, and “System­
Verilog fo r Design: A Guide to Using the SystemVerilog Enhancements to Verilog fo r
Hardware Design” (co-authored with Simon Davidmann and Peter Flake), and " Ver­
ilog and SystemVerilog Gotchas: 101 Common Coding Error and How to Avoid
Them" (co-authored with Don Mills) ”
Stuart is the founder of Sutherland HDL, Inc., which specializes in providing expert
SystemVerilog training and consulting services. He holds a Bachelor’s Degree in
Computer Science with an emphasis in Electronic Engineering Technology (Weber
State University (Ogden, Utah and Franklin Pierce College, Nashua, New Hampshire)
and a Master’s Degree in Education with an emphasis on eLearning course develop­
ment (Northcentral University, Prescott, Arizona).
 IX

Table of Contents

Table of Contents........................................................................................................... ix

List of Examples.......................................................................................................... xvii

List of Figures................................................................................................................xxi

Foreword....................................................................................................................... xxv

Preface......................................................................................................................... xxvii
Why this book........................................................................................................................xxvii
Intended audience for this book............................................................................................xxviii
Topics covered in this book..................................................................................................xxviii
Book examples........................................................................................................................ xxix
Obtaining copies of the examples............................................................................................ xxx
Simulators and synthesis compilers used in this book.............................................................xxx
Other sources of information.................................................................................................. xxxi
Acknowledgements................................................................................................................. xxxi

Chapter 1: SystemVerilog Simulation and Synthesis...............................................1

1.1 Verilog and SystemVerilog — a brief history.................................................................. 1
1.1.1 The Original Verilog............................................................................................ 2
1.1.2 Open Verilog and VHDL..................................................................................... 3
1.1.3 IEEE Verilog-95 and Verilog-2001..................................................................... 3
1.1.4 SystemVerilog extensions to Verilog — a separate standard..............................4
1.1.5 SystemVerilog replaces Verilog.......................................................................... 5
1.2 RTL and gate-level modeling........................................................................................... 6
1.2.1 Abstraction........................................................................................................... 6
1.2.2 Gate-level models................................................................................................. 7
1.2.3 RTL models........................................................................................................10
1.2.4 Behavioral and transaction-level models.............................................................11
1.3 Defining an RTL synthesis subset of SystemVerilog .................................................... 12
1.4 Modeling for ASICs and FPGAs.................................................................................... 12
1.4.1 Standard cell ASICs........................................................................................... 12
1.4.2 FPGAs.................................................................................................................15
1.4.3 RTL coding styles for ASICs and FPGAs...........................................................16
1.5 SystemVerilog simulation ...............................................................................................17
1.5.1 SystemVerilog simulators.................................................................................. 21
1.5.2 Compilation and elaboration............................................................................... 21
1.5.3 Simulation time and event scheduling................................................................ 23
X RTL Modeling with SystemVerilog for Simulation and Synthesis

1.6 Digital synthesis ............................................................................................................. 31

1.6.1 SystemVerilog synthesis compilers................................................................... 32
1.6.2 Synthesis Compilation....................................................................................... 33
1.6.3 Constraints......................................................................................................... 34
1.7 SystemVerilog lint checkers........................................................................................... 35
1.8 Logic Equivalence Checkers .......................................................................................... 36
1.9 Summary ........................................................................................................................ 37

Chapter 2: RTL Modeling Fundamentals................................................................39

2.1 Modules and procedural blocks.......................................................................................39
2.2 SystemVerilog language rules........................................................................................40
2.2.1 Comments.......................................................................................................... 40
2.2.2 White space........................................................................................................ 43
2.2.3 Reserved keywords............................................................................................ 44
2.2.4 Keyword backward compatibility — ‘begin_keywords....................................46
2.2.5 Identifiers (user-defined names)........................................................................ 49
2.2.6 Naming conventions and guidelines.................................................................. 50
2.2.7 System tasks and functions................................................................................ 51
2.2.8 Compiler directives............................................................................................ 52
2.3 M odules.......................................................................................................................... 52
2.4 Modules instances and hierarchy ................................................................................... 54
2.4.1 Port order connections....................................................................................... 55
2.4.2 Named port connections.................................................................................... 56
2.4.3 The dot-name inferred named port connection shortcut....................................57
2.4.4 The dot-star inferred named port connection shortcut.......................................58
2.5 Summary ........................................................................................................................ 59

Chapter 3: Net and Variable types........................................................................... 61

3.1 Four-state data values..................................................................................................... 61
3.2 Literal values (numbers)................................................................................................. 62
3.2.1 Literal integer values......................................................................................... 62
3.2.2 Vector fill literal values..................................................................................... 65
3.2.3 Floating-point literal values (real numbers)....................................................... 66
3.3 Types and data types ...................................................................................................... 66
3.3.1 Net types and variable types.............................................................................. 66
3.3.2 Two-state and four-state data types (bit and logic)............................................67
3.4 Variable types................................................................................................................. 67
3.4.1 Synthesizable variable data types.......................................................................67
3.4.2 Variable declaration rules.................................................................................. 70
3.4.3 Variable assignment rules.................................................................................. 74
3.4.4 Uninitialized variables....................................................................................... 74
3.4.5 In-line variable initialization.............................................................................. 75
3.5 Net types......................................................................................................................... 76
3.5.1 Synthesizable net types...................................................................................... 77
3.5.2 Net declaration rules.......................................................................................... 79
Table of Contents XI

3.5.3 Implicit net declarations..................................................................................... 80

3.5.4 Net assignment and connection rules................................................................. 83
3.6 Port declarations ............................................................................................................. 84
3.6.1 Synthesizable port declarations.......................................................................... 84
3.6.2 Non synthesizable port declarations.................................................................. 87
3.6.3 Module port declaration recommendations....................................................... 88
3.7 Unpacked arrays of nets and variables ........................................................................... 89
3.7.1 Accessing array elements................................................................................... 90
3.7.2 Copying arrays................................................................................................... 91
3.7.3 Array list assignments........................................................................................ 91
3.7.4 Bit-select and part-select of array elements.......................................................92
3.8 Parameter constants........................................................................................................ 93
3.8.1 Parameter dec larations....................................................................................... 94
3.8.2 Parameter overrides (parameter redefinition)....................................................97
3.9 Const variables ............................................................................................................... 99
3.10 Summary ........................................................................................................................ 99

Chapter 4: User-defined Types and Packages....................................................... 101

4.1 User-defined types......................................................................................................... 101
4.1.1 Naming conventions for user-defined types.................................................... 102
4.1.2 Local typedef definitions...................................................................................102
4.1.3 Shared typedef definitions............................................................................... 102
4.2 SystemVerilog packages ...............................................................................................102
4.2.1 Package declarations.........................................................................................103
4.2.2 Using package items.........................................................................................104
4.2.3 Importing from multiple packages................................................................... 108
4.2.4 Package chaining..............................................................................................109
4.2.5 Package compilation order............................................................................... 110
4.2.6 Synthesis considerations...................................................................................111
4.3 The $unit declaration space.......................................................................................... 112
4.4 Enumerated types ..........................................................................................................114
4.4.1 Enumerated type declaration syntax................................................................. 114
4.4.2 Importing enumerated types from packages.................................................... 117
4.4.3 Enumerated type assignment rules.................................................................. 118
4.4.4 Enumerated type methods................................................................................ 121
4.4.5 Traditional Verilog coding style without enumerated types............................ 124
4.5 Structures.......................................................................................................................124
4.5.1 Structure declarations...................................................................................... 124
4.5.2 Assigning to structure members...................................................................... 125
4.5.3 Assigning to entire structures...........................................................................125
4.5.4 Typed and anonymous structures.................................................................... 126
4.5.5 Copying structures............................................................................................127
4.5.6 Packed and unpacked structures...................................................................... 127
4.5.7 Passing structuresthrough ports and to tasks and functions............................. 129
4.5.8 Traditional Verilog versus structures............................................................... 130
 ■■
XII RTL Modeling with SystemVerilog for Simulation and Synthesis

4.5.9 Synthesis considerations..................................................................................130

4.6 Unions ...........................................................................................................................131
4.6.1 Typed and anonymous unions.........................................................................131
4.6.2 Assigning to, and reading from, union variables............................................. 132
4.6.3 Unpacked, packed and tagged unions.............................................................. 132
4.6.4 Passing unions through ports and to tasks and functions................................. 134
4.7 Using arrays with structures and unions........................................................................136
4.8 Summary .......................................................................................................................139

Chapter 5: RTL Expression Operators.................................................................141

5.1 Operator expression ru les..............................................................................................141
5.1.1 4-state and 2-state operations............................................................................142
5.1.2 X-optimism and X-pessimism........................................................................ 142
5.1.3 Expression vector sizes and automatic vector extension................................. 144
5.1.4 Signed and unsigned expressions.................................................................... 145
5.1.5 Integer (vector) and real (floating-point) expressions..................................... 145
5.2 Concatenate and replicate operators..............................................................................146
5.3 Conditional (ternary) operator.......................................................................................150
5.4 Bitwise operators...........................................................................................................153
5.5 Reduction operators.......................................................................................................158
5.6 Logical operators...........................................................................................................160
5.6.1 Difference between negate and invert operations............................................ 161
5.6.2 Short circuiting logical operations................................................................... 163
5.6.3 Non-synthesizable logical operators................................................................ 164
5.7 Comparison operators (equality and relational) ........................................................... 164
5.8 Case equality (identity) operators..................................................................................168
5.9 Set membership (inside) operator................................................................................ 171
5.10 Shift operators ...............................................................................................................173
5.10.1 Synthesizing shift operations............................................................................174
5.10.2 Synthesizing rotate operations........................................................................ 177
5.11 Streaming operators (pack and unpack) ........................................................................181
5.12 Arithmetic operators......................................................................................................184
5.12.1 Integer and floating-point arithmetic............................................................... 186
5.12.2 Unsigned and signed arithmetic might synthesize to the same gates.............. 188
5.13 Increment and decrement operators ..............................................................................189
5.13.1 Proper usage of increment and decrement operators....................................... 190
5.13.2 An example of correct usage of increment and decrement operators.............. 192
5.13.3 Compound operations with increment and decrement operators..................... 194
5.13.4 An anecdotal story on the increment and decrement operators...................... 195
5.14 Assignment operators ....................................................................................................196
5.15 Cast operators and type conversions ............................................................................198
5.15.1 Typecasting..................................................................................................... 200
5.15.2 Size casting...................................................................................................... 202
5.15.3 Signedness casting........................................................................................... 206
Table of Contents XIII

5.16 Operator precedence..................................................................................................... 209

5.17 Summary ...................................................................................................................... 210

Chapter 6: RTL Programming Statements...........................................................211

6.1 SystemVerilog procedural blocks.................................................................................. 211
6.1.1 Sensitivity lists................................................................................................. 212
6.1.2 Begin-end statement groups.............................................................................. 214
6.1.3 Using variables and nets in procedural blocks..................................................216
6.2 Decision statements...................................................................................................... 216
6.2.1 if-else statements.............................................................................................. 216
6.2.2 Case statements................................................................................................ 222
6.2.3 Unique and priority decision modifiers...........................................................227
6.3 Looping statements....................................................................................................... 228
6.3.1 For loops.......................................................................................................... 228
6.3.2 Repeat loops..................................................................................................... 233
6.3.3 While and do-while loops................................................................................ 235
6.3.4 Foreach loops and looping through arrays.......................................................236
6.4 Jump statements ........................................................................................................... 238
6.4.1 The continue and break jump statements.........................................................239
6.4.2 The disable jump statement............................................................................. 240
6.5 No-op statement ........................................................................................................... 241
6.6 Functions and tasks in RTL modeling.......................................................................... 243
6.6.1 Functions.......................................................................................................... 243
6.6.2 Tasks................................................................................................................ 248
6.7 Summary ...................................................................................................................... 249

Chapter 7: Modeling Combinational Logic...........................................................251

7.1 Continuous assignments (Boolean expressions) .......................................................... 252
7.1.1 Explicit and inferred continuous assignments.................................................254
7.1.2 Multiple continuous assignments...................................................................... 254
7.1.3 Using both continuous assignments and always procedures............................255
7.2 The always and always_comb procedures ................................................................... 256
7.2.1 Synthesizing combinational logic always procedures.....................................257
7.2.2 Modeling with the general purpose always procedure....................................257
7.2.3 Modeling with the RTL-specific always_comb procedure..............................260
7.2.4 Using blocking (combinational logic) assignments.........................................261
7.2.5 Avoiding unintentional latches in combinational logic procedures.................262
7.3 Using functions to represent combinational logic........................................................ 263
7.4 Combinational logic decision priority.......................................................................... 265
7.4.1 Removing unnecessary priority encoding from case decisions........................266
7.4.2 The unique and uniqueO decision modifiers....................................................266
7.4.3 The obsolete parallel_case synthesis pragma..................................................270
7.5 Summary ...................................................................................................................... 271
xiv RTL Modeling with SystemVerilog for Simulation and Synthesis

Chapter 8: Modeling Sequential Logic................................................................... 273

8.1 RTL models of flip-flops and registers ........................................................................ 274
8.1.1 Synthesis requirements for RTL sequential logic............................................274
8.1.2 Always procedures and always_ff procedures.................................................. 275
8.1.3 Sequential logic clock-to-Q propagation and setup/hold times........................276
8.1.4 Using nonblocking (sequential logic) assignments..........................................278
8.1.5 Synchronous and asynchronous resets............................................................. 286
8.1.6 Multiple clocks and clock domain crossing (CDC)..........................................295
8.1.7 Additional RTL sequential logic modeling considerations..............................297
8.2 Modeling Finite State Machines (FSMs) ..................................................................... 299
8.2.1 Mealy and Moore FSM architectures............................................................... 301
8.2.2 State encoding.................................................................................................. 302
8.2.3 One, two and three-procedure FSM coding styles........................................... 305
8.2.4 A complete FSM example............................................................................... 309
8.2.5 Reverse case statement one-hot decoder......................................................... 313
8.2.6 Avoiding latches in state machine decoders.................................................... 317
8.3 Modeling memory devices such as RAM s................................................................... 317
8.3.1 Modeling asynchronous and synchronous memory devices............................319
8.3.2 Loading memory models using Sreadmemb and Sreadmemh.........................320
8.4 Summary ...................................................................................................................... 322

Chapter 9: Modeling Latches and Avoiding Unintentional Latches.................323

9.1 Modeling Latches ......................................................................................................... 323
9.1.1 Modeling latches with the general purpose always procedure........................324
9.1.2 Modeling latches with the always_latch procedure.........................................325
9.2 Unintentional latch inference ....................................................................................... 327
9.3 Avoiding latches in intentionally incomplete decisions............................................... 329
9.3.1 Latch avoidance coding style trade-offs.......................................................... 330
9.3.2 A small example to illustrate avoiding unintentional latches..........................332
9.3.3 Latch avoidance style 1 — Default case item with known values..................335
9.3.4 Latch avoidance style 2—Pre-case assignment, known values.......................338
9.3.5 Latch avoidance style 3 — unique and priority decision modifiers................340
9.3.6 Latch avoidance style 4 — X assignments for unused decision values...........345
9.3.7 Latch avoidance style 5 — the full_case synthesis pragma.............................350
9.3.8 Additional notes about synthesis pragmas....................................................... 351
9.4 Summary ...................................................................................................................... 353

Chapter 10: Modeling Communication Buses — Interface Ports................... 355

10.1 Interface port concepts ................................................................................................. 356
10.1.1 Traditional Verilog bus connections................................................................ 357
10.1.2 SystemVerilog interface definitions................................................................ 361
10.1.3 Referencing signals within an interface........................................................... 365
10.1.4 Differences between modules and interfaces.................................................... 365
10.1.5 Source code declaration order.......................................................................... 366
10.2 Using interfaces as module ports.................................................................................. 366
Table of Contents xv

10.2.1 Generic interface ports..................................................................................... 366

10.2.2 Type-specific interface ports........................................................................... 367
10.3 Interface modports........................................................................................................ 367
10.3.1 Specifying which modport view to use........................................................... 368
10.3.2 Using modports to define different sets of connections..................................371
10.4 Interface methods (tasks and functions)....................................................................... 372
10.4.1 Calling methods defined in an interface.......................................................... 374
10.4.2 Synthesizing interface methods....................................................................... 375
10.4.3 Abstract, non-synthesizable interface methods............................................... 375
10.5 Interface procedural code ............................................................................................. 376
10.6 Parameterized interfaces............................................................................................... 378
10.7 Synthesizing interfaces................................................................................................. 379
10.8 Summary ...................................................................................................................... 382

List of Appendices...................................................................................................... 383

Appendix A: Best Practice Coding Guidelines....................................................385

Appendix B: SystemVerilog Reserved Keywords...............................................391

B.l All SystemVerilog-2012 reserved keywords............................................................... 391
B.2 Verilog-1995 reserved keywords ................................................................................ 393
B.3 Verilog-2001 reserved keywords ................................................................................ 394
B.4 Verilog-2005 reserved keywords ................................................................................ 394
B.5 SystemVerilog-2005 reserved keywords......................................................................395
B.6 SystemVerilog-2009 reserved keywords......................................................................396
B.7 SystemVerilog-2012 reserved keywords......................................................................396
B. 8 SystemVerilog-2017 reserved keywords......................................................................396

Appendix C: X Optimism and X Pessimism in RTL Models............................397

C. 1 Introducing My X .........................................................................................................398
C.2 How did my one (or zero) become my X? ...................................................................399
C.2.1 Uninitialized 4-state variables........................................................................ 399
C.2.2 Uninitialized registers and latches.................................................................. 400
C.2.3 Low power logic shutdown or power-up........................................................ 401
C.2.4 Unconnected module input ports.................................................................... 401
C.2.5 Multi-driver Conflicts (Bus Contention)........................................................ 401
C.2.6 Operations with an unknown result................................................................ 401
C.2.7 Out-of-range bit-selects and array indices...................................................... 401
C.2.8 Logic gates with unknown output values....................................................... 402
C.2.9 Setup or hold timing violations....................................................................... 402
C.2.10 User-assigned X values in hardware models...................................................402
C.2.11 Testbench X injection..................................................................................... 403
xvi RTL Modeling with SystemVerilog for Simulation and Synthesis

C.3 An optimistic X — is that good or bad?......................................................................403

C.3.1 If...else statements........................................................................................... 404
C.3.2 Case statements without a default-X assignment........................................... 407
C.3.3 Casex, casez and case...inside statements....................................................... 408
C.3.4 Bitwise, unary reduction, and logical operators............................................. 411
C.3.5 And, nand, or, nor, logic primitives................................................................ 412
C.3.6 User-defined primitives.................................................................................. 412
C.3.7 Array index with X or Z bits for write operations..........................................412
C.3.8 Net data types.................................................................................................. 413
C.3.9 Posedge and negedge edge sensitivity............................................................ 414
C.4 A pessimistic X — is that any better? .........................................................................415
C.4.1 If...else statements with X assignments.......................................................... 416
C.4.2 Conditional operator....................................................................................... 417
C.4.3 Case statements with X assignments.............................................................. 419
C.4.4 Edge-sensitive X pessimism........................................................................... 420
C.4.5 Bitwise, unary reduction, and logical operators............................................. 420
C.4.6 Equality, relational, and arithmetic operators................................................. 421
C.4.7 User-defined primitives.................................................................................. 422
C.4.8 Bit-select, part-select, array index on right-hand side of assignments...........423
C.4.9 Shift operations............................................................................................... 423
C.4.10 X-pessimism summary................................................................................... 424
C.5 Eliminating my X by using 2-state simulation............................................................424
C.6 Eliminating some of my X with 2-state data types .....................................................426
C.7 Breaking the rules—simulator-specific X-propagation options..................................428
C.8 Changing the rules — A SystemVerilog enhancement wish list ................................429
C.9 Detecting and stopping my X at the door....................................................................430
C. 10 Minimizing problems with my X ................................................................................ 432
C. 10.1 2-state versus 4-state guidelines..................................................................... 432
C.10.2 Register initialization guidelines.................................................................... 433
C.10.3 X-assignment guidelines................................................................................. 433
C.10.4 Trapping X guidelines.................................................................................... 433
C .ll Conclusions ................................................................................................................. 434
C. 11.1 About the author............................................................................................. 435
C.12 Acknowledgments ....................................................................................................... 435
C.13 References ................................................................................................................... 436

Appendix D: Additional Resources........................................................................437

Index 441
 XVII

List of Examples

This book contains a number o f examples that illustrate the proper usage o f System-
Verilog constructs. A summary o f the major code examples is listed in this section. In
addition to these examples, each chapter contains many code fragments, referred to as
snippets, that illustrate specific features o f SystemVerilog. The source code for the
full examples can be downloaded from http://www.sutherland-hdl.com. Navigate the
menus to “SystemVerilog Book Examples

The Preface provides more details regarding the code examples in this book.

Chapter 1: SystemVerilog Simulation and Synthesis

Example 1-1: SystemVerilog gate-level model of 1-bit adder with carry............................... 8
Example 1-2: SystemVerilog RTL model of 1-bit adder with carry......................................10
Example 1-3: SystemVerilog RTL model of 32-bit adder/subtractor....................................11
Example 1-4: Design model with input and output ports (a 32-bit adder/subtractor)............18
Example 1-5: Testbench for the 32-bit adder/subtractor model.............................................18
Example 1-6: Top-level module connecting the testbench to the design.............................. 20
Example 1-7: A clock oscillator, stimulus and flip flop to illustrate event scheduling........ 29

Chapter 2: RTL Modeling Fundamentals

Example 2-1: RTL model showing two styles of comments................................................. 41
Example 2-2: SystemVerilog RTL model with minimum white space................................. 44
Example 2-3: SystemVerilog RTL model with good use of white space.............................. 44
Example 2-4: Using 'begin_keywords with a legacy Verilog-2001 model.................. 47
Example 2-5: Using 'begin_keywords with a SystemVerilog-2012 model.................. 48

Chapter 3: Net and Variable types

Example 3-1: Example of undeclared identifiers creating implicit nets................................ 80
Example 3-2: Changing the net type for implicit nets............................................................81
Example 3-3: Module port declaration using recommended coding guidelines.................... 89
Example 3-4: Add module with parameterized port widths.................................................. 94
Example 3-5: Model of a configurable RAM using a module parameter list........................ 96
Example 3-6: Adder with configurable data types................................................................ 97

Chapter 4: User-defined Types and Packages

Example 4-1: A package definition with several package items..........................................103
Example 4-2: Using a package wildcard import...................................................................105
Example 4-3: Importing specific package items into a module............................................106
Example 4-4: Explicit package references using the :: scope resolution operator...............107
Example 4-5: Using enumerated type methods for a state machine sequencer....................123
Example 4-6: Package containing structure and union definitions.......................................134
xviii RTL Modeling with SystemVerilog for Simulation and Synthesis

Example 4-7: Arithmetic Logical Unit (ALU) with structure and union ports................... 135
Example 4-8: Using arrays of structures to model an instruction register........................... 137

Chapter 5: RTL Expression Operators

Example 5-1: Using concatenate operators: multiple input status register............................147
Example 5-2: Using concatenate operators: adder with a carry b it....................................... 149
Example 5-3: Using theconditional operator: multiplexed 4-bit register D input............... 151
Example 5-4: Using theconditional operator: 4-bit adder with tri-state outputs................. 152
Example 5-5: Using bitwise operators: multiplexed N-bit wide AND/XOR operation.....156
Example 5-6: Using reduction operators: parity checker using XOR................................. 159
Example 5-7: Using logical operators: set flag when values are within a range................. 163
Example 5-8: Using comparison operators: a relationship comparator............................... 167
Example 5-9: Using case equality operators: a comparator for high address range............ 170
Example 5-10: Using theset membership operator: a decoder for specific addresses........... 172
Example 5-11: Using theshift operator: divide-by-two by shifting right one b it.................. 175
Example 5-12: Using theshift operator: multiply by a power of two by shifting left............ 176
Example 5-13: Performing a rotate operation using concatenate and shift operators........... 179
Example 5-14: Using the streaming operator: reverse bits of a parameterized vector.......... 183
Example 5-15: Using arithmetic operators with unsigned data types................................... 186
Example 5-16: Using arithmetic operators with signed data types....................................... 187
Example 5-17: Using arithmetic operators with real data types............................................ 187
Example 5-18: Using increment and decrement operators.................................................... 192
Example 5-19: Using assignment operators.......................................................................... 197
Example 5-20: Using size casting..........................................................................................205
Example 5-21: Using sign casting for a mixed signed and unsigned comparator.................207

Chapter 6: RTL Programming Statements

Example 6-1: Using if-else to model multiplexor functionality................................... 219
Example 6-2: Using if without else to model latch functionality................................... 220
Example 6-3: Using an if-else-if series to model a priority encoder.................................... 220
Example 6-4: Using if-else-if series to model a flip-flop with reset and chip-enable........ 221
Example 6-5: Using a case statement to model a 4-to-l MUX.........................................225
Example 6-6: Using an case-inside to model a priority encoder.........................................226
Example 6-7: Using a for loop to operate on bits of vectors...............................................229
Example 6-8: Using a for loop to find the lowest bit that is set in avector........................ 231
Example 6-9: Using a repeat loop to raise a value to the power of an exponent................ 234
Example 6-10: Controlling for loop execution using continue and break..........................239

Chapter 7: Modeling Combinational Logic

Example 7-1: Add, multiply, subtract dataflow processing with registered output........... 255
Example 7-2: Function that defines an algorithmic multiply operation..............................264
Example 7-3: State decoder with inferred priority encoded logic (partial code).................267
Example 7-4: State decoder with unique parallel encoded logic (partial code)..................268
List of Examples xix

Chapter 8: Modeling Sequential Logic

Example 8-1: RTL model of a 4-bit Johnson counter..........................................................279
Example 8-2: 4-bit Johnson counter incorrectly modeled with blocking assignments......282
Example 8-3: RTL model of an 8-bit serial-to-parallel finite state machine.......................310

Chapter 9: Modeling Latches and Avoiding Unintentional Latches

Example 9-1: Using intentional latches for a cycle-stealing pipeline..................................326
Example 9-2: Simple round-robin state machine that will infer latches..............................334

Chapter 10: Modeling Communication Buses — Interface Ports

Example 10-1: Master and slave module connections using separate ports..........................358
Example 10-2: An interface definition for the 8-signal simple AMBA AHB bus............... 362
Example 10-3: Master and slave modules with interface ports.............................................363
Example 10-4: Netlist connecting the master and slave interface ports............................... 364
Example 10-5: Interface with modports for custom views of interface signals....................371
Example 10-6: Interface with internal methods (functions) for parity logic.........................373
Example 10-7: Interface with internal procedural code to generate bus functionality..........376
Example 10-8: Parameterized interface with configurable bus data word size.....................378
 xxi

List of Figures

Chapter 1: SystemVerilog Simulation and Synthesis

Figure 1-1: Verilog-95 and Verilog-2001 language features................................................... 4
Figure 1-2: Verilog-2005 with SystemVerilog language extensions....................................... 5
Figure 1-3: SystemVerilog modeling abstraction levels ..........................................................7
Figure 1-4: 1-bit adder with carry, represented with logic gates ............................................. 8
Figure 1-5: Typical RTL-based ASIC design flow ................................................................ 13
Figure 1-6: Typical RTL-based FPGA design flow ............................................................... 16
Figure 1-7: Simulation time line and time slots .....................................................................26
Figure 1-8: Simplified SystemVerilog event scheduling flow .............................................. 28
Figure 1-9: Simulation time line and time slots with some events scheduled ........................30
Figure 1-10: SystemVerilog synthesis tool flow ......................................................................31
Figure 1-11: Diagram of a simple circuit requiring synthesis constraints .............................. 34

Chapter 2: RTL Modeling Fundamentals

Figure 2-1: SystemVerilog module contents ..........................................................................53
Figure 2-2: Design partitioning using sub blocks ..................................................................54

Chapter 3: Net and Variable types

Figure 3-1: Vectors with subfields ........................................................................................73

Chapter 4: User-defined Types and Packages

Figure 4-1: State diagram for a confidence counter state machine ......................................122
Figure 4-2: Packed structures are stored as a vector ............................................................ 128
Figure 4-3: Packed union with two representations of the same storage..............................133
Figure 4-4: Synthesis result for Example 4-7: ALU with structure and union ports ............136
Figure 4-5: Synthesis result for Example 4-8: instruction register with structures ..............138

Chapter 5: RTL Expression Operators

Figure 5-1: Synthesis result for Example 5-1: Concatenate operator (status register) ........148
Figure 5-2: Synthesis result for Example 5-2: Add operator (adder with carry in/out)........149
Figure 5-3: Synthesis result for Example 5-3: Conditional operator (mux’ed register) .......151
Figure 5-4: Synthesis result for Example 5-4: Conditional operator (tri-state output).........152
Figure 5-5: Synthesis result for Example 5-5: Bitwise AND and OR operations ................157
Figure 5-6: Synthesis result for Example 5-6: Reduction XOR (parity checker) ................159
Figure 5-7: Synthesis result for Example 5-7: Logical operators (in-range compare) .........163
Figure 5-8: Synthesis result for Example 5-8: Relational operators (comparator) ..............168
Figure 5-9: Synthesis result for Example 5-9: Case equality, ==? (comparator) ................170
Figure 5-10: Synthesis result for Example 5-10: Inside operator (boundary detector)......... 172
Figure 5-11: Bitwise and arithmetic shift operations ........................................................... 174
Figure 5-12: Synthesis result for Example 5-11: Shift operator, right-shift by 1 b i t ............ 175
Figure 5-13: Synthesis result for Example 5-12: Shift operator, variable left shifts ........... 176
Figure 5-14: Rotate a variable number of times using concatenate and shift operators .......178
Figure 5-15: Synthesis result for Example 5-13: Concatenate and shift (rotate) .................179
xxii RTL Modeling with SystemVerilog for Simulation and Synthesis

Figure 5-16: Synthesis result for Example 5-14: Streaming operator (bit reversal) ............ 183
Figure 5-17: Synthesis result for Example 5-15: Arithmetic operation, unsigned .............. 187
Figure 5-18: Synthesis result for Example 5-16: Arithmetic operation, signed .................. 187
Figure 5-19: Synthesis result for Example 5-18: Increment and decrement operators......... 193
Figure 5-20: Synthesis result after mapping to a Xilinx Virtex®-7 FPG A ........................... 193
Figure 5-21: Synthesis result after mapping to a Xilinx CoolRunner™-II CPLD ............... 194
Figure 5-22: Synthesis result for Example 5-19: Assignment operators .............................. 197
Figure 5-23: Synthesis result for Example 5-20: Size casting ............................................. 205
Figure 5-24: Synthesis result for Example 5-21: Sign casting ............................................. 208

Chapter 6: RTL Programming Statements

Figure 6-1: Synthesis result for Example 6-1: if-else as a M U X ..........................................219
Figure 6-2: Synthesis result for Example 6-2: if-else as a latch ..........................................220
Figure 6-3: Synthesis result for Example 6-3: if-else as a priority encoder ........................221
Figure 6-4: Synthesis result for Example 6-4: if-else as a chip-enable flip-flop .................222
Figure 6-5: Synthesis result for Example 6-5: case statement as a 4-to-l M U X ..................226
Figure 6-6: Synthesis result for Example 6-6: case...inside as a priority encoder ...............227
Figure 6-7: Synthesis result for Example 6-7: for-loop to operate on vector bits ...............230
Figure 6-8: Synthesis result for Example 6-8: for-loop to find lowest bit set .....................232
Figure 6-9: Synthesis result for Example 6-9: repeat loop to raise to an exponent ..............234
Figure 6-10: Synthesis result for Example 6-10 .................................................................. 240

Chapter 7: Modeling Combinational Logic

Figure 7-1: Synthesis result for Example 7-1: Continuous assignment as comb, logic .......255
Figure 7-2: Synthesis result for Example 7-2: Function as combinational logic .................264
Figure 7-3: Synthesis result for Example 7-3: Reverse case statement with priority...........267
Figure 7-4: Synthesis result for Example 7-4: Reverse case statement, using unique .........268

Chapter 8: Modeling Sequential Logic

Figure 8-1: 4-bit Johnson counter diagram ........................................................................ 277
Figure 8-2: Simplified SystemVerilog event scheduling flow ........................................... 279
Figure 8-3: Synthesis result for Example 8-1: Nonblocking assignments, J-Counter..........280
Figure 8-4: Synthesis result for Example 8-2: Blocking assignments, bad J-Counter .........283
Figure 8-5: Blocking assignment to intermediate temporary variable ...............................284
Figure 8-6: Nonblocking assignment to intermediate temporary variable .......................284
Figure 8-7: Synthesis result: Async reset DFF mapped to Xilinx Virtex®-6 FPGA ..........288
Figure 8-8: Synthesis result: Async reset mapped to Xilinx CoolRunner™-II CPLD .......288
Figure 8-9: Waveform showing result of incorrectly modeled asynchronous reset ...........289
Figure 8-10: Synthesis result for a chip-enable flip-flop ..................................................... 290
Figure 8-11: External logic to create the functionality of a chip-enable flip-flop ...............290
Figure 8-12: Synthesis result for an asynchronous set-reset flip-flop .................................293
Figure 8-13: Two flip-flop clock synchronizer for 1-bit control signals .............................296
Figure 8-14: An 8-bit serial value of hex CA, plus a start bit ..............................................299
Figure 8-15: State flow for an 8-bit serial-to-parallel Finite State Machine ........................ 300
Figure 8-16: Primary functional blocks in a Finite State Machine ......................................305
Figure 8-17: Functional block diagram for a serial-to-parallel finite state machine ...........310
Figure 8-18: Synthesis result for Example 8-3: Simple-SPI using a state machine ............312
List of Figures xxiii

Chapter 9: Modeling Latches and Avoiding Unintentional Latches

Figure 9-1: Synthesis result for Example 9-1: Pipeline with intentional latches ...............327
Figure 9-2: Round-robin Finite State Machine state flow .................................................332
Figure 9-3: Synthesis result for Example 9-2: FSM with unintended latches ....................335
Figure 9-4: Synthesis result when using a default case item to prevent latches ................336
Figure 9-5: Synthesis result using a pre-case assignment to prevent latches......................339
Figure 9-6: Synthesis result when using a unique case statement to prevent latches ........343
Figure 9-7: Synthesis result using a default case X assignment to prevent latches ............347
Figure 9-8: Synthesis results when using a pre-case X assignment....................................348

Chapter 10: Modeling Communication Buses — Interface Ports

Figure 10-1: Block diagram connecting a Master and Slave using separate ports ..............357
Figure 10-2: Block diagram connecting a Master and Slave using interface ports .............361

Appendix A: Best Practice Coding Guidelines

Appendix B: SystemVerilog Reserved Keywords

Appendix C: X Optimism and X Pessimism in RTL Models

Figure C-l: Flip-flop with synchronous reset......................................................................404
Figure C-2: 2-to-l selection — MUX gate implementation................................................405
Figure C-3: 2-to-l selection — NAND gate implementation..............................................405
Figure C-4: Clock divider with pessimistic X lock-up........................................................416

Appendix D: Additional Resources

 XXV

Foreword

by Phil M oorby
The creator o f the Verilog language

Verilog is now over 30 years old, and has spanned the years of designing with
graphical schematic entry tools of a few thousand gates, to modem RTL design using
tools supporting millions, if not billions, of gates, all following the enduring predic­
tion of Moore's law. Verilog addressed the simulation and verification problems of the
day, but also included capabilities that enabled a new generation of EDA technology
to evolve, namely synthesis from RTL. Verilog thus became the mainstay language of
IC designers.
Behind the scenes, there has been a steady process of inventing and learning what
was needed and what worked (and what did not work!) to improve the language to
keep up with the inevitable growth demands. From the public's point of view, there
were the stepping-stones from one published standard to the next: the first published
standard in 1995, the eagerly awaited update of Verilog in 2001, the final of the older
Verilog standard in 2005, and the matured System Verilog standard in 2012, just to
name some of the main stones.
I have always held the belief that for hardware designers to achieve their best in
inventing new ideas they must think (if not dream) in a self contained, consistent and
concise language. It is often said when learning a new natural language that your
brain doesn't get it until you realize that you are speaking it in your dreams.
Over the last 15 years, Verilog has been extended and matured into the System Ver­
ilog language of today, and includes major new abstract constmcts, test-bench verifi­
cation, formal analysis, and C-based API’s. SystemVerilog also defines new layers in
the Verilog simulation strata. These extensions provide significant new capabilities to
the designer, verification engineer and architect, allowing better teamwork and co­
ordination between different project members. As was the case with the original Ver­
ilog, teams who adopt SystemVerilog based tools will be more productive and pro­
duce better quality designs in shorter periods. Many published textbooks on the
design side of the new SystemVerilog assumed that the reader was familiar with Ver­
ilog, and simply explained the new extensions. It is time to leave behind the stepping-
stones and to teach a single consistent and concise language in a single book, and
maybe not even refer to the old ways at all!
XXVI RTL Modeling with SystemVerilog for Simulation and Synthesis

If you are a designer or architect building digital systems, or a verification engineer

searching for bugs in these designs, then SystemVerilog will provide you with signif­
icant benefits, and this book is a great place to learn the design aspects of SystemVer­
ilog and the future of hardware design.
Happy inventing...

P hil Moorby,
M ontana Systems, Inc.
M assachusetts, 2016
 X X V II

Preface

SystemVerilog, officially the IEEE Std 1800™ standard, is a “Hardware Design

and Verification Language”. The language serves a dual purpose: to model digital
design behavior, and to program verification testbenches to stimulate and verify the
design models.
This book is based on the IEEE Std 1800-2012 and proposed IEEE Std 1800-2017
SystemVerilog standards. The 1800-2012 SystemVerilog standard was the version
currently in use at the time this book was written. The 1800-2017 standard was in the
process of being finalized.
SystemVerilog is the latest generation of what was originally called Verilog. Sys­
temVerilog adds powerful language constructs for modeling and verifying the behav­
ior of designs that are ever increasing in size and complexity. These extensions to
Verilog fall into two major groups: design modeling enhancements, and verification
enhancements.
This book, RTL Modeling with SystemVerilog fo r Simulation and Synthesis,
focuses on using SystemVerilog for modeling digital ASIC and FPGA designs at the
RTL level of abstraction. A companion book, SystemVerilog fo r Verification1, covers
verifying correct functionality of large, complex designs.

W hy this book

I (Stuart Sutherland) teach corporate-level SystemVerilog training workshops for

companies throughout the world, and provide SystemVerilog consulting services. As
a course developer and trainer, I have been disappointed with the offering of System­
Verilog books for design and synthesis. There are a few books that offer a primer-like
overview of SystemVerilog, many books that focus on the verification aspects of Sys­
temVerilog, and several books that cover the long-obsolete Verilog-2001 language for
hardware design. A few of these older Verilog based books have been updated to
show some SystemVerilog features, but the traditional Verilog roots are still evident
in the coding styles and examples of those books.
This book addresses these shortcomings. The book was written with SystemVerilog
as its starting point, rather than starting with traditional Verilog and adding System­
Verilog features. The focus is writing RTL models of digital designs, using System­
Verilog constructs that are synthesizable for both ASIC or FPGA devices. Proper
coding styles for simulation and synthesis are emphasized throughout the book.

1. Chris Spear and Greg Tumbush, “SystemVerilog for Verification, Third Edition”, New York, NY:
Springer 2012, 978-1-4614-0715-7.
X X V III RTL Modeling with SystemVerilog for Simulation and Synthesis

Intended audience for this book

This book is for all engineers who are involved with digital IC design. The book is
intended to serve as both a learning guide and a reference manual on the RTL synthe­
sis subset of the SystemVerilog language. The book presents SystemVerilog in the
context of examples, with an emphasis on correct, best-practice coding styles.

NOTE
This book assumes the reader is already familiar with digital logic design.

The text and examples in this book assume and require an understanding of digital
logic. Concepts such as AND, OR and Exclusive-OR gates, multiplexors, flip-flops,
and state machines are not defined in this book. This book can be a useful resource in
conjunction with learning and applying digital design engineering skills.

Topics covered in this book

This book focuses on the portion of SystemVerilog that is intended for representing
digital hardware designs in a manner that is both simulatable and synthesizable.
Chapter 1 presents a brief overview of simulating and synthesizing the SystemVer­
ilog language. The major differences between SystemVerilog and traditional Verilog
are also presented.
Chapter 2 provides an overview of RTL modeling in SystemVerilog. Topics include
SystemVerilog language rules, design partitioning, and netlists.
Chapter 3 goes into detail on the many data types in SystemVerilog, and which data
types are useful in RTL modeling. The appropriate use of 2-state and 4-state types is
discussed. The chapter also presents using data arrays as synthesizable, RTL model­
ing constructs.
Chapter 4 presents user-defined types, including enumerated types, structures, and
unions. The use of packages as a place to declare user-defined types is also covered.
Chapter 5 explains the many programming operators in SystemVerilog, and shows
how to use these operators to code accurate and deterministic RTL models.
Chapter 6 covers the programming statements in SystemVerilog, with an emphasis
on proper RTL coding guidelines in order to ensure the code will synthesize to the
gate-level implementation intended. Several programming statements that System­
Verilog adds to the original Verilog language make it possible to model using fewer
lines of code compared to standard Verilog.
Chapter 7 gives an in-depth look at writing RTL models of combinational logic.
Best-practice coding recommendations are given for writing models that will simulate
and synthesize correctly.
Preface X X IX

Chapter 8 examines the correct way to model RTL sequential logic behavior. Topics
include synchronous and asynchronous resets, set/reset flip-flops, chip-enable flip-
flops, and memory devices, such as RAMs.
Chapter 9 presents the proper way to model latches in RTL models, and how to avoid
unintentional latches.
Chapter 10 discusses the powerful interface construct that SystemVerilog adds to tra­
ditional Verilog. Interfaces greatly simplify the representation of complex buses and
enable the creation of more intelligent, easier to use IP (intellectual property) models.
Appendix A summarizes the best-practice coding guidelines and recommendations
that are made in each chapter of the book.
Appendix B lists the set of reserved keywords for each generation of the Verilog and
SystemVerilog standards.
Appendix C is a reprint of a paper entitled I ’m Still In Love With My X, regarding
how X values propagate in RTL models. The paper recommends ways to minimize or
catch potential problems with X-optimism and X-pessimism in RTL models.
Appendix D lists some additional resources that are closely related to the topics dis­
cussed in this book.

Book examples
The examples in this book illustrate specific SystemVerilog constructs in a realistic,
though small, context. Complete code examples list the code between two horizontal
lines, as shown below. This book use a convention of showing all SystemVerilog key­
words in bold.

SystemVerilog RTL model of 32-bit adder/subtractor (same as Example 1-3, page 11)
module rtl_adder_subtractor
(input logic elk, // 1-bit scalar input
input logic mode, // 1-bit scalar input
input logic [31:0] a, b, // 32-bit vector inputs
output logic [31:0] sum // 32-bit vector output
);
always_ff 0 (posedge elk) begin
if (mode == 0) sum <= a + b;
else sum <= a - b;
end
endmodule: rtl adder subtractor

Each chapter also contains many shorter examples, referred to a code snippets.
These snippets are not complete models, and are not encapsulated between horizontal
lines. The full source code, such as variable declarations, is not included in these code
XXX RTL Modeling with SystemVerilog for Simulation and Synthesis

snippets. This was done in order to focus on specific aspects of SystemVerilog con­
structs without clutter from surrounding code.

Obtaining copies of the examples

The complete code for all the examples listed in this book is available for personal,
non-commercial use. They can be downloaded from the Sutherland HDL website, at
sutherland-hdl.com/books/sv_rtl_synthesis/sv_rtl_synthesis_book_examples.zip.

Simulators and synthesis compilers used in this book

NOTE
This book strives to be vendor and software tool neutral. While specific
products were used to test the examples in this book, all examples should run
with any simulator or synthesis compiler that adheres to the IEEE 1800-2012
SvstemVerilog standard.

The examples in this book have been tested with multiple simulation and synthesis
tools, including (listed alphabetically by company name):

• The Cadence Genus RTL Compiler (r ) synthesis compiler.

• The Intel (formerly Altera) Quartus (r ) Prime synthesis compiler.

• The Mentor Graphics Questa™ simulator and Precision RTL Synthesis™ com­
piler.

• The Synopsys VCS ( )

simulator, DC-Ultra(
r r )
synthesis compiler, and Synplify-
Pro® synthesis compiler. The SpyGlass® Lint RTL rule checker was also used
with certain examples.

• The Xilinx Vivado (r ) synthesis compiler.

The software versions used for testing the book examples were the latest versions
available to the author in Q 1-2017. (A few tools did not support a SystemVerilog lan­
guage feature used in one or two examples, but will probably support those language
features in future versions of the tool.)
The Mentor Graphics Precision RTL Synthesis™ compiler was used to generate
the synthesis schematic output shown with many of the examples. This compiler was
selected because the schematics created by this tool were easy to capture in black-
and-white, and to adapt to the page size of the book.
Preface xxxi

Other sources of information

Some other resources which can serve as companions to this book include:
IEEE Std 1800-2012, SystemVerilog Language Reference Manual LRM)— IEEE
Standard for SystemVerilog: Unified Hardware Design, Specification and Verification
Language.
Copyright 2013, IEEE, Inc., New York, NY. ISBN 978-0-7381-8110-3. Elec­
tronic PDF form, (also available in soft cover).
This is the official SystemVerilog standard. The book is a syntax and semantics
reference, not a tutorial for learning SystemVerilog. It can be downloaded for free
from https://standards.ieee.org/getieeeZl800/download/1800-2012.pdf.
System Verilog fo r Verification—A Guide to Learning the Testbench Language Fea­
turest third edition by Chris Spear and Greg Tumbush.
Copyright 2012, Springer, New York, New York. ISBN 978-1-4614-0715-7.
The Spear and Tumbush book is a companion to this book, with a focus on the
verification side of SystemVerilog. For more information, refer to the publisher’s
web site: h ttp ://www. springer, com/engineering/circui ts+%2 6+systems/book/
978-1-4614-0714-0.
Additional resources related to the topics in this book are listed in Appendix D.

Acknowledgements
I am grateful to all those who have helped with this book. I would like to specifi­
cally thank those that provided invaluable feedback by reviewing specific chapters
the book for technical content and accuracy. These reviewers include: Leah Clark,
Clifford Cummings, Steve Golson, Kelly Larson, Don Mills and Chris Spear. I am
also grateful to Shalom Bresticker, who answered many technical questions over the
period of time that I wrote this book.
Special recognition is extended to Don Mills, who provided valuable feedback and
assistance throughout the writing process. Don recommended ideas for many of the
book examples, and helped with testing the code examples on multiple simulators and
synthesis compilers.
I am especially appreciative of Phil Moorby, the creator of the original Verilog lan­
guage and simulator, for writing the foreword for this book and for creating a long-
lasting design and verification language for the digital design industry.
I would also like to recognize and thank my wonderful wife, LeeAnn Sutherland,
for her painstaking reviews of this book for grammar, punctuation and readability.*

* * *
 1

Chapter 1
SystemVerilog Simulation and Synthesis

Abstract — This chapter explores the general concepts of modeling hardware using
SystemVerilog, and the roles of simulation and synthesis in the hardware design flow.
Some of the major topics presented in this section are:
• The difference between Verilog and SystemVerilog
• RTL and gate-level modeling
• Defining an RTL synthesis subset of SystemVerilog
• Modeling ASICs and FPGAs
• Model verification testbenches
• The role and usage of digital simulation with SystemVerilog
• The role and usage of digital synthesis with SystemVerilog
• The role and usage of SystemVerilog lint checkers

1.1 Verilog and SystemVerilog — a brief history

Verilog and System Verilog are synonymous names for the same Hardware Descrip­
tion Language (HDL). SystemVerilog is the newer name for the official IEEE lan­
guage standard, and replaces the original Verilog name.
Verilog began as a proprietary design language in the early 1980s, for use with a
digital simulator sold by Gateway Design Automation. The proprietary Verilog HDL
was opened to the public domain in 1989, and standardized by the IEEE as an interna­
tional standard in 1995 as IEEE Std 1364-1995™ (commonly referred to as “Ver-
ilog-95”). The IEEE updated the Verilog standard in 2001 as the 1364-2001™
standard, referred to as “Verilog-2001”. The last official version under the Verilog
name was IEEE Std 1364-2005™. In that same year, the IEEE released an extensive
set of enhancements to the Verilog HDL. These enhancements were initially docu­
mented under a different standards number and name, the IEEE Std 1800-2005™
SystemVerilog standard. In 2009, the IEEE terminated the IEEE-1364 standard, and
merged Verilog-2005 into the SystemVerilog standard, with the standards number
IEEE Std 1800-2009™ standard. Additional design and verification enhancements
were added in 2012, as the IEEE Std 1800-2012™ standard, referred to as System-
2 RTL Modeling with SystemVerilog for Simulation and Synthesis

Verilog-2012. At the time this book was writting, the IEEE was nearing completion
of a proposed IEEE Std 1800-2017™ standard, or SystemVerilog-2017. This version
only corrects errata in the 2012 version of the standard, and adds clarifications on the
language syntax and semantic rules.

1.1.1 The Original Verilog

Verilog began in the early 1980s as a proprietary Hardware Description Language
(HDL) from a company called Gateway Design Automation. The primary author of
the original Verilog HDL is Phil Moorby. In the early 1980s, digital simulation was
becoming popular. Several Electronic Design Automation (EDA) companies provided
digital simulators, but there were no standard Hardware Description Languages to use
with these simulators. Instead, each simulator company provided a proprietary model­
ing language specific to that simulator. Gateway Design Automation was no different.
The simulator product was named “Verilog-XL” (short for “Verification Logic,
Accelerated”), and its accompanying modeling language was called “Verilog”.
The Verilog-XL simulator and the Verilog HDL became the dominant simulator
and language for digital design in the latter half of the 1980s. Some factors that attrib­
uted to this popularity included: 1) speed and capacity, 2) ASIC timing accuracy, 3)
an integrated design and verification language, and 4) digital synthesis.
1. The Verilog-XL simulator was faster and had a larger design size capacity than
most, if not all, of its contemporary competing simulators, allowing companies to
more efficiently design larger, more complex digital integrated circuits (ICs).
2. In the latter half of the 1980s, many electronic design companies were switching
from custom ICs to Application Specific ICs (ASICs). Gateway Design Automa­
tion worked closely with major ASIC suppliers, and Verilog-XL became the
golden reference simulator for ensuring timing accurate ASIC simulations. This
preference by ASIC suppliers helped make Verilog a preferred language for com­
panies involved in designing ASICs.
3. The major digital simulators in the 1970s and early 1980s typically involved
working with two proprietary languages: a gate-level modeling language to
model the digital logic, and a separate proprietary language to model stimulus
and response checking for simulation. Gateway Design Automation departed
from this tradition, and integrated gate-level modeling, abstract functional mod­
eling, stimulus and response checking all into a single language, called Verilog.
4. The fourth reason many companies adopted the Verilog language for the design
of ASICs was the ability to synthesize abstract Verilog models into gate-level
models. In the latter half of the 1980s, Synopsys, Inc. struck an agreement with
Gateway Design Automation to use the proprietary Verilog language with the
Synopsys Design Compiler (DC) digital synthesis tool. The ability to both simu­
late and synthesize the Verilog language was a tremendous advantage over all
other proprietary digital modeling languages at that time.
Exploring the Variety of Random
Documents with Different Content
up to a higher place, to show to the brethren who remained in the
monastery of Lindisfarne that the holy soul of Cudberct had now
departed to the Lord; for such was the signal agreed upon among
them to notify his most holy death. And when the monk who was
intently watching afar off, on the opposite watch-tower of the island
of Lindisfarne, saw this, for which he had been waiting, he ran
quickly to the church, where the whole congregation of the monks
were assembled to celebrate the solemnities of nocturnal psalmody;
and it happened that they also, when he entered, were singing the
before-mentioned psalm,’ The body of Cudberct was then brought in
a boat to the island of Lindisfarne, where ‘it was received by a great
multitude of people, who, together with choirs of choristers, met it,
and it was deposited in a stone coffin in the church of the blessed
apostle Peter, on the right side of the altar.’[414]
Α.D. 698. Eleven years after his death, the remains of
Relics of Cudberct were enshrined, and, as the custom of
Cudberct enshrining the relics of their saints was now
enshrined.
beginning in the Irish Church, the circumstances
here detailed are very instructive. The Divine power, Bede tells us,
‘put it into the hearts of the brethren to raise his bones, which they
expected to have found dry, as is usual with the dead when the rest
of the body has been consumed and reduced to dust, in order that
they might enclose his remains in a light chest; and they intended,
for the sake of decent veneration, to deposit them in the same
place, but above instead of below the pavement. When they
expressed this their desire to Eadberct, their bishop, he assented to
their proposal, and commanded that they should remember to do
this on the day of his deposition, which occurred on the thirteenth of
the kalends of April, or the 20th of March. This they accordingly did;
but, on opening the sepulchre, they found his whole body as entire
as when he was yet living, and more like one in a sound sleep, for
the joints of the limbs were flexible, than one who was dead.’ They
hastened to inform the bishop, who was at the time dwelling as a
solitary in the island of Farne, of what appeared to them a
miraculous preservation of the remains, and he desired them ‘to gird
the body with fresh wrappings instead of those which they had
removed, and so place him in the chest they had prepared.’ The
monks did as they were commanded; ‘and the body having been
wrapped in new raiment and laid in a light chest, they deposited it
upon the pavement of the sanctuary.’[415] This is a very early example
of enshrining, and shows that the shrine they had prepared was
large enough to receive the entire body, and that the custom then
was to inter a saint in a stone coffin under the pavement, at the
right side of the altar; but to place a shrine, enclosing his remains,
above the pavement.[416]
A.D. 688. Adamnan’s first visit to Northumbria was made
Strathclyde in the year 686; but we know nothing of it
Britons conform beyond the fact that the object of it was to
to Rome.
redeem from Aldfrid the captives who had been
carried off from Ireland by his predecessor, King Ecgfrid. Cudberct
was at this time bishop of Lindisfarne, and it is extremely probable
that they met. Adamnan’s second visit, however, was in 688, after
Cudberct’s death, but while the whole kingdom was still full of his
memory and the report of his sayings and doings; and these may
have probably had their effect in bringing Adamnan over to the
adoption of the Roman system, of which Cudberct had latterly been
such a strenuous supporter. Bede tells us that, through his efforts, a
great part of the Scots in Ireland, and some also of the Britons in
Britain, conformed to the proper and ecclesiastical time of keeping
Easter. By the latter expression, the Britons of Strathclyde, who had
recently regained their freedom from the yoke of the Angles, are
meant,[417] as the Britons of North Wales did not conform till the year
768, nor those of South Wales till the year 777. With the Britons of
Strathclyde, too, we may connect at this time Sedulius as their
bishop, who was present at a council held at Rome in the year 721,
under Pope Gregory II., and subscribes its canons as Sedulius, a
bishop of Britain of the nation of the Scots.[418] The Strathclyde
Britons therefore, on regaining their independence, appear to have
obtained a bishop from Ireland, probably from the southern Scots;
and his presence at this council proves that he was of the Roman
party.
A.D.705-709. On Cudberct’s death, Wilfrid, who had been
Wilfrid founds restored to his bishopric of York by King Aldfrid in
chapels at the previous year, held the episcopal see of
Hexham,
dedicated to St. Lindisfarne one year, till such time as a bishop
Michael and St. was chosen to be ordained in his room,[419] and
Mary. seems to have not a little troubled the monks
during his short rule, as no doubt Bede alludes to
his temporary government of the monastery when he says, ‘For in
truth, after the man of God was buried, so violent a storm of
temptation shook that church, that several of the brethren chose
rather to depart from the place than to encounter such dangers.
Nevertheless Eadberct was ordained to the bishopric the year after;
and, as he was a man noted for his great virtues and deep learning
in the Scriptures, and above all given to works of almsdeeds, he put
to flight the tempest of disturbance which had arisen.’[420] Wilfrid was
not more fortunate in the management of his restored diocese of
York, for he was again expelled after having held it five years.[421]
Wilfrid, as usual, appealed to Rome, and the Pope, as usual, decided
in his favour; and we learn both from Bede and Eddi that on his
return journey he was suddenly seized with illness in the city of
Meaux in Gaul, where he lay four days and nights as if he had been
dead; but on the dawn of the fifth day he sat up in bed, as it were
awakening out of a deep sleep, and saw numbers of the brethren
singing and weeping about him. He asked for Acca the priest, and,
when he came, told him that he had a dreadful vision. ‘There stood
by him,’ he said, ‘a certain person remarkable for his white
garments, who told him that he was Michael the Archangel, and was
sent to recall him from death; for the Lord had granted him life
through the prayers and tears of his disciples and the intercession of
the blessed Virgin Mary; and that he would recover from his illness.
“But be ready,” he added, “for I will return and visit thee at the end
of four years. Go home and rear a church in her honour who has
won for thee thy life. You have already built churches in honour of
St. Peter and St. Andrew, but hast done nothing for St. Mary who
interceded for thee. Amend this, and dedicate a church to her.”’[422]
The bishop accordingly recovered, and setting forward on his
journey arrived in Britain. Notwithstanding the decision of the Pope,
King Aldfrid refused to admit him, but, on the king’s death in 705, a
synod was held near the river Nidd in the first year of the reign of
his successor Osred, and after some contention he was, by the
consent of all, admitted to preside over his church, and his two
principal monasteries—Ripon and Hexham—were restored to him;
and thus he lived in peace four years, that is, till the day of his
death. His troubled life came to an end in 709; and he was carried to
his first monastery of Ripon, and buried in the church of the blessed
Peter the apostle close by the south end of the altar. During this
period of four years Wilfrid had, as we have seen, regained
possession of the monastery of Hexham, which he had founded and
dedicated to St. Andrew; and now, according to the injunction of the
archangel, as Eddi tells us, the church of St. Mary at Hexham had its
beginning; and, as a thank-offering to St. Michael himself, another
temple in the same place, or near it, was erected soon afterwards.
A.D. 709-731. Wilfrid was succeeded, as Bede tells us, in the
Relics of St. bishopric of the church of Hagustald by Acca his
Andrew brought priest, who, ‘being himself a most active person
to Hexham by
Acca. and great in the sight of God and man, much
adorned and added by his wonderful works to the
structure of his church, which is dedicated to the blessed apostle
Andrew. For he made it his business, and does so still (for Acca was
still bishop of Hexham when Bede wrote), to procure relics of the
blessed apostles and martyrs of Christ from all parts, to erect altars
in honour of them, dividing the same by porches in the walls of the
church. Besides which he very diligently gathered the histories of
their sufferings together with other ecclesiastical writings, and
erected there a most numerous and noble library.’ Bede adds that
‘Acca was bred up from his youth and instructed among the clergy of
the most holy and beloved of God, Boza, bishop of York. Afterwards
coming to Bishop Wilfrid in the hope of improving himself, he spent
the rest of his life under him till that bishop’s death, and, going with
him to Rome, learnt there many profitable things concerning the
government of the holy church which he could not have learnt in his
own country.’[423] Among the relics of the blessed apostles thus
collected and brought to Hexham by Acca were most certainly the
relics of St. Andrew,[424] and among the histories gathered together
by him would no doubt be the legend of that apostle. When Bede
finishes his history in the year 731, he tells us that at that time four
bishops presided in the province of the Northumbrians. Wilfrid
(second of the name) in the church of York, Ediluald in that of
Lindisfarne, Acca in that of Hagustald, or Hexham, and Pecthelm in
that which is called Candida Casa, or the White House, ‘which, from
the increased number of believers, has lately become an additional
see, and has him for its first prelate.’[425]
Monastery of From the time when the great diocese of York
Balthere at was broken up in the year 681, its history has
Tyninghame. had no bearing upon that of the churches of
Cumbria or Lothian. The diocese of Lindisfarne, however, extended
to the Firth of Forth; and about this time the monastery of
Tyninghame, at the mouth of the river Tyne in East Lothian, must
have been founded within it by Balthere the anchorite. Simeon of
Durham, in his History of the Kings, records in the year 756 the
death of Balthere the anchorite, and, in his History of the Church of
Durham, he adds ‘in Tiningaham.’[426] He is popularly known in the
district as St. Baldred of the Bass. By Bower St. Baldred is connected
with Kentigern, and said to have been his suffragan bishop; and he
reports a tradition that, a contest having arisen between the
parishioners of the three churches of Haldhame, Tyninghame, and
Lyntoun, in Lothian, for the possession of his body, and arms having
been resorted to, they were at night overcome with sleep, and on
awaking found three bodies exactly alike, one of which was buried in
each church. This sufficiently connects St. Baldred with Tyninghame;
and Alcuin, who wrote in the eighth century, as clearly connects
Balthere with the Bass.[427] He was thus removed from Kentigern’s
time by more than a century, was in reality an anchorite, and
connected, not with the British diocese of Cumbria, but with the
Anglic see of Lindisfarne. This diocese contained the territory
extending from the Tyne to the Tweed, including the district of
Teviotdale; and we learn from the anonymous history of Cudberct
that its possessions beyond the Tweed consisted of the districts on
the north bank from the sea to the river Leader, and the whole land
which belonged to the monastery of St. Balthere, which is called
Tyningham, from the Lammermoors to the mouth of the river Esk.
[428]
Beyond this western boundary the church of Lindisfarne
possessed the monastery of Mailros with its territory;
Tighbrethingham, which cannot be identified with any certainty;
Eoriercorn or Abercorn, on the south shore of the Firth of Forth, and
the monastery in which Trumuini had his seat when he ruled over
the province of the Picts during their subjection to the Angles, and
from which he fled after the disastrous battle of Dunnichen; and
Edwinesburch, or Edinburgh, where the church dedicated to St.
Cuthbert still bears his name.[429] The history of the church of
Hagustald, or Hexham, will be found to have an important bearing
upon that of one of the more northern churches.
Anglic bishopric Between the diocese of Lindisfarne and the
of Whithern Western Sea lay that of Glasgow, or Strathclyde,
founded about now freed from the yoke of the Angles and under
A.D. 730, and
comes to an end an independent bishop; but the district of
about 803. Galloway was still under the rule of the Angles of
Northumbria, and here the church of Ninian
appears to have been revived under an Anglic bishop some few
years before Bede terminates his History. By the increased number
of believers Bede no doubt means those of the Anglic nation who
had settled there. The line of the Anglic bishops was kept up here
for upwards of sixty years, during which five bishops filled the see;
and, when King Eadberct added the plain of Kyle and other regions
to his kingdom, they would become more firmly seated. It was
probably at this time that the veneration of Cudberct and Osuald
was extended into Ayrshire, where there are numerous dedications;
but soon afterwards the power of the Angles began to wane, and
the Anglic diocese of Candida Casa, or Whithern—owing, according
to William of Malmesbury, to the ravages of the Scots or Picts—came
to an end in the person of Beadulf, its last bishop, who lived to about
803.[430] In other words, the disorganisation of the Northumbrian
kingdom at this time and the decrease of its power enabled the
native population to eject the strangers and assert their
independence.

355. The life by Jocelyn is printed in Pinkerton’s Vitæ Sanctorum,

but very inaccurately. The fragment was first printed in the Glasgow
Chartulary; but both have been re-edited with a translation by the
late Bishop of Brechin, in his Life of Saint Ninian and Saint Kentigern,
forming the fifth volume of the Historians of Scotland.

356. This sentence would be in modern Gaelic, A Dhia gur fior sin,
and means, ‘O God, that that might be true.’

357. Vit. Anon. S. Kent., cc. i. ii. iii. iv. v.

358. In this narrative Servanus speaks a mongrel language.

Mochohe seems a Gaelic form, as the prefix Mo appears in the Gaelic
interjections, as Mo thruaigh!—woe’s me! and Chohe is probably
meant for Oche, Ochon!—alas! well-a-day! but ‘Capitalis Dominus’ is
only applicable to the Welsh form of his name. Cyndeyrn and
Munghu are pure Welsh—Cyndeyrn from Cyn, chief, teyrn, lord.
Mwyngu from Mwyn, amiable; Cu, dear.

359. Jocelyn, Vit. S. Kent., cc. i. ii. iii. iv.

360. The Breviary of Aberdeen attempts to get over the difficulty

by supposing two Servanuses—one the disciple of Palladius, the
other the Servanus of the life; but this does not help matters much,
as it involves the improbability of both having founded Culenros, and
both dying on the same day, the 1st of July.

361. Four Ancient Books of Wales, vol. ii. p. 457. It is possible that
the epithet Garthwys may be the word Jocelyn has converted into
Cathures.

362. Myvyrian Archæology, vol. ii. p. 34.

 363. See p. 37.

364. Old Stat. Ac., vol. x. p. 146.

365. Id. Jan. In Scotia sancti Kentigerni episcopi Glascuensis et

confessoris.—Mart. Usuardi, A.D. 875.

366. Jocelyn, Vit. S. Kent., cc. xxii. xxiii. xxiv.

367. Thomas’s History of the Diocese of Saint Asaph, p. 5. See

also Index of the Llyfr Coch Asaph, printed in Archæologia
Cambrensis, 3d series, vol. xiv. p. 151, where we have, ‘Nomina
villarum quas Malgunus rex dedit Kentigerno episcopo et
successoribus suis episcopis de Llanelwy.’

368. Jocelyn, Vit. S. Kent., c. xxv.

369. Jocelyn, Vit. S. Kent., cc. xxx. xxxi.

370. Jocelyn, Vit. S. Kent., c. xxxii.

371. Jocelyn, Vit. S. Kent., c. xxxiv.

372. Rees’s Essay on Welsh Saints, pp. 240 and 295. It is probable
that some others of the dedications north of the Firths of Forth and
Clyde have come through the Welsh Calendar, as Saint Modocus, or
Madoc of Kilmadock, but these are the only ones which can be
directly connected with Kentigern.

373. Diciul de Mensura orbis terræ, c. vii.

374. Adamnan, B. i. c. 8.

375. Jocelyn, Vit. S. Kent., c. xxxix.

376. Jocelyn, Vit. S. Kent., c. xliv.

 377. The Annales Cambriæ have at 612 ‘Conthigirni obitus.’—
Chron. Picts and Scots, p. 14. The 13th January fell on a Sunday in
the years 603 and 614; and, if this is to regulate it, the first year is
preferable, as Jocelyn says that Kentigern and King Rydderch died in
the same year, and this is the year in which we find King Aidan of
Dalriada heading the Cumbrian forces, which he could hardly have
done in the life of King Rydderch. The Aberdeen Breviary, in the Life
of Saint Baldred, says he died on 13th January 503, by which 603 is
probably meant.

378. Bede, Hist. Ec., B. ii. c. 14.

379. Si quis scire voluerit quis eos baptizavit, Rum map, Urbgen
baptizavit eos, et per quadraginta dies non cessavit baptizare omne
genus Ambronum, et per predicationem illius multi crediderunt in
Christo.—Chron. Picts and Scots, p. 13.

380. Bede, Hist. Ec., B. iii. c. 3.

381. Ib., B. iii. c. 26.

382. N. S. A., vol. iii. p. 56.

383. Vita S. Eatæ (Surtees).

384. N. S. A., vol. ii. p. 281.

385. Bede, Vit. S. Cudbercti, c. x.

386. Bede, Vit. S. Cudbercti, Præf.

387. Alio quoque tempore, in adolescentia sua, dum adhuc esset

in populari vita, quando in montanis juxta fluvium, quoad dicitur
Leder, cum aliis pastoribus pecos a domini sui pascebat.—Vita Anon.
S. Cuth.: Bedæ Opera Minora, p. 262.

388. Vit. S. Cud., cc. iv. vi.

 389. Libellus de nativitate Sancti Cuthberti de Historiis
Hybernensium excerptus et translatus—a MS. of the fourteenth
century, in the Diocesan Library at York, printed by the Surtees Club.

390. Et miro modo in lapidea devectus navicula, apud Galweiam in

regione illa, quae Rennii vocatur, in portu qui Rintsnoc dicitur,
applicuit.—C. xix.

391. Post hæc, curroc lapidea in Galweia derelicta, navim aliam

subiit, et alio portu, qui Letherpen dicitur, in Erregaithle, quæ est
terra Scottorum, applicuit. Portus ille inter Erregaithle et Incegal
situs est, lacus vero, qui ibi proximus adjacet, Loicafan vocatus est.
Non tamen amplius quam tres viri cum matre et filio extiterant qui
applicuerant.—Ib.

392. Ib., c. xx.

393. Scotia is here distinguished from Erregaithle, or Argathelia,

which indicates a certain antiquity.

394. Ib., c. xxi.

395. Ib., cc. xxii. xxiii.

396. Bede, Hist. Ec., B. iv. c. 27. Reverentissimus ecclesiæ

Lindisfarnensis in Britannia ex anachorita antistes Cuthberctus,
totam ab infantia usque ad senilem vitam miraculorum signis
inclitam duxit.—Bede, Chronicon Adam., 701.

397. See Preface to the volume containing the Life, p. ix.

398. It is on the authority of this life alone that a Columba is

sometimes called the first bishop of Dunkeld; but it is impossible to
accept this as historical.

399. This is true of the Columban monasteries generally.

 400. This account is abridged from the Irish Life, cc. xxvi. and
xxvii. See Surtees’ edition, pp. 82, 83.

401. In the Statistical Account we are told that there is a spring of

water about the middle of the Rock of Weem, of which St. David is
said to be the patron, who had a chapel on a shelf of the rock called
Craig-an-chapel. The fair is called Feill Dhaidh, and there is a
burying-ground called Cill Dhaidh. St. David seems to have
superseded St. Cuthbert here. The fair was held in March. St.
Cuthbert’s day is 20th March.

402. Bede, Hist. Ec., B. v. c. 19.

403. Bede, Vit. S. Cud., c. ix.

404. Bede, Vit. S. Cud., cc. x. xi. See also for locality of Niduari
Picts vol. i. p. 133, note.

405. Bede, Vit. S. Cud., c. xvi.

406. Bede, Hist. Ec., B. iii. c. 27.

407. Eddii, Vita S. Wilfridi, cap. 22

408. Bede, Vit. S. Cudbercti, c. 17; Raine’s North Durham, p. 145.

409. Bede, Vit. S. Cud., c. xvii.

410. Bede, Hist. Ec., B. iv. c. 12.

411. Ib., B. iv. c. 28. Sim. Dun. Opera (Surtees Club), p. 140.

412. Sarcophagum terræ cespite abditum.

413. Bede, Vit. S. Cud., cc. xxxvii. xxxviii. xxxix.

414. Bede, Vit. S. Cud., c. xl.

 415. Ib., c. xlii.

416. The expression by Bede for the stone coffin is arca, and for
the shrine, theca in the Ecc. Hist.; and in the Vita S. Cudbercti,
Sarcophagus and theca are used.

417. Bede, Hist. Ec., B. v. c. 15. The expression is, ‘Nonnulla etiam
de Brettonibus in Britannia,’ and Bede uses a similar expression
when he says that a part of the Britons recovered their freedom in
655.

418. Sedulius, Episcopus Britanniæ de genere Scottorum, huic

constituto a nobis promulgato subscripsi.—Haddan and Stubbs’
Councils, vol. ii. p. 7.

419. Bede, Hist. Ec., B. iv. c. 29; B. v. c. 19; Eddi, c. 43.

420. Vit. S. Cud., cap. 40.

421. Bede, Hist. Ec., B. v. c. 19; Eddi, c. 44.

422. Bede, Hist. Ec., B. v. c. 19; Eddi, Vit. S. Wilf., c. 54.

423. Bede, Hist. Ec., B. v. c. 20.

424. In the Liber de Sanctis Ecclesiæ Hagustaldensis et eorum

miraculis there is this statement—‘Ipsa insuper ecclesia pretiosis
decorata ornamentis et Sancti Andreæ aliorumque sanctorum ditata
reliquiis tam advenientium quam inhabitantium devotionem
adauxit.’—Mabillon, A.SS., sec. iii. part i. p. 204.

425. Bede, Hist. Ec., B. v. cap. 23.

426. Eodem anno (DCCLVI.) Balthere anachorita viam sanctorum

patrum est secutus, migrando ad Eum Qui se reformavit ad
imaginem Filii Sui.—Sim. Dun., Hist. Regum, ad an. 756.
 427. Scotichron., B. iii. c. 29. Alcuin, in his poem De Pontificibus et
Sanctis Ecclesiæ Eboracensis, has the following lines, obviously
referring to the Bass, under the head of ‘Nota. Baltheri Anachoretæ
res gestæ’:—

Est locus undoso circumdatus undique ponto,

Rupibus horrendis prærupto et margine septus,
In quo belli potens terreno in corpore miles
Sæpius aërias vincebat Balthere turmas, etc.
Gale, Scriptores, xv. p. 726.

428. Et illa terra ultra Tweoda ab illo loco ubi oritur fluvius Edre ab
aquilone, usque ad illum locum ubi cadit in Tweoda, et tota terra
quæ jacet inter istum fluvium Edre et alterum fluvium, qui vocatur
Leder, versus occidentem; et tota terra quæ jacet ab orientali parte
istius aquæ, quæ vocatur Leder, usque ad illum locum ubi cadit in
fluvium Tweoda versus austrum; et tota terra quæ pertinet ad
monasterium Sancti Balthere, quod vocatur Tinningaham a
Lombormore usque ad Escemathe.—Sim. Dun., Opera (Surtees ed.),
p. 140.

429. Omnes quoque ecclesia ab aqua quæ vocatur Tweoda usque

Tinam australem et ultra desertum ad occidentem pertinebant illo
tempore ad præfatam ecclesiam; et hæ mansiones, Carnham et
Culterham et duæ Geddewrd ad australem plagam Tevietæ, quas
Ecgfridus episcopus condidit; et Mailros, et Tigbrethingham, et
Eoriercorn ad occidentalem partem, Edwinesburch et Petterham, et
Aldham, et Tinningaham, et Coldingaham, et Tollmathe, et Northam.
—Sim. Dun., His. Rec., p. 68.

430. Eum (Pehtelmum) subsecuti sunt Frithewald, Pectwine,

Ethelbriht, Beadulf, nec præterea plures alicubi reperio, quod cito
defecerit episcopatus, quia extrema, ut dixi, Anglorum ora est et
Scottorum vel Pictorum depopulationi opportuna.—W. Malm., Gest.
Pontific. Ang., Lib. iii. § 118.
 CHAPTER VI.

THE SECULAR CLERGY AND THE CULDEES.

No appearance of It is not till after the expulsion of the Columban

name of Culdee monks from the kingdom of the Picts, in the
till after beginning of the eighth century, that the name of
expulsion of
Columban monks. Culdee appears. To Adamnan, to Eddi and to
Bede it was totally unknown. They knew of no
body of clergy who bore this name, and in the whole range of
ecclesiastical history there is nothing more entirely destitute of
authority than the application of this name to the Columban monks
of the sixth and seventh centuries,[431] or more utterly baseless than
the fabric which has been raised upon that assumption. Like many of
our popular notions, it originated with Hector Boece, and, at a time
when the influence of his fabulous history was still paramount in
Scotland, it became associated with an ecclesiastical controversy
which powerfully engaged the sympathies of the Scottish people;
and this gave it a force and vitality which renders it difficult for the
popular mind to regard the history of the early Scottish Church
through any other medium. At this most critical period of its history
we unfortunately lose the invaluable light afforded by the
trustworthy narratives of Adamnan and Bede, but their very silence
shows that it was a name not identified with the Monastic Church,
which then not only prevailed in Ireland, but embraced likewise the
churches of the Scots and the Picts, of the Cumbrians and the
Northumbrians, but rather associated with those influences which
affected the monastic system in both countries.
Monastic Church The Monastic Church was broken in upon by
affected by two two opposite influences, which, though very
opposite different in their characters, yet possessed one
influences: feature in common, and were eventually to unite.
One of these influences was external to the Monastic Church. The
other developed itself within it.
First, by secular The first arose when the Irish Church came in
clergy. contact with that of Rome, and is associated with
the controversy regarding Easter, and other Roman usages which
arose out of it. Although the monastic system was an important and
recognised institution in the Roman Church at the time, it was
subordinated to a hierarchy of secular clergy; and a church which
not only possessed monasticism as a feature, but was so entirely
monastic in its character that its whole clergy were embraced within
its rule, not only was alien to the Roman system, but necessarily
produced peculiarities of jurisdiction and clerical life which were
repugnant to it. Hence, where the Roman Church exercised a direct
influence upon this Monastic Church, its tendency necessarily was to
produce a return to the older system of a hierarchy of secular clergy,
with monachism as a separate institution existing within the church,
but not pervading the whole. It was this influence, which had been
brought to bear upon the church of the Picts, originating with Wilfrid
of York and affecting them through their connection with the Angles
of Northumbria, that eventually severed their connection with the
Columban church, and brought to an end the primacy of Iona over
the churches of Pictland. We have hitherto regarded this church as
identified with that founded by Columba in Iona, and, as such,
intimately connected with the Church of Ireland. We have also found
the interpretation of the peculiarities of the former in the institutions
of the latter, and the leading facts of its history in the Irish Annals.
We must now, however, treat the history of the church in the eastern
districts, which formed the territory of the Picts, separately from that
of Iona; and as, with this connection with the Irish Church, we
likewise lose the invaluable guidance of Bede, we must find our main
source of information in an analysis of those ecclesiastical traditions
applicable to this period, which have come down to us. We have
already seen, from the narrative of Bede, how Naiton, as he calls
him, or Nectan, king of the Picts who inhabit the northern parts of
Britain, taught by frequent study of the ecclesiastical writings,
renounced the error by which he and his nation had till then been
held in relation to the observance of Easter, and submitted, together
with his people, to celebrate the Catholic time of our Lord’s
resurrection; how he sought assistance from the nation of the
Angles, and sent messengers to Ceolfrid, abbot of the monastery of
Jarrow, desiring him to write him a letter containing arguments by
the help of which he might the more powerfully confute those that
persevered in keeping Easter out of the due time, and also
concerning the form and manner of the tonsure for distinguishing
the clergy; how he prayed to have architects sent him to build a
church in his nation after the Roman manner, which he promised to
dedicate to St. Peter; how, when he received the letter he
requested, he had it read in his presence and that of the most
learned men, and interpreted into his own language, and issued a
decree that, together with his nation, he would observe this time of
Easter, and that the coronal tonsure should be received by all the
clergy in his nation; how this decree, by public command, was sent
throughout all the provinces of the Picts to be transcribed, learned
and observed; and how all the ministers of the altar and monks
adopted the coronal tonsure, and the nation was placed under the
patronage and protection of St. Peter, the Prince of the Apostles. We
have also learned from the Irish Annals that this powerful
confutation, like many other efforts to enforce uniformity, resulted in
the resistance of the Columban monks and their expulsion from his
territories.
Legend of The legend which mainly deals with this
Bonifacius. revolution is that of Bonifacius, preserved in the
Aberdeen Breviary; and his leading statements harmonise so well
with Bede’s narrative, and are so much supported by the dedications
of the churches mentioned in connection with it, that we may safely
import them into the history of this period.[432] It is thus told:—
Bonifacius was an Israelite by birth, descended from the sister of St.
Peter and St. Andrew, and born in Bethsaida. In his thirty-sixth year
he was ordained priest by John, Bishop and Patriarch of Jerusalem.
When he attained his forty-sixth year he went to Rome, where he
was made a bishop and cardinal, and then, by the election of all the
cardinals, he was elevated to the papacy. He then called some of his
brethren into the oratory, and informed them that he proposed to
set forth on a mission to the ends of the earth, for the love of God
and those people who dwelt in the northern regions beyond the
bounds of Europe. They said, ‘Send religious men, as your
predecessors Celestinus and Gregorius sent Palladius, Patricius and
Augustinus.’ But Bonifacius replied that it had been revealed to him
by St. Peter, in an angelic vision, that he should undertake this
mission himself. Accordingly, after due preparation, he shortly
afterwards set out from Rome. The mission consisted of Bonifacius,
and of Benedictus, Servandus, Pensandus, Benevolus, Madianus, and
Principuus, bishops and most devout men, who devotedly followed
him, and two distinguished virgins, abbesses, Crescentia and
Triduana; seven presbyters, seven deacons, seven sub-deacons,
seven acolytes, seven exorcists, seven lectors, seven doorkeepers,
and a great multitude of God-fearing men and women. They had a
prosperous journey and voyage, and arrived in Pictavia, sailed up the
Scottish Sea or Firth of Forth, and proceeded as far as Restinoth.
Here they were met by Nectan, king of the Picts, at the head of his
army, who, seeing such a multitude of strangers, was struck with
astonishment, but finally, with all his nobles and officers, received
the sacrament of baptism at the hands of Bonifacius and his bishops.
The king then dedicated the place of his baptism to the Holy Trinity,
and gave it to Bonifacius, who then performed the usual miracles,
‘wrote one hundred and fifty books, and founded as many churches,
with an equal number of bishops and a thousand presbyters, and
converted and baptized thirty-six thousand men and women; and
finally, in the eighty-fourth year of his age, on the 17th day before
the kalends of April, or 16th March, departed to Christ.’ Another form
of the legend states that his name was Albanus Kiritinus, surnamed
Bonifacius; that he founded a church at the mouth of the river
Gobriat, or Gowry, in Pictavia, after baptizing Nectanus the king; that
he preached sixty years to the Picts and Scots, and, at the age of
eighty, died at Rosmarkyn, and was buried in the church of St. Peter.
 These legends are borne out by the dedications, as we find that
the churches of Restennot, near Forfar, and Invergowry, at the
mouth of the water of Gowry, are dedicated to St. Peter; and
Rosemarky, on the north shore of the Moray Firth, an old Columban
monastery founded by Lugadius, or Moluog, of Lismore, was
dedicated to St. Peter and Bonifacius; while the church of Scone, the
chief seat of the kingdom, was dedicated to the Holy Trinity. The
legends are obviously connected with the revolution by which King
Nectan and the entire nation of the Picts conformed to Rome. The
earlier part of the narrative is of course fictitious, and Bonifacius is
here erroneously identified with one of the Bonifaces who occupied
the papal throne in the seventh century. The object of this was no
doubt to make more prominent and direct his character as a
missionary in the interest of the Roman party. He was in reality a
bishop from that party in the Irish Church which had conformed to
Rome. When Adamnan went to Ireland and held the synod in which
his law was promulgated in the year 697, its canons were signed,
among others, by Cuiritan epscop, or Bishop Cuiritan, and also by
Bruide mac Derili Ri Cruithintuath, or king of Pictavia, the brother
and immediate predecessor of Nectan; and in the old Irish Calendars
he appears on the 16th March as Curitan epscoip ocus abb Ruis mic
bairend, that is, Curitan, bishop and abbot of Rosmarkyn.[433] This is
also the day in which Bonifacius appears in the Scotch Calendars,
and their identity seems beyond doubt. It is equally clear that the
legend also shows the introduction of a body of secular clergy into
the kingdom of the Picts, and, as we found that at the council on the
banks of the Nidd, at which it was resolved to appoint Cuthbert
bishop, and to place him at Lindisfarne, while Eata was transferred
to Hexham, a body of seven bishops were present and confirmed the
arrangement, so here the mission is composed of seven bishops,
with an equal number of presbyters, deacons, sub-deacons,
acolytes, exorcists, lectors and doorkeepers—that is, the entire
hierarchy of the secular clergy of Rome with its minor orders.
Wynton, in his notice of Boniface, well expresses this—

‘Sevyn hundyr wynter and sextene,

 Quhen lychtare wes the Virgyne clene,
Pape off Rome than Gregore
The Secund, quham off yhe herd before,
And Anastas than Empryowre,
The fyrst yhere off hys honowre,
Nectan Derly wes than regnand
Owre the Peychtis in Scotland.
In Ros he fowndyd Rosmarkyne,
That dowyd wes wytht kyngys syne,
And made was a place Cathedrale
Be-north Murrave severalle;
Quhare chanownys ar seculare
Wndyr Saynt Bonyface lyvand thare.’[434]

Legend of Another legend which appears to belong to this

Fergusianus. period, and which is likewise confirmed by the
dedications, is that of Fergus, or Fergusianus. His story is this: He
was for many years a bishop in Ireland, and then came to the
western parts of Scotland, to the confines of Strogeth, where he
founded three churches. Thence he went to Cathania, or Caithness,
where for some time he occupied himself in converting the
barbarous people. After that he visited Buchan, resting in a place
called Lungley, where he built a basilica, which still exists, dedicated
to himself. Then he came to Glammis, where he consecrated a
tabernacle to the God of Jacob, and where he died full of years. His
bones were afterwards enshrined in a shrine of marble, and his head
taken with all due honour to the monastery of Scone, where many
miracles were performed.[435] Now, we find that among the bishops
who were present at the council held at Rome in the year 721, and
signed the canons, is ‘Fergus the Pict, a bishop of Ireland,’[436] who is
no doubt our Fergus before he passed over to Pictland in Britain,
which appears to have been his native country; and his appearance
at the council of Rome shows that he belonged to the party who had
conformed to the Roman Church. At Strageath, in the district of
Stratherne, and in the immediate neighbourhood, are three churches
dedicated to St. Patrick—those of Strageath, Blackford and
Dolpatrick—which shows that their founder had come from Ireland.
In Caithness, the churches of Wick and Halkirk are dedicated to St.
Fergus. In Buchan the village called in the legend Lungley is now
named St. Fergus, and the neighbouring parish of Inverugie, now
called Peterhead, is dedicated to St. Peter. At Glammis we have St.
Fergus’ cave and St. Fergus’ well, and the statement that his head
was preserved at Scone is confirmed by an entry in the accounts of
the Lord High Treasurer, of a payment by James IV. for a silver case
for it.
Churches The distribution of the churches among the
dedicated to St. Picts which were dedicated to St. Peter will show
Peter. the extent to which the country at this time
adopted him as their patron. Among the southern Picts we have
Invergowry, Tealing, Restennot, and Meigle. Among the northern
Picts we have in Aberdeen and Banff, Cultyr, Fivy and Inverugie; and
in Moray and Ross, Drumdelgy, Ruthven, Glenbucket, Belty,
Inverawen, Duffus and Rosemarky. King Nectan himself is said by
the Irish annalist Tighernac to have become a cleric in the year 724,
[437]
and probably retired to the church which he had built after the
Roman manner by the architects sent him from Northumbria, and
which, as he had promised to dedicate that church to St. Peter, must
have been one of these we have named, either Restennot or
Rosemarky.
Second influence: These legends having thus so far indicated the
the Anachoretical external influence which led to the introduction of
life. the secular clergy into the church among the
Picts, we must now advert to another and more powerful influence
of an opposite kind, which arose within the Monastic Church itself,
and equally tended to break in upon the monastic character of that
church. This influence was that increasing asceticism which led the
monks to forsake the cœnobitical life for the solitary cell of the
anchorite, and induced those who wished to pass from a secular to a
religious life to prefer this more ascetic form of it. This form of the
religious life had long existed in the Christian Church, and, from a
very early period, there prevailed a feeling that the solitary life in the
desert, or in the anchorite’s cell, was a higher form of the religious
life than that afforded by the cœnobitical life of the monastery. Thus
St. Jerome, writing in the fourth century, tells us that ‘there were in
Egypt three kinds of monks. First, the Cœnobites, whom they call in
the Gentile tongue Sausses but whom we may term those living in
common. Secondly, the Anchorites, who live alone in desert places,
and are so called as living apart from men; and, thirdly, that kind
which are called Remoboth, the worst and most neglected;’[438] and
John Cassian, a native of Scythia, who founded two monasteries at
Marseilles, one for men and the other for virgins, and died about the
year 440, writing what he terms ‘Conferences with the Monks,’
speaks, in his eighteenth, of the different sorts of monks in his day.
He likewise distinguishes them into three sorts. First the Cœnobites,
who live in common, under an abbot, imitating the life of the
apostles. Second, Anchorites, who, after they have been instructed
and educated in monasteries, withdraw into the deserts. The authors
of this order were St. Paul the hermit and St. Anthony. And third, the
Sarabaites, who pretended to retire from the world, and joined
themselves together by two or three in a company, to live after their
own humour, not being subject to any man. He looks upon these but
as a corruption of the monastic state rather than a distinct order. He
adds to these a fourth sort of monks, made of those who, not being
able to endure the monastic life in a convent, retreated alone into
certain cells to live more at liberty, but praises the second as the
most perfect. In his nineteenth conference, an abbot called John,
who had been an anchorite and had entered a monastery, is asked
which of the two orders was to be preferred, and replies that he
thought the life of the cœnobites best for those who were not
absolutely perfect, and shows that none but those who have
attained to a degree of eminent perfection are capable of living the
life of a hermit.[439] Another of these ancient fathers, Nilus, who had
betaken himself to a solitary life in the desert of Sinai, and died
about the year 451, writes a treatise upon the question whether the
life of the Anchorites, or Hermits, whom he also calls Hesycasts, or
Quietists, who dwell in solitude, is to be preferred before the life of
those religious who dwell in cities, and states that this is a question
about which the judgment of spiritual men is much divided. Those
who prefer the religious who live in communities in cities before the
anchorites, say that they have more worth because they meet with
more opposition; whereas those who live in solitude being quiet and
not subject to temptations, have not so much virtue; to which Nilus
replies that there are as many temptations in solitude as in cities,
and that the reason why some persons argue so is because they
regard outward sins only, not considering that there are infinite
temptations and spiritual sins which encounter us as well in privacy
as in cities; and he therefore supports the opinion that the solitary
life is the higher form of the religious life.[440] Isidore of Seville, too,
in the seventh century, distinguishes between the different kinds of
monks, and says that the Cœnobites are they that live in common,
like those in the days of the apostles, who sold their goods and had
all things in common; the Hermits, they that withdraw into desert
places and vast solitudes in imitation of Elias and John the Baptist,
delighting, with a wonderful contempt of the world, in total solitude;
and the Anchorites, they who, having perfected themselves in
cœnobitical life, shut themselves up in cells apart from the aspect of
men, inaccessible to all, and living in the sole contemplation of God.
[441]
But Bede, who was a Benedictine monk, seems also to regard
the life of an anchorite as a higher form of religious life, when in his
History he says of Cudberct on his retiring to the island of Farne,
that, ‘advancing in the merits of his devout intention, he proceeded
even to the adoption of a hermit life of solitary contemplation and
secret silence;’ and, in his Life, that ‘he was now permitted to
ascend to the leisure of divine speculation, and rejoiced that he had
now reached the lot of those of whom we sing in the Psalm, The
saints shall go from virtue to virtue; the God of Gods shall be seen in
Sion.’[442]
The preference for this mode of life, as the highest form of a
religious life that could be attained, seems to have arisen from an
overstrained interpretation of some passages of Scripture. Thus
Bede, in the beginning of his Life of Cudberct, tells us that he ‘would
hallow its commencement by quoting the words of the prophet
Jeremiah, who, in lauding the state of the perfection of the
anchorite, says, “It is good for a man who hath borne the yoke from
his youth; he shall sit alone and keep silent, because he shall raise
himself above himself.”’[443] But the preference of the solitary life as
the highest form of asceticism seems to have been mainly founded
upon two passages in the New Testament. One is that passage in
the Epistle of St. James in which he winds up his exhortation by
saying, ‘Pure religion and undefiled, before God and the Father, is to
visit the widows and fatherless in their affliction, and to keep himself
unspotted from the world;’ or, as a literal rendering of the old Latin
version would be, ‘Pure and immaculate religious service towards
God and the Father is this, to visit the infants and widows in their
tribulation, and to keep oneself immaculate from this world.’[444] By
an overstrained interpretation of this passage it was assumed that a
person could only keep himself immaculate from the world by
withdrawing himself from it altogether, and from all association with
his fellow-creatures, except in works of benevolence to those in
distress; and that this was a form of religion peculiarly acceptable to
God and the Father. The other passage is that in the First Epistle of
St. Peter, where it is said, ‘But ye are a chosen generation, a royal
priesthood, an holy nation, a peculiar people; that ye should show
forth the praises of Him who hath called you out of darkness into His
marvellous light; which in times past were not a people, but are now
the people of God; which had not obtained mercy, but now have
obtained mercy. Dearly beloved, I beseech you as strangers and
pilgrims, abstain from fleshly lusts which war against the soul.’[445]
And this was interpreted to mean that those who passed their lives
in mortifying the body and praising God by singing the psalter, in
living in this world as strangers from all society and as pilgrims to a
better world, were a peculiar people and entitled to call themselves
the people of God.
Anchorites called They thus came to the conclusion that a
Deicolæ or God- solitary life passed in devotion and self-
worshippers. mortification, accompanied by acts of
benevolence to the sick and bereaved, was a ‘cultus’ or ‘religio’
peculiarly acceptable to God and the Father; and hence they were
called, if they did not call themselves so, Deicolæ, or God-
worshippers, in contrast to Christicolæ, the name applied in a
general sense to all Christians, and, in a narrower application, to
monks leading a cœnobitical life. Thus in the Life of St. Anthony,
written by Athanasius, bishop of Alexandria, who introduced
monachism into the Western Church, and translated into Latin by
Evagrius, a priest of Antioch, in the year 358, we find it stated that
‘the neighbours and the monks whom he often visited, seeing St.
Anthony, called him a Deicola, and, indulging in the expression of
natural affection, they loved him, some as a son, others as a
brother.’[446] Again, Martinus, a bishop, who terms himself Scotus, or
a native of Ireland, writing to Miro, king of Gallicia, in the sixth
century, probably about the year 560, regarding ‘the rules of an
honest life,’ says that he will not urge him to follow ‘those more
arduous and perfect rules which are practised by a few very
excellent Deicolæ.’[447] Columbanus, too, in his second instruction or
sermon to his monks, says, ‘Whosoever, therefore, willeth to be
made a habitation for God, let him strive to become lowly and quiet,
that not by glibness of words, nor by suppleness of body, but by the
reality of his humility he may be recognised as a Deicola; for
goodness of heart requireth not the feigned religion of words;’[448]
and a disciple of Columbanus, who followed out this life after his
master had been driven out of Luxeuil with his monks, retired to a
solitary spot called Luthra in the midst of a forest, now Lure in the
district of Besançon, ‘But his virtues having attracted religious men
to him from all quarters, he formed a community of monks and
erected two oratories; and, after governing his monastery for several
years, he appointed one of his disciples abbot in his stead, and again
withdrew to a solitary cell, where he devoted himself to divine
contemplation till his death about 625. This man bears no other
name in the calendars than Deicola, and his memory is still held in
high estimation by the people of that country, who call him Saint
Die.’[449]
Anchorites called We find, too, these solitaries also called the
the people of people of God. In the ancient Life of St. Patrick
God. written by Probus, he tells us that, after Patrick
had passed four years with St. Martin of Tours, where he was trained
in monastic life, an angel appeared to him and said, ‘Go to the
people of God, that is, to the hermits and solitaries, with naked feet,
and live with them, that you may be tried for some time; and he
went into a solitude, and remained with the hermits eight years.’[450]
The conception of this ‘cultus’ of God is well expressed in a
passage of Simeon of Durham, who, in his History of the Kings,
under the year 781, says, some 250 years after, of a certain Dregmo,
in the territory of the church at Hexham, that ‘he greatly feared God
and diligently devoted himself, as far as his means allowed, to the
exercise of works of charity, leading a life in all respects apart from
the customs of his countrymen—a man of remarkable simplicity and
innocence, and of profound devotion and reverence towards the
saints of God; on which account his neighbours held him in great
honour, and called him a true God-worshipper.’[451]
In the seventh century attempts were made by several councils to
bring the solitaries more under the monastic rule. By the fifth canon
of the Council of Toledo, held in 646, it was provided that ‘well-
instructed monks alone should be allowed to live separate from a
cloister as recluses, and become the trainers of others in the higher
forms of ascetic life. Those recluses and wanderers who are
unworthy must be brought within a cloister, and in future no one
must be devoted to this highest form of the ascetic life, as a recluse,
who had not first been trained in a monastery to the knowledge and
practice of the monastic life.’[452] By the Council of Trullo, held in 692,
it was provided, by canon 41, that those who would live separate in
their own cells must have first passed three years in a monastery,
and that any one who has once withdrawn himself to a solitary cell
must not again leave it; and by canon 42 that, as there are hermits
who come to the towns in black clothing and long hair, and associate
with secular persons, it is ordered that such persons shall be
tonsured and enter a monastery, wearing the monastic dress. If they
will not do this, they must be expelled from the town.[453]
A.D. 747. Such attempts, however, seem to have had
Order of Secular little effect, and the next century was to see the
Canons Anchorites and Recluses, who lived apart from
instituted.
the monastic rule, and practised what they
considered the highest form of asceticism, and the secular clergy,
who had never come under the monastic rule, but were subject only
to the general canon-law of the church, brought more together, a
tendency to which indeed had probably already manifested itself in
the end of the previous century, which the forty-second canon of the
Council of Trullo was designed to check. For though nothing could be
more opposed in spirit, than the secular life of the ordinary clergy on
the one hand and the ascetic life of the anchorites on the other,
forming, as it were, the opposite poles of the ecclesiastical system,
yet they had one feature in common—that both lived separately, in
opposition to the cœnobitical life of the monks. The new institution
which thus brought them together was that of the secular canons,
founded by Chrodegang, bishop of Metz, in the year 747. His rule
was at first intended for his clergy of Metz alone, with a view of
leading them to adopt a more regular life in the ecclesiastical sense
of the term. This rule consists of thirty-four chapters. By the third he
directs that the canon clerics shall live together in a cloister, and
shall all sleep in one dormitory, with the exception of those to whom
the bishop shall give permission to sleep separately in their own
dwellings within the cloister; that no woman or layman is to enter
the cloister without an order from the bishop, the archdeacon, or the
‘primicerius’; that they shall eat in the same refectory, that laics shall
only be allowed to remain in the cloister as long as they have work,
and that those living separately within the cloister must live alone
and have no other cleric with them. By the ninth chapter he enjoins
them to perform the bodily labours in common as well as in private.
By the thirty-first he enjoins his clerics to give to the church what
real property they have, retaining the income only, but gives them
leave to reserve to themselves their moveable property, for
almsgiving, and to dispose of it as they please by their wills.[454]
Deicolæ brought The object of this rule was certainly to bring
under canonical the secular clergy of this town to live a
rule. cœnobitical life, but with such relaxations as
would both allow it to be considerably modified towards certain of
the body, and to permit the recluses, though not expressly named,
to be included within it; but the new canonical life became so
popular, that the rule was revised and enlarged, so as to adapt it to
the state of the clergy generally, and enable it to be extended over
the whole church. This revised rule consists of eighty-six chapters.
By the thirteenth it is provided that within the cloisters there shall be
dormitories, refectories, cellars and other habitations; that all shall
sleep in one dormitory, living as brethren in one society, except
those to whom the bishop shall give leave to sleep separately on
separate couches in their own dwellings in the cloister, with seniors
among them to watch over them; and that no female or laic shall
enter the cloister. Chapter thirty-nine bears that, as there is an evil
zeal of bitterness which separates from God and leads to
destruction, so there is a good zeal which separates from vice and
leads to God and eternal life: therefore they ought to exercise zeal
with the most fervent love, as servants of God (Servi Dei). The
eighty-first chapter, however, deals directly with the Deicolæ, with
the view of bringing them under the canonical rule. It consists of
‘the epistle of a certain Deicola, sent in the name of Christ to the
priests and clerics for their instruction and exhortation;’ and it is
addressed ‘to the beloved priests in the churches of Christ, the
bishops and all the clergy therein everywhere, and their servants,
and to all the Deicolæ living in the whole world.’[455] He begs of them
that, ‘living justly, piously and holily, they should show a good
example to others, and live with soul, heart and body under the
canonical rule.’ He exhorts ‘all clerics under them to give humble
obedience, and endeavour to fulfil the canonical rule without
murmuring, serving the Lord willingly; seeing that every man ought
to be subject to the higher powers and those put over them, how
much more should they, as servants of God (Servi Dei), humbly obey
their provosts?’ He finally exhorts them to be mindful ‘of the
canonical rules, and to have their precepts always before their
eyes.’[456] By the General Council held at Aix-la-Chapelle in 816 and
817, this canonical rule was adopted, and a number of canons were
passed to give effect to it, with some modifications. They begin with
the 114th canon. The 117th canon provides that each bishop must
see that the cloister in which his clerics live is enclosed with a strong
wall; the 120th, that those clerics who possess property of their own
and an income from the church shall receive from the community
their daily food only, with a share of the oblations. Those who have
no private means are entirely supported and clothed. By the 135th,
the boys and youths who are educated in the canonry shall be well
cared for and instructed, be placed under a senior canon and dwell
together in the upper floor of a house. By the 141st, each bishop
must provide a hospital for the poor and strangers, and each cleric
shall give the tenth of what he received for its support. By the 142d,
canons are allowed to have separate dwellings, and proper places
shall be provided for the aged and the sick within the canonry; and
by the 144th, women must not enter the dwellings and the cloister,
with the exception of the church.[457]
Deicolæ in the In the early English Church we find the name
Saxon Church. Deicola in a Saxon form applied to a community
of solitaries. We find it stated in the Peterborough MS. of the Anglo-
Saxon Chronicle, in the year 655, that ‘Peada, king of the Mercians,
and Oswiu, the brother of King Osuald, came together and said that
they would rear a monastery to the glory of Christ and the honour of
St. Peter; and they did so, and gave it the name of Medeshamstede,’
now Peterborough. In 657 the monastery was finished, and
consecrated by Deusdedit, archbishop of Canterbury, in the presence
of King Wulfhere, the brother and successor of King Peada, and his
earls and thanes. There were also present four bishops, and Wilfrid,
who was then only a priest; and the king endowed it. Then ‘the
abbot desired that he would grant him that which he would desire of
him, and the king granted it to him. “I have here,” he said, “God-
fearing monks, who would pass their lives in an anchoretage, if they
knew where. But here is an island, which is called Ancarig,” now
Thorney Isle, “and I will crave this—that we may there build a
monastery to the glory of St. Mary, that they may there dwell who
may desire to lead their lives in peace and in rest.”’ The king
accordingly grants the request, and endows this monastery also.[458]
The expression Gode-frihte, or God-fearing, here applied to these
anchorite monks, is obviously the Saxon equivalent of Deicola. In the
following century the canonical rule was introduced into England, as
we find in a legatine synod held in Northumberland, in the year 787,
that by the fourth canon bishops are required to take care that all
canons live canonically, and all monks or nuns regularly—that is,
according to monastic rule;[459] and that the title of God-worshippers
passed down to the canon clerics, at least to those who lived
separately, appears from this, that, when King Athelstan was on his
march against the Scots in 936, he halted at York, and there
besought of the ministers of St. Peter’s church, who were then called
Colidei, to offer up their prayers on behalf of himself and his
expedition. They are said to be ‘men of holy life and honest
conversation, then styled Colidei, who maintained a number of poor
people, and withal had but little whereon to live.’ ‘It would appear,’
says Dr. Reeves, ‘that these Colidei were the officiating clergy of the
cathedral church of St. Peter’s at York in 946, and that they
discharged the double function of divine service and eleemosynary
entertainment;’[460] in other words, they were canon clerics, and the
name Colidei is merely an inversion of that of Deicolæ. Those of
Canterbury we find called in a charter by King Ethelred, in 1006,
cultores clerici, or cleric God-worshippers, the word Dei being
evidently implied.[461]
Anchoretical life In the early Monastic Church of Ireland, this
in Ireland and tendency to prefer a solitary life, as a higher form
Scotland. of the religious life, developed itself at a very
early period. It seems to have assumed two different aspects. One
when the abbot or one of the brethren of the monastery retired for a
time to a separate cell, for solitary prayer, or for penitential
exercises, during which time he held no intercourse with the other
inmates of the monasteries. The cells adopted for this purpose were
usually those primitive dwellings called by the Irish Clochans, built of
unmortared stone, with walls of great thickness, circular in shape,
with a dome-shaped roof, somewhat of a beehive form, and hence
often called beehive cells. When used for such retirement they were
called Carcair, or prison cells. Thus, in an old poem attributed to
Cuimin of Coindeire, he says of Enda, who founded the monastery
on the principal of the Arann Isles:—

Enda of the high piety loved

In Ara, victory with sweetness,
Welcome to our website – the ideal destination for book lovers and
knowledge seekers. With a mission to inspire endlessly, we offer a
vast collection of books, ranging from classic literary works to
specialized publications, self-development books, and children's
literature. Each book is a new journey of discovery, expanding
knowledge and enriching the soul of the reade

Our website is not just a platform for buying books, but a bridge
connecting readers to the timeless values of culture and wisdom. With
an elegant, user-friendly interface and an intelligent search system,
we are committed to providing a quick and convenient shopping
experience. Additionally, our special promotions and home delivery
services ensure that you save time and fully enjoy the joy of reading.

Let us accompany you on the journey of exploring knowledge and

personal growth!

ebooknice.com