ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5

UNIT II - COMBINATIONAL LOGIC CIRCUITS

Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design,
Elmore’s constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic, Power
Dissipation, Low Power Design principles.

1. Introduction:
The combinational circuit is the circuit whose output depends only on the present
inputs.
Examples: Adder, Subtractor, Multiplexer, Encoder etc.,
2. Propagation Delay:
Propagation delay of a logic gate is defined as the time it takes for the effect of change
in input to be visible at the output. In other words, propagation delay is the time required for
the input to be propagated to the output.
Normally, it is defined as the difference between the times when the transitioning input
reaches 50% of its final value to the time when the output reaches 50% of the final value
showing the effect of input change.

Figure 1: 2-input AND gate

Let us consider a 2-input AND gate as shown in figure 1, with input ‘I2’ making
transition from logic ‘0’ to logic ‘1’ and 'I1' being stable at logic value '1'. In effect, it will
cause the output ‘O’ also to make a transition. The output will not show the effect immediately,
but after certain time interval. The timing diagram for the transitions are shown. The
propagation delay, in this case, will be the time interval between I2 reaching 50% while rising
to 'O' reaching 50% mark while rising as a result of 'I2' making a transition. The propagation
delay is labeled as “TP” in figure 2.

Figure 2: Propagation delay

Propagation Delay of CMOS inverter

Figure shows the CMOS inverter circuit with load capacitance CL

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
When input goes from High to Low, PMOS ON and NMOS OFF. So, CL will get charge via
PMOS upto VDD.
Similarly, When input goes from Low to High, PMOS OFF and NMOS ON. So, CL will get
discharge via NMOS.

Input and output voltage waveforms of CMOS inverter and definitions of propagation
delay times. The time required for the output voltage to rise from V 10% level to V 90% level.
The propagation delay times tpHL and tpLH establish the input to output signal delays during
high-to-low and low-to-high transitions of the output, respectively. The high-to-low
propagation delay (tpHL ) is defined as the time delay between the V 50% transition of the
rising input voltage and V 50% transition of the falling output voltage. Similarly, the low-to-
high propagation delay (tpLH ) is the time delay between the V 50% transition of the falling
input voltage and V 50% transition of the rising output voltage. To compute fall time (tf ) of the
output voltage, output load capacitance (CL ) should be discharged through the active NMOS
transistor, considering PMOS transistor is in cut-off region.

We can minimize the propagation delay by

 By decreasing the load capacitance CL, by minimizing the size of an IC.
 By increasing width of the MOS transistor, transition time will be decreased.
 By full voltage swing. That VOL=0 or GND and VOH= VDD
 By implementing the circuit using pull down network only.
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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5

Calculation of propagation delay

C V C V  V50%  12.5
tpHL = L HL = L OH = 0.69 R N C where RN 
I avgHL I avgHL W / L N

C L VLH C V  VOL  30
tpLH = = L 50% = 0.69 RPC where RP 
I avg LH I avgLH W / L P
t pHL  t pLH
Therefore, Average propagation delay t P 
2

3. Stick and Layout Diagram: Refer class Note

4. Elmore’s Constant:

The Elmore delay estimates the delay from a source (root) to one of the leaf nodes as the sum
of the resistance in the path to the i th node multiplied by the capacitance present at the end of
the branch.
It computes the delay of an RC ladder as the sum of RC delay at each node.
It has some general property:
 Single input node.
 All the capacitors are between a node and a ground.
 Network does not contain any resistive loads.

RC ladder for Elmore delay

Delay at n1:  1  R1C1

Delay at n2:  2  R1  R2 C2
Delay at n3:  3  R1  R2  R3 C3
In general
Delay at nN:  N  R1C1  R1  R2 C2  .........  R1  R2  ....RN C N
If R1  R2  R3  R and C1  C2  C3  C
Therefore,  N  RC  2RC  ......  NRC

Equation used to find the total propagation delay is given by

N i
t pd   Rni Ci   Ci R j
i i 1 j 1

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
Here Rn−i denotes the total resistance from the source to the node i.
For example delay at node N=3(n3) , using the above equation we get
t pd  C1 R1  C 2 R1  R2   C3 R1  R2  R3 
If R1  R2  R3  R and C1  C2  C3  C
Therefore total propagation delay t pd  RC  2 RC  3RC  6 RC

Problem: Calculate the Elmore delay model for the Vout in the given 2nd order system.

Solution: t pd  C1 R1  C 2 R1  R2 

5. Power Dissipation:
Generally CMOS gates are very power efficient because they dissipate zero power
while idle. In earlier stage power factor was a secondary consideration. As transistor count
and clock frequencies have increased, now power consumption becomes the primary design
constraint.
Dissipation comes from two components
1. Static dissipation
2. Dynamic dissipation
So the total power dissipation Ptotal =Pstatic + Pdynamic
1. Static dissipation:
Consider the CMOS inverter

If input= 0, PMOS = ON and NMOS= OFF. Thus output = VDD or logic 1

If input= 1, PMOS = OFF and NMOS=ON. Thus output = VSS or logic 0
Note that one of the transistor is always OFF irrespective of input. In ideal condition,
there is no current flow in OFF transistors. But due to second order effects such as

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
subthreshold conduction, tunnelling etc., some amount of static current flowing through
OFF transistor.
Thus static power dissipation is given by Pstatic  I static .Vdd
Where I static = leakage current
Vdd = supply voltage
i. Leakage due to subthreshold conduction:
Leakage current I ds due to subthreshold conduction is
Vgs Vt
 V
 ds 
I ds  I dso .e VT
.1  e VT 
 
 
That is I ds is exponentially dependent on subthreshold voltage. I ds Increases when VT
Scaled down.
ii. Leakage due to tunnelling: It is possible for electrons (leakage current) flow from
channel to gate if we use thin insulator (Sio2).
iii. Leakage due to reverse biased diodes: we know that junction of the diffusion and
substrate form diodes. Also the substrate is connected to VDD or GND becomes
reversed biased diodes. Still it conduct a small amount of current is given by
 VVD 

I D  I S e  1
T

 
 
iv. Leakage due to ratioed circuits: The leakage current is occurring in pseudo NMOS
gates where there is a direct path between power and ground.

2. Dynamic dissipation:
It is due to charging and discharging of load capacitance.

Consider a load C is switched between VDD and GND at an average frequency of fsw.
At any time interval of T, the load will be charged and discharged “T. fsw.” times. The
charging takes place when current flows from VDD to load C whereas discharge takes
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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
place when current flows from load C to GND. So for one complete charge/discharge
cycle, the total charge is transferred from VDD to GND is Q  C.VDD .
Therefore dynamic power dissipation is given by
T
Pdynamic   i DD t  VDD .dt
1
T0
T
iDD t  dt
VDD
T 0
=

T
T . f sw .C VDD   i t  dt  T f
VDD
= where DD sw C VDD
T 0

Pdynamic VDD C f sw
2

Also f sw  activity factor . clock frequency f 

Therefore, Pdynamic VDD C  f
2

6. Static Logic Gates:

It is the combination of pull-up network (PUN) and pull-down network (PDN). Here
PUN is always connected to Vdd and PDN is always connected to Gnd. Only one of the
network will be ON at a time. In PUN all switches are implemented by using PMOS
transistor which passes strong 1 but weak 0. Whereas in PDN all switches are implemented
by using NMOS transistor which passes strong 0 but weak 1. The following figure shows the
general structure of static CMOS logic.

Advantages:
 Good Noise Margin
 High speed
 Low power consumption
 Easy to design
Disadvantages:
 For a N-logic circuit, it require 2N transistors
 PUN pass weak 0 and PDN pass weak 1
The following techniques are used to optimize the static CMOS circuits
a. Bubble pushing:
A NAND gate is equivalent to an OR gate with inverted inputs and a NOR gate is
equivalent to an AND gate with inverted inputs. This is called bubble pushing.
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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5

b. Compound gates:
Static CMOS also efficiently handles compound gates computing various inverting
combinations of AND/OR functions in a single stage.
The function F = AB +CD can be computed with an AND-OR INVERT- 22 (AOI22)
gate and an inverter, as shown in Figure.

c. Skewed gates:
w.k.t βp = βn allows the load capacitance to charge and discharge in equal times by
providing equal time and sink capabilities.
Inverted with different beta ratios βp /βn are called skewed inverters.

If βp /βn > 1, the inverter is HI-skewed

βp /βn < 1, the inverter is LO-skewed
βp /βn = 1, the inverter is Unskewed

High-skew gates favor to rising output and Low-skew gates favor to falling output. This
favoring is done by decreasing the size of the non-critical transistors.
Example

Problem :
Draw the static CMOS circuit for the given function? Refer class Note

7. Transmission Gate:
The CMOS transmission gate consists of one nMOS and one pMOS transistor, connected
in parallel.The gate voltages applied to these two transistors are also set to be
complementary signals.
Thus, the CMOS TG operates as a bidirectional switch between the nodes A and B which is
controlled by signal C.
If the control signal C is
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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
logic-high, i.e., equal to VDD, then both transistors are turned on and provide a low-
resistance current path between the nodes A and B.
low, then both transistors will be off, and the path between the nodes A and B will
be an open circuit. This condition is also called the high-impedance state.

Fig: Four different representations of CMOS Transmission Gate (TG)

TGs are efficient in implementing some functions such as multiplexers, XORs, XNORs,
latches, and Flip-Flops.

Advantages:
 Lesser number of transistors when compared to static CMOS
 It will pass both strong 0 and strong 1
Problems:
Design a basic gates (AND, OR, NAND, NOR, XOR, XNOR, 2:1 Mux ) using
transmission gates. Refer class notes

8. Pass Transistor Logic:

In pass transistor logic, only NMOS are used to design the logic. The input signals are
applied to both the gate and source/drain terminals. Depending upon the gate value it passes
logic from input node to output node.

Here, the switch is considered closed when the voltage applied to the gate is logic high, and
it is considered open when the voltage applied to the gate is logic low. The output (Y) is logic
high when the input (A) is logic high and the switch-control signal (B) is logic high.
Problems:
Design a basic gates (AND, OR, NAND, NOR, XOR, XNOR, 2:1 Mux ) using PTL.
Refer class notes

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
9. Differential Pass Transistor Logic OR Complementary Pass Transistor Logic :
In the complementary pass transistor logic (CPL), the inputs are applied both in the true
and complement form and the output are also evaluated in both true and complement form
using pass transistor logic. Figure shows the general structure of CPL.

DPTL employs differential signaling, which improves noise immunity and reduces
power consumption. This makes DPTL highly suitable for high-speed and low-power
applications. By utilizing differential pairs, DPTL delivers robust performance in noisy
environments and at high frequencies.
Problems:
1. Design a AND/NAND gate using CPL
2. Design a OR/NOR gate using CPL
3. Design a EXOR/EXNOR gate using CPL
Answer: Refer class notes

10. Ratioed Circuits:

It uses weak pull-up and strong pull-down devices. This will reduce the input capacitance and
improve logical effort.
It also dissipates static power while the output is low.
It can be designed using Pseudo –NMOS Logic.
Pseudo –NMOS Logic:
In this, the pull down network is same as a static CMOS and the pull up network is replaced
with a single PMOS transistor which is grounded. So the PMOS transistor is always ON. The
following figure shows the general structure of Pseudo NMOS.

Using this arrangement, the area and input capacitance problem can be solved.
Advantages:
 Less number of transistors
 Low input capacitance
Disadvantages:
 PMOS always ON, so high static power dissipation.
 Contention problem will occur.
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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
Problems:
1. Realize a  b c  d  using pseudo NMOS.
2. Realize ab  cd  efg  using pseudo NMOS.
Answer: Refer class notes

11. Dynamic Logic Gates:

Inorder to overcome the drawbacks present in ratioed circuits, we replace single PMOS
transistor in the ratioed circuits by using a clocked (ф) pullup transistor becomes dynamic
circuits.

Fig1: Dynamic circuit

Dynamic circuits operated in two modes,

a) Precharge mode
During precharge CLK (ф) = 0, so the clocked PMOS is ON, produce the output
Y=1.
b) Evaluation mode
During Evaluation CLK (ф) = 1, so the clocked PMOS is OFF, produce the
output high or low depending upon the input A.

Fig2: Precharge and evaluation of dynamic circuit

Problems in dynamic circuits and its solutions:

In Fig1, during precharge if the input A=1 means contention problem will takes place
because both the networks will be ON. To overcome the contention problem, an extra
clocked evaluation transistor can be added to the bottom of the PDN called foot transistor.

Fig3: Dynamic circuit with footed transistor

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
Now if the input A=1 during precharge, the foot transistor will be in OFF condition avoids
contention problem produce the output to logic HIGH.

In Fig3, during Evaluation CLK(ф) =1, if the input A=1, produce the output as logic 0.
Later if the input A falls 1 to 0 both the networks will be in OFF thus the output floats,
staying 0 rather than rising 1. This is called monotonicity problem. To overcome the
monotonicity problem, by placing a static CMOS inverter between dynamic gates called
domino CMOS logic.

Fig4: Monotonicity problem

Domino CMOS Logic:

It is slightly modified version of the dynamic CMOS logic circuit. In this case, a static
CMOS inverter is connected at the output of each dynamic CMOS logic block shown in Fig5.
This converts the monotonically falling output into monotonically rising signal suitable for the
next gate.

Fig5. Domino CMOS Logic Circuit

In the Precharge phase CLK(ф)=0, the outputs of the dynamic CMOS logic circuits are
precharged to logic High and the output of the static inverter is logic Low.
In the Evaluation phase CLK(ф)=1, the outputs of the dynamic CMOS logic circuits
can either go to logic Low or remain at logic High. Consequently, the static inverter can make
only a 0 to 1 transition, cannot make 1 to 0 transitions irrespective of the input logic.

Advantages:
 Low input capacitance
 No contention problem
 Zero static power dissipation
Disadvantages:
 Require careful clocking
 Sensitive to noise

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ECE EC3352 – VLSI AND CHIP DESIGN SEMESTER 5
Problems:
1. Realize the given function ABC  DEF using
a. Unfooted dynamic circuit OR Dynamic circuit
b. Footed dynamic circuit
c. Domino logic circuit
Answer: Refer class notes

12. Content Beyond Syllabus:

RC Delay Model: In this model, the transistor act as switch series with resistor. And also
transistor has its own gate and diffusion capacitance.
For getting equal rise and fall time, choose
The effective resistance of NMOS =R
The effective resistance of PMOS =2R (since mobility of PMOS is lower than NMOS)
Figure shows the k-width transistor

k-width PMOS and NMOS transistor

Here C is proportional to width and R is inversely proportional to width.

Example:

Equivalent width of Inverter, 2-input NAND and NOR

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