Digital Design I

Lecture 9 – Synchronous Sequential Logic

Asst. Prof. Dr. Ertuğrul SAATÇI

Sequential Circuits
 A sequential circuit consists of a combinational circuit to which
storage elements are connected to form a feedback path.

 The storage elements are devices capable of storing binary

information.

 The binary information stored in storage elements at any given

time defines the state of the sequential circuit at that time.

1
 Sequential Circuits
 The binary information received from external inputs, together
with the present state of the storage elements determine
• the binary value of the outputs, and
• the condition for changing the state in the storage elements.

 The outputs in a sequential circuit are a function not only of the

inputs, but also of the present state of the storage elements.

 The next state of the storage elements is also a function of

external inputs and the present state.

 A sequential circuit is specified by a time sequence of

• inputs,
• outputs and
• internal states.

Sequential Circuits
 There are two main types of sequential circuits and their
classification depends on the timing of signals:
• A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its signals at
discrete instants of time.
• An asynchronous sequential circuit depends upon the
input signals at any instant of time and the order in which
the inputs change.
 The storage elements commonly used are time-delay
devices.

 Synchronization is achieved by a timing device called a clock

generator that provides a periodic train of clock pulses.

2
 Sequential Circuits
 Synchronous sequential circuits that use clock pulses in the
inputs of storage elements are called clocked sequential circuits.
 The storage elements used in clocked sequential circuits are
called flip-flops.

Sequential Circuits
 The outputs can come either from the combinational circuit or
from the flip-flops or both.

 The flip-flops receive their inputs from the combinational circuit

and also from a clock signal with pulses that occur at fixed
intervals of time.

 The state transition of the flip-flops occurs only at

predetermined time intervals dictated by the clock pulses.

3
 Latches
 A flip-flop circuit can maintain a binary state indefinitely until
directed by an input signal to switch states.

 The most basic types of flip-flops operate with signal levels and
are referred to as latches.

 The latches are the basic circuits from which all flip-flops are
constructed.

 Although latches are useful for storing binary information and

for the design of asynchronous sequential circuits, they are not
practical for use in synchronous sequential circuits.

Latches
SR Latch
 SR latch is a circuit with two cross-coupled NOR gates or two
cross-coupled NAND gates.

 It has
• two inputs labeled S for set and R for reset,
• two outputs labeled Q and its complement Q’.

 SR latch has two useful states:

• When output Q = 1 and Q’ = 0, it is in the set state,
• When Q = 0 and Q’ = 1, it is in the reset state,
• When both inputs are equal to 1 at the same time, an
undefined state with both outputs equal to 0 occurs,
• Under normal conditions, both inputs of the latch remain at
0 unless the state has to be changed.

4
 Latches
SR Latch
 The SR latch constructed with two cross-coupled NOR gates:

 The application of a momentary 1 to the S input causes the

latch to go to the set state.
 The S input must go back to 0 before any other changes to
avoid the occurrence of the undefined state.
 When both inputs are equal to 0 at the same time, the latch
can be in either the set or the reset state, depending on which
input was most recently a 1.

Latches
SR Latch
 The SR latch constructed with two cross-coupled NAND gates:

 It operates with both inputs normally at 1 unless the state of the

latch has to be changed.
 When both inputs are equal to 0 at the same time, an undefined
state with both outputs equal to 1 occurs.
 The input signals for the NAND latch require the complement of
those values used for the NOR latch.
 Thus, it is sometimes referred to as an S’-R’ latch.

10

5
 Latches
SR Latch
 The operation of the basic SR latch can be modified by providing an
additional control input that determines when the state of the latch can
be changed.

 Indeterminate condition places 0’s on both inputs of the basic

SR latch, which places it in the undefined state.
 When the control input goes back to 0 from 1, the next state
cannot be determined conclusively as it depends on whether the S
or R inputs goes to 0 first.
 The indeterminate condition makes this circuit difficult to manage
and it is seldom used in practice.

11

Latches
D Latch
 One way to eliminate the undesirable condition of the indeterminate
state in the SR latch is to ensure that inputs S and R are never equal to
1 at the same time.
 This is done by the D latch:

 D latch has only two inputs: D (Data) and C (Control).

 The D input goes directly to the S input and its complement is applied to
the R input.
 As long as the control input is at 0, the SR latch has both inputs at the 1
level and the circuit cannot change state regardless of the value of D.

12

6
 Latches
D Latch
 The binary information present at the data input of the D latch is
transferred to the Q output when the control input is enabled.
 The output follows changes in the data input as long as the control
input is enabled. Therefore, this circuit is often called a transparent
latch.
 The graphic symbols for various latches:

 In the case of a NAND gate latch, bubbles are added to the inputs to
indicate that setting and resetting occur with logic 0 signal.

13

Flip-Flops
 The state of a latch or flip-flop is switched by a change in the
control input.

 This momentary change is called a trigger and the transition it

causes is said to trigger the flip-flop.

 The D latch with pulses in its control input is essentially a flip-

flop, that is triggered every time the pulse goes to the logic 1
level.

 As long as the pulse input remains in this level, any changes in

the data input will change the output and the state of the latch.

14

7
 Flip-Flops
 When latches are used for the storage elements, a serious
difficulty arises:
• The state transitions of the latches start as soon as the clock
pulse changes to the logic 1 level.
• The new state of a latch appears at the output while the
pulse is still active.
• This output is connected to the inputs of the latches through
the combinational circuit.
• If the inputs applied to the latches change while the clock
pulse is still in the logic 1 level, the latches will respond to
new values and a new output state may occur.
• The result is an unpredictable situation since the state of
latches may keep changing for as long as the clock pulse
stays in the active level.

15

Flip-Flops
 The problem with the latch is that is
responds to a change in the level of
a clock pulse.

 A positive level response in the

control input allows changes in the
output, when the D input changes
while the clock pulse stays at logic 1.

 The key to the proper operation of a

flip-flop is to trigger it only during a
signal transition.

 The positive transition (from 0 to 1)

is defined as the positive-edge and
the negative transition (from 1 to 0)
as the negative-edge.

16

8
 Flip-Flops
 There are two ways that a latch can be modified to form a flip-
flop:
1. To employ two latches in a special configuration that isolates
the output of the flip-flop from being affected while its input
changing.

2. To produce a flip-flop that triggers only during a signal

transition (from 0 to 1 or from 1 to 0), and is disabled during
the rest of the clock pulse duration.

17

Flip-Flops
Edge-Triggered D Flip-Flop
 The construction of a D flip-flop with two D latches and an inverter:

 The first latch is called the master and the second the slave.
 The output Q of the master-slave D flip-flop can change only at the
negative-edge of the controlling clock (designated as CLK).
• When CLK is 0, only the slave latch is enabled and its output Q is
equal to the master output Y.
• When CLK changes to 1, the slave latch become disabled and the
data from the external D input is transferred to the master output Y.
• When CLK returns to 0, the master is disabled and slave is enabled
and the value of Y is transferred to the flip-flop output Q.

18

9
 Flip-Flops
Edge-Triggered D Flip-Flop
 The output of the flip-flop shown in the previous slide, can change
only during the transition of the clock from 1 to 0 (negative-edge
triggered).

 It is possible to design a positive-edge triggered master-slave D flip-

flop by adding an additional inverter:

19

Flip-Flops
Edge-Triggered D Flip-Flop
 Another 1
construction of
an edge- 1
triggered D Reset
flip-flop using State
three SR 0
latches. 0
1
0 1
 Two latches
respond to the 1 1
external D
(data) and CLK 1 0
1
(clock) inputs,
while the third
latch provides 1 0
the outputs for 0
1
the flip-flop.

20

10
 Flip-Flops
Edge-Triggered D Flip-Flop
 When CLK=0, the S and R inputs of the output latch are maintained
at logic 1 level. This causes the output to remain in its present state.

 Input D may be equal to 0 or 1.

• If D=0 when CLK becomes 1, R changes to 0 and flip-flop goes to
the reset state making Q=0.
• If D=1 when CLK becomes 1, S changes to 0 and flip-flop goes to
the set state making Q=1.

 If there is a change in the D input while CLK=1, terminal R remains

at 0. Thus, the flip-flop is locked out and is unresponsive to further
changes in the input.

 When CLK returns to 0, R goes to 1, placing the output latch in the

quiescent condition without changing the output.

 In summary, when the CLK input makes a positive transition,

the value of D is transferred to Q.

21

Flip-Flops
Edge-Triggered D Flip-Flop
 If D=1 when 0
CLK becomes 1,
S changes to 0 1 0
and flip-flop Set
goes to the set
state making State
1
Q=1. 1
1 0
 Any change in 0 1
D while CLK=1 1 0 0
does not affect
the output. 1
0
 This type of
flip-flop 1
responds to the 1
transition from 0
0 to 1 and
nothing else.

22

11
 Flip-Flops
Edge-Triggered D Flip-Flop
 There is a minimum time, called setup time, for which the D input
must be maintained at a constant value prior to the occurrence of
the clock transition.

 There is a minimum time, called the hold time, for which the D
input must not change after the application of the positive transition
of the clock.

 The propagation delay time of the flip-flop is defined as the time

interval between the trigger edge and the stabilization of the output
to a new state.

23

Flip-Flops
Edge-Triggered D Flip-Flop
 The graphic symbol for the edge-triggered D flip-flop:

 The dynamic indicator, arrowhead-like symbol in front of the letter C,

denotes the fact that the flip-flop responds to the edge transition of
the clock.

 A bubble outside the block adjacent to the dynamic indicator

designates a negative-edge triggering.

24

12
 Flip-Flops
Other Flip-Flops
 The most economical and efficient flip-flop constructed by
interconnecting the smallest number of gates is the edge-triggered
D flip-flop.

 Other types of flip-flops can be constructed by using the D flip-flop

and external logic.

 Two flip-flops widely used in the design of digital systems are the JK
and T flip-flops.

 There are three operations that can be performed with a flip-flop:

• Set it to 1
• Reset it to 0
• Complement its output

25

Flip-Flops
Other Flip-Flops (JK Flip-Flop)
 The J-K flip-flop, constructed with a D flip-flop and gates, performs
all three operations.

D = JQ’+K’Q
• When J=1 and K=0, D=Q’+Q=1, next clock edge sets the output to 1.
• When J=0 and K=1, D=0, next clock edge resets the output to 0.
• When J=1 and K=1, D=Q’, next clock edge complements the output.
• When J=0 and K=0, D=Q, next clock edge leaves the output unchanged.

26

13
 Flip-Flops
Other Flip-Flops (T Flip-Flop)
 The T (toggle) flip-flop is a complementing flip-flop and can be
obtained from
 a tied-input JK flip-flop
• When T=0 (J=K=0) a clock edge does not change the output
• When T=1 (J=K=1) a clock edge complements the output
 a D flip-flop with an XOR gate, D=TQ=TQ’+T’Q
• When T=0, then D=Q, there is no change in the output.
• When T=1, then D=Q’, the output complements.

27

Flip-Flops
Characteristic Tables
 A characteristic table defines the logical properties of a flip-flop by
describing its operation in tabular form.

 They define the next state as a function of the inputs and present
state.

 Q(t) refers to the present state prior to the application of a clock

edge, while Q(t+1) is the next state one clock period later.

JK Flip-Flop D Flip-Flop T Flip-Flop

J K Q(t+1) D Q(t+1) T Q(t+1)
0 0 Q(t) No change 0 0 Reset 0 Q(t) No change
0 1 0 Reset 1 1 Set 1 Q’(t) Complement
1 0 1 Set Q(t+1)=D
1 1 Q’(t) Complement

28

14
 Flip-Flops
Characteristic Equations
 The logical properties of a flip-flop as described in the characteristic
table can be expressed also algebraically with a characteristic
equation.
 For D flip-flop
Q(t+1) = D

 For JK flip-flop
Q(t+1) = JQ’+K’Q

 For T flip-flop
Q(t+1) = TQ = TQ’+T’Q

29

Flip-Flops
Direct Inputs
 Some flip-flops have asynchronous inputs that are used to force the
flip-flop to a particular state independent of the clock.
• The input that sets the flip-flop to 1 is called preset or direct
set
• The input that clears the flip-flop to 0 is called clear or direct
reset

 When power is turned on in a digital system, the state of the flip-

flops is unknown.

 The direct inputs are useful for bringing all flip-flops in the system
to a known starting state prior to the clocked operation.

30

15
 1 0
Flip-Flops 1
Direct Inputs
1 1 0
 A positive edge- 0 1
triggered D flip-flop
with asynchronous 1
reset:
0
 When the reset input is
0, it forces output Q’ to 1
stay at 1, which clears
output Q to 0, thus 0
resetting the flip-flop. 0

 Two other connections

from the reset input
ensure that the S input
of the third SR latch
stays at logic 1
regardless of the values
of D and CLK. The bubble
indicates that
the reset is
active at the
logic 0 level

31

16