Digital Design I

Lecture 8 – Combinational Logic

Asst. Prof. Dr. Ertuğrul SAATÇI

Decoders
 Discrete quantities of information are represented in digital
systems by binary codes.

 A decoder is a combinational circuit that converts binary

information from n input lines to a maximum of 2n unique
output lines and is called n-to-m-line decoders, where m ≤ 2n.

 Their purpose is to generate the 2n (or fewer) minterms of n

input variables.

 The name decoder is also used in conjunction with other code

converters such as a BCD-to-seven-segment decoder.

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 Decoders
Example
 Consider the 3-to-8-line
decoder circuit.

 The three inputs are decoded

into eight outputs, each
representing one of the
minterms of the three input
variables.

 The three inverters provide

the complement of the inputs,
and each one of the eight AND
gates generates one of the
minterms.

 A particular application of 3-
to-8-line decoder is binary-to-
octal conversion.
3-to-8-line decoder

Decoders
Example
 For each possible input combination, there are seven outputs that
are equal to 0 and only one that is equal to 1.
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
 The output whose value is 1 represents the minterm equivalent of
the binary number presently available in the input.

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 Decoders
Example
 Some decoders are constructed with NAND gates, since it is more
economical to generate the decoder minterms in their
complemented form.
 Furthermore, decoders include one or more enable inputs to
control the circuit operation.

 The truth table for 2-to-4-line decoder with an enable input and its
circuit implementation with NAND gates (the circuit operates with
complemented outputs):
E A B D0 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

Decoders
Demultiplexer
 In general, a decoder may operate with complemented or
uncomplemented outputs and the enable input may be activated
with a 0 or a 1 signal.

 A decoder with enable input can function as demultiplexer and

therefore it is referred to as a decoder/demultiplexer.
• A demultiplexer is a circuit that receives information from a
single line and directs it to one of 2n possible output lines.
• The selection of a specific output is controlled by the bit
combination of n selection lines.

 The previous 2-to-4-line decoder with enable input can function as

a 1-to-4-line demultiplexer when E is taken as a data input line and
A and B are taken as the selection inputs.

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 Decoders
 Enable inputs are a convenient feature for interconnecting two or
more standard components for the purpose of expanding the
component into a similar function with more inputs and outputs.

 Two 3-to-8-line decoders with enable inputs connected to form a 4-

to-16-line decoder. When
• w=0, the top decoder generates minterms 0000 to 0111.
• w=1, the bottom decoder generates minterms 1000 to 1111.

Decoders
Combinational Logic Implementation
 Since any Boolean function can be expressed in sum of minterms,
one can use a decoder to generate the minterms and an external OR
gate to form the logical sum.

 Any combinational circuit with n inputs and m outputs can be

implemented with an n-to-2n-line decoder and m OR gates.

 The procedure for implementing a combinational circuit with

decoders and OR gates:
1. Express the Boolean function of the circuit in sum of minterms.
2. Choose a decoder that generates all the minterms of the input
variables.
3. Select the inputs to each OR gate from the decoder outputs
according to the list of minterms of each function.

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 Combinational Logic Implementation
Example
 Implementation of a full adder with a decoder:

Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8-

line decoder.
S(x,y,z) = (1,2,4,7)
C(x,y,z) = (3,5,6,7)

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Combinational Logic Implementation

Example
 If the number of minterms in a function is greater than 2n/2, then
F’ can be expressed with fewer minterms.

 In such a case, it is advantageous to use a NOR gate to sum the

minterms of F’, while the output of NOR gate complements this sum
and generates the normal output F.

 If NAND gates are used for the decoder, the external gates must be
NAND gates instead of OR gates.
 This is because a two-level NAND gate circuit implements a sum
of minterms function and is equivalent to a two level AND-OR
circuit.

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 Encoders
 An encoder, performing the inverse operation of a decoder, has 2n
(or fewer) input lines and n output lines.

 The output lines generate the binary code corresponding to the

input value.

 An encoder can be implemented with OR gates whose inputs are

determined directly from the truth table.

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Encoders
Example
 Octal-to-binary encoder has eight inputs (one for each octal digit)
and three outputs that generate the corresponding binary number.
 It is assumed that only one input has a value of 1 at any time.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z The encoder can be
1 0 0 0 0 0 0 0 0 0 0 implemented with
three OR gates:
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 z = D1+D3+D5+D7
0 0 0 1 0 0 0 0 0 1 1 y = D2+D3+D6+D7
0 0 0 0 1 0 0 0 1 0 0 x = D4+D5+D6+D7
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

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 Encoders
Example
 The ambiguity need to be resolved:
1. The encoder has the limitation that only one input can be active at
any given time.
 If two inputs are active simultaneously, the output produces an
undefined combination.
 To resolve this, encoder circuit must establish an input priority
to ensure that only one input is encoded (higher priority to
inputs with higher subscript numbers).

2. When all the inputs are 0, an output with all 0’s is generated. This
output is the same as when D0 is equal to 1.
 Providing one more output indicating that at least one input is
1, can resolve this problem.

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Encoders
Priority Encoder
 A priority encoder is an encoder circuit that includes the priority
function.

 The higher the subscript number, the higher the priority of the
input.

 The operation of the priority encoder:

• If two or more inputs are equal to 1, the input having the
highest priority will take precedence.
• If all inputs are 0, there is no valid input and V, valid bit
indicator, is equal to 0.

 When V equals to 0, the outputs are not inspected and are specified
as don’t-care conditions.

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 Encoders
Priority Encoder
 The truth table of a four input priority encoder:

Inputs Outputs Inputs Outputs

D0 D1 D2 D3 x y V D0 D1 D2 D3 x y V
0 0 0 0 X X 0 1 0 0 0 0 0 1
0 0 0 1 1 1 1 1 0 0 1 1 1 1
0 0 1 0 1 0 1 1 0 1 0 1 0 1
0 0 1 1 1 1 1 1 0 1 1 1 1 1
0 1 0 0 0 1 1 1 1 0 0 0 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 0 1 1 1 1 0 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 1

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Encoders
Priority Encoder
 The K-maps for simplifying outputs x and y:

x = D2+D3 y = D3+D1D2’
The output V is an OR function of all input variables.
V = D0+D1+D2+D3

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 Encoders
Priority Encoder
 Logic diagram of 4-input Priority Encoder:

x = D2+D3
y = D3+D1D2’
V = D0+D1+D2+D3 = D0+D1+x

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Multiplexers
 A multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line.
 The selection of a particular input line from 2n input lines is controlled
by a set of n selection lines.
 A 2-to-1-line multiplexer has two data input lines I0 I1, one output
line Y, and one selection line S.

 It acts like an electronic switch that selects one of two sources.

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 Multiplexers
 Logic diagram and function
table of a 4-to-1 line
multiplexer:

 Each of the four inputs, I0

through I3, is applied to one
input of an AND gate.

 Selection lines S1 and S0 are

decoded to select a particular S1 S0 Y
AND gate.
0 0 I0
0 1 I1
 The outputs of the AND gates
are applied to a single OR gate 1 0 I2
that provides the 1 line output. 1 1 I3

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Multiplexers
 A multiplexer is also called a data selector, since it selects one
of many inputs.

 In general, a 2n-to-1-line multiplexer is constructed from an

n-to-2n decoder
• By adding to it 2n input lines, one to each AND gate.
• The outputs of the AND gates are applied to a single OR
gate.

 The size of a multiplexer is specified by the number 2n of its

data input lines and the single output line.

 The n selection lines are determined from the 2n data lines.

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 Multiplexers
 As in decoders, multiplexers
may have an enable input
to control the operation of
the unit.

 Multiplexer circuits can be

combined with common
selection inputs to provide
multiple-bit selection logic.

 The circuit in figure has 4

multiplexers, each capable
of selecting one of two input
lines.
A quadruple 2-to-1-line
multiplexer

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Multiplexers
Boolean Function Implementation
 A decoder can be used to implement Boolean functions by
employing external OR gates, while Multiplexer is a decoder that
includes the OR gate within the unit.

 This provides a method of implementing a Boolean function of n

variables with a multiplexer that has n selection inputs and 2n
data inputs, one for each minterm.

 A more efficient method for implementing a Boolean function of n

variables with a multiplexer that has n–1 selection inputs:
• The first n–1 variables of the function are connected to the
selection inputs of the multiplexer
• The remaining single variable of the function is used for the
data inputs.

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 Boolean Function Implementation
Example 1
 Consider the Boolean function of three variables:
F(x,y,z) = (1,2,6,7)
The function can be implemented with a 4-to-1-line MUX.

 The two variables x

and y are applied
to selection lines.

 The values for the

data input lines are
determined from
the truth table of
the function.

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Boolean Function Implementation

Procedure
 The general procedure for implementing any Boolean function of
n variable with a MUX with n-1 selection inputs and 2n-1 data
inputs:
1. Obtain the truth table for the Boolean function.

2. Apply the first n-1 variables in the table to the selection

inputs of the MUX.

3. For each combination of the selection variables, evaluate the

output as a function of the last variable. This function can be:
0, 1, the variable or the complement of the variable.

4. Apply these values to the data inputs in the proper order.

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 Boolean Function Implementation
Example 2
 Consider the Boolean function of four variables:
F(A,B,C,D) = (1,3,4,11,12,13,14,15)

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Three State Gates

 A three-state gate is a digital circuit that exhibits three states.

 Two of the states are signals equivalent to logic 1 and 0 as in a

conventional gate, while the third state is a high-impedance state,
which behaves like an open circuit disconnecting the output.

 Three-state gates are most commonly used as the buffer gates.

 When the control input is equal to 1, the output is enabled and the
gate behaves like a conventional buffer, with the output equal to
the normal input.

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 Three State Gates
 A multiplexer can be constructed with three-state gates.
 Because of the high-impedance state, a large number of three
state gate outputs can be connected with wires to form a
common line without endangering loading effects.

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