Course Code: 20EC0411 R20

SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY :: PUTTUR (AUTONOMOUS)

Siddharth Nagar, Narayanavanam Road – 517583

QUESTION BANK (DESCRIPTIVE)

Subject with Code: LDICA (20EC0411) Course & Branch: B.Tech – ECE
Year &Sem: II-B.Tech & II-Sem Regulation: R20

UNIT –I
OP AMP CHARACTERISTICS AND LINEAR APPLICATIONS
1 a) Explain the operation of an Instrumentation amplifier with neat sketch. [L2][CO2] [6M]
b) Define Virtual ground Property. [L1][CO1] [2M]
c) Determine the output voltage of a differential Amplifier for the input voltages [L3][CO1] [4M]
of 300µV & 240µV.The Differential gain of the amplifier is 5000.the value of
the CMRR is 100
2 a) Discuss about DC and AC characteristics of an ideal OP-AMP with relevant [L2][CO1] [6M]
expressions.
b) Differentiate Open-Loop & Closed Loop Op Amp Configurations. [L3][CO1] [6M]
3 Draw the circuit and explain the working of the following.
a) Voltage to current converter. [L3][CO2] [6M]
b) Current to voltage converter. [L3][CO2] [6M]
4 a) Describe about the block diagram of Op-Amp. [L1][CO1] [8M]
b) Write the features of 741 op-amp. [L3][CO1] [4M]
5 a) Draw and Explain about the Inverting Amplifier. [L2][CO1] [6M]
b) Draw and Explain about the Non-Inverting Amplifier. [L2][CO1] [6M]
6 a) Analyze the expression of Inverting Amplifier and draw its input and output [L4][CO1] [8M]
Wave forms.
b) List out the applications of Comparator. [L1][CO2] [4M]
7 Draw and analyze the expressions of the following.
a) Differentiator. [L4][CO2] [6M]
b) Integrator. [L4][CO2] [6M]
8 Explain about the following.
a) Inverting A.C Amplifier. [L2][CO2] [6M]
b) Non-Inverting A.C Amplifier. [L2][CO2] [6M]
9 a) Explain about the operation of sample and hold circuit with relevant [L2][CO2] [6M]
Waveforms.
b) Discuss about Schmitt trigger with neat sketches. [L3][CO2] [6M]
10 Explain the followings with neat sketch.
a) Inverting Mode comparator. [L3][CO2] [6M]
b) Non-Inverting Mode Comparator. [L3][CO2] [6M]
Course Code: 20EC0411 R20
UNIT –II
ACTIVE FILTERS, OSCILLATORS & TIMERS
1 a) Explain the operation of Astable multivibrator using 555 timer and also derive [L2][CO2] [8M]
the expression for frequency of oscillation.
b) Write the application of multivibrator. [L1][CO2] [4M]
2 a) With the help of schematic diagram explain how 555 timer can be used as [L2][CO3] [8M]
Monostable multivibrator.
b) Draw the pin diagram of 555 timer. [L1][CO3] [4M]
3 a) Explain about the operation of Wien Bridge Oscillator using Op-Amp [L3][CO2] [6M]
b) Define Oscillator and List out the types of the oscillators. [L1][CO2] [6M]
4 a) Explain about the operation of RC Phase shift Oscillator using Op-Amp [L2][CO2] [8M]
b) What are the disadvantages of RC phase shift Oscillator? [L1][CO2] [4M]
5 a) Draw the circuit of a 1st order low pass Butterworth filter and discuss its [L2][CO1] [6M]
transfer functions.
b) Compare the low pass and high pass filters. [L1][CO1] [6M]
6 a) Explain the functional block diagram of 555 timers. [L2][CO3] [8M]
b) Draw the frequency response curve for a band-pass filter. [L1][CO2] [4M]
7 a) Design the first order high pass filter and discuss its frequency responses. [L2][CO2] [8M]
b) Define Filter and Illustrate the Types of filters. [L1][CO1] [4M]
8 a) Draw and Explain narrow band pass filter and discuss its frequency responses. [L2][CO1] [6M]

b) Design wide band pass filter. [L2][CO2] [6M]

9 a) Draw the circuit diagram of the wide Band-Reject Filter and explain its [L2][CO2] [8M]
operation.
b) Compare Band pass and Band-Reject Filter. [L2][CO2] [4M]
10 a) Discuss about All pass filter with neat sketch. [L2][CO2] [8M]
b) Discuss about the Discharge and control voltage pin role in the 555 timer. [L2][CO3] [4M]
Course Code: 20EC0411 R20
UNIT –III
PHASE LOCKED LOOPS, CONVERTERS & CMOS LOGIC

1 a) Draw and Explain about the block schematics of PLL. [L2][CO4] [8M]
b) Define PLL and List the applications of PLL. [L3][CO4] [4M]
2 a) Draw and Explain about the Monolithic IC 565. [L2][CO3] [6M]
b) Compare CMOS, TTL Logic Families [L2][CO4] [6M]
3 a) Draw and explain the weighted resistor DAC. [L1][CO4] [6M]
b) Explain about ladder type DAC. [L1][CO4] [6M]
4 Draw and explain about R-2R DAC with an example. [L1][CO4] [12M]
5 Explain about counter type ADC with neat block diagram. [L2][CO4] [12M]
6 a) The basic step of a 9-bit DAC is 10.3 mV. If “000000000” represents 0V. [L1][CO4] [3M]
What output is produced if the input is “101101111”?
b) Explain about flash type ADC. [L2][CO4] [9M]
7 Draw and explain successive approximation type ADC with an [L1][CO4] [12M]
Example.
8 Draw the circuit diagram of Dual Slope ADC and explain its working with [L1][CO4] [12M]
neat sketches.
9 a) Draw the circuit diagram of basic CMOS gate and explain its operation. [L3][CO4] [6M]
b) Compare CMOS, TTL and ECL logic families. [L2][CO4] [6M]
10 a) Discuss about low voltage CMOS and Interfacing. [L2][CO4] [6M]
b) Explain in detail about basic ECL logic circuit. [L2][CO4] [6M]
Course Code: 20EC0411 R20
UNIT –IV
HARDWARE DESCRIPTION LANGUAGES
1 a) Explain the various data types supported by VHDL. Give the necessary [L2][CO5] [6M]
examples.
b) Explain about VHDL program structure. [L2][CO5] [6M]
2 a) Explain about functions and procedures with an example. [L2][CO5] [6M]
b) Explain about libraries and packages. [L2][CO5] [6M]
3 a) Discuss about behavioral design element with an example. [L2][CO5] [6M]
b) Design the logic circuit and write a data-flow style VHDL program for the [L3][CO6] [6M]
following function. F (P) = ΣA, B, C, D (1,5,6,7,9,13) + d (4,15).
4 Draw and explain in detail about VHDL design flow. [L3][CO5] [12M]
5 a) Write about structural design elements with an example. [L2][CO5] [6M]
b) Write a VHDL entity and Architecture for the following function. [L2][CO5] [6M]
F(x) = (a + b) (c+d) Also draw the relevant logic diagram.
6 Design the logic circuit and write VHDL program for the following function. [L3][CO6] [12M]
F(X) = Σ A, B, C, D (0, 2, 5, 7, 8, 10, 13, 15) + d (1, 6, 11).
7 Design the logic circuit and write VHDL program for the following function. [L3][CO6] [12M]
F(Y) = Π A, B, C, D (1, 4, 5, 7, 9, 11, 12, 13, 15).
8 Design a logic circuit for 4-bit parallel adder and write the VHDL code in [L3][CO6] [12M]
structural style by considering full adder as a component.
9 Explain in detail different modeling styles of VHDL with suitable examples. [L2][CO5] [12M]
10 a) What is the importance of time dimension in VHDL and explain. [L2][CO5] [6M]
b) Explain the behavioral design elements of VHDL. [L2][CO5] [6M]
Course Code: 20EC0411 R20
UNIT –V
COMBINATIONAL & SEQUENTIAL LOGIC DESIGN PRACTICES
1 a) Design a 4 to 16 decoder with 74×138 IC’s. [L3][CO6] [6M]
b) Write a VHDL program for the above design. [L2][CO6] [6M]
2 a) Design a Full adder with Half adder’s logic circuit. [L3][CO6] [6M]
b) Write VHDL code for the above design in structural model. [L2][CO5] [6M]
3 a) Explain the operation of standard IC for 3X8 decoder with necessary truth [L2][CO6] [6M]
table and internal architecture.
b) Write a VHDL code for the above Decoder [L2][CO6] [6M]
4 a) With the help of logic diagram explain 74×157 multiplexer. [L2][CO6] [6M]
b) Write a VHDL code for the above IC in data flow style. [L2][CO5] [6M]
5 Design a priority encoder that can handle 32 requests. Use 74×148 and [L3][CO6] [12M]
required discrete gates. Provide the truth table and explain the operation.
6 a) Draw the logic symbol of 74 x 85, 4-bit comparator and write a VHDL code [L3][CO6] [6M]
for it.
b) Design a 16-bit comparator using 74×85 ICs. [L3][CO6] [6M]
7 a) Distinguish between the synchronous and asynchronous counters. [L4][CO6] [6M]
b) Design an 8-bit serial in and parallel out shift register. [L3][CO6] [6M]
8 a) Distinguish between latch and flip flop. Show the logic diagram for both. [L4][CO6] [6M]
Explain the operation with the help of function table.
b) Write a VHDL code for a D-flip flop in behavioral model. [L2][CO5] [6M]
9 a) Design a synchronous 4-bit up counter. [L3][CO6] [6M]
b) Write a VHDL code for the above design. [L2][CO5] [6M]
10 Design an 8 -bit serial in and serial out shift register and write a VHDL code [L3][CO6] [12M]
for it.

Prepared by:

1. Mr. J. Rajanikanth Associate Professor/ECE

2. Mr. C.Vijayabhaskar Associate Professor/ECE

3. Mr. K.D.Mohana Sundaram Associate Professor/ECE