CS3351- DIGITAL PRINCIPLES & COMPUTER

ORGANIZATION
(Common to B.E (CSE), B.Tech (AI&DS and IT))

Anna University Regulation: 2021

II Year/III Semester

Question Bank

Prepared By,

Mr.K.DINESH,AP/ECE
 4201-A.K.T Memorial College of Engineering & Technology

A.K.T Memorial College of Engineering&Technology

B.E- CSE,B.Tech (AI&DS,IT)

CS3351-DIGITAL PRINCIPLES AND COMPUTER
ORGANIZATION
UNIT 1
2 marks

1. What are basic properties of Boolean algebra?

The basic properties of Boolean algebra are commutative property, associative Property and
distributiveproperty.
2. State De Morgan's theorem.

De Morgan suggested two theorems that form important part of Boolean algebra. They are,

1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'

3. Reduce AB + (AC)' + AB’C (AB + C)

AB + (AC)' + AB’C (AB + C)

= AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' =A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C =A' + B + C' + B'
=A' + C' + 1
= 1 [A+ 1 =1]

4. Define duality property.

Duality property states that every algebraic expression deducible from the postulates Of Boolean
algebraremains valid if the operators and identity elements are interchanged. If the dual of an
algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by
0's and 0's by 1's.
5. What is a karnaugh map?
A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up
ofsquares, with each squares representing one minterm of the function.
6. Explain or list out the advantages and disadvantages of K-map method?
The advantages of the K-map method are

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It is a fast method for simplifying expression up to four variables.

It gives a visual method of logic simplification.
Prime implicants and essential prime implicants are identified fast.
Suitable for both SOP and POS forms of reduction.
It is more suitable for class room teachings on logic simplification.

The disadvantages of the K-map method are

i) Generally it is limited to six variable map (i.e) more then six variable involving expression are not
reduced.

ii) The map method is restricted in its capability since they are useful for simplifying only Boolean
expression represented in standard form

7. What are called don’t care conditions?

In some logic circuits certain input conditions never occur, therefore the Corresponding
output never appears. In such cases the output level is not defined, it can be either high or
low. These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care
conditions or incompletely specified functions.

8. Define combinational logic

When logic gates are connected together to produce a specified output for certain specified
combinationsof input variables, with no storage involved, the resulting circuit is called
combinational logic.

9. Explain the design procedure for combinational

The problem definition determines the number of available input variables & required O/P
variables. Assigning letter symbols to I/O variables Obtain simplified Boolean expression for each
O/P. Obtain the logic diagram.

10. Define half adder and full adder

The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the
addition of three bits is a full adder

11. What is a half-adder?

The combinational circuit that performs the addition of two bits is called a half-adder
12. What is a full-adder?
The combinational circuit that performs the addition of three bits is called a half-adder.
13. What is half-subtractor?
The combinational circuit that performs the subtraction of two bits is called a half-subtractor.
14. What is a full-subtractor?
The combinational circuit that performs the subtraction of three bits is called a half- subtractor.
15. What is binary parallel adder?
A binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel.

16. Define Decoder?

A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded
outputswhere the input and output codes are different.

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17. What is binary decoder?

A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of2n out puts lines.

18. Define Encoder?

An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary
codecorresponding to the input value.

19. What is priority Encoder?

A priority encoder is an encoder circuit that includes the priority function. In priority encoder,
if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will
take precedence.

20. Define multiplexer?

Multiplexer is a digital switch. If allows digital information from several sources to be routed
onto asingle output line

21. What do you mean by comparator?

A comparator is a special combinational circuit designed primarily to compare the relative
magnitude oftwo binary numbers.

22. Define carry propagation delay.

The sum and carry outputs of any stage cannot be produced until the input carry occurs, this
leads to atime delay in the addition process. This delay is knows as carry propagation delay.

23. What is BCD adder?

A BCD adder is a circuit that adds two BCD Digits and produces a sum digit also in BCD

24. Mention The Application Of Mux.

1. They can be used as a data selector
2. They can be used to implement combinational logic circuits.

25. Mention the Application Of Decoder

1. They can be used to implement combinational logic circuits.

2. It can be used to convert BCD into 7-segment code.

26. Define seven segment decoder.

Seven segment displays are used to give a visual indication of the outputs states.

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PART B

1. Solve following using K-map and boolean algebra:(i) F(A,B,C)=∑m(2,3)

(ii) F(A,B,C)=∑m(1,3,5,7) (iii)F(A,B,C)=∑m(0,4,1,3,6)
2. i) Find the maxterms for the expression F=AC’+ABC’+A’BC ii) Convert the given expression in
canonical SOPform Y = AC + AB + BC
3. Simplify the function using Karnaugh map and implement using minimum number of logic gates
.F = (2, 9, 10,12, 13) + D (1, 5, 14) what are the limitations of Karnaugh map.
4. Minimize the following function by K-map
Y’=A’BC’D’+A’BC’D+ABC’D’+ABC’D+AB’C
D+A’B’CD’.
5. Simplify the function F(w,x,y,z) = ∑m(2,3,12,13,14,15) using K-map method. Implement
thesimplified function using gates.
6. Simplify the following Boolean expression in (i) Sum-of-product (ii) Product-of-sum using
Karnaugh-map AC′+B′D+A′CD+ABCD
7. Discuss the need and working principle of Carry Look ahead adder.
8. Draw the circuit of a 3 bit binary subtractor and explain its operation with the help of an example.
9. Design a full/half adder and half/Full Subtractor circuit using NAND gates only
10. Design a combinational circuit to perform BCD addition.
11. Write note on 3 bit binary magnitude comparator.
12. i) Use a 8 x 1 MUX to implement the logic function F=∑m (0,1,2,3,4,10,11,14,15) ii)
F(A,B,C,D)= ∑m(1,3,4,11,12,13,14,15)
13. i) Design a 4-bit Binary to Excess-3 code converter. ii) Design a BCD Adder using two 4-bit
parallel binaryadder blocks and additional logic.
14. i) Design a priority encoder and explain its operation. ii) Implement full adder using suitable
decoder and additional logic.
15. Design a BCD to 7 segment decoder and implement it by using basic gates.
16. Implement the following using 8 to 1 Mux
F=(A, B, C, D) = A’BD’+ACD+B’CD+A’C’D. Also implement the function using 16 to 1 multiplexer
17. (i) Implement the following Boolean functions with a multiplexer:
F(w,x,y,z) = ∑ (2,3,5,6,11,14,15) (ii)Construct a 5 to 32 line decoder using 3 to 8 line
decoders and 2 to 4 line decoder.

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