Clock Tree Synthesis
Clock Tree Synthesis
• Global skew: the difference between max insertion delay and the
min insertion delay.it can be positive and negative local skew also
• max insertion delay: delay of the clock signal takes to propagate
to the farthest leaf cell in the design.
• min insertion delay: delay of the clock signal takes to propagate
to the nearest leaf cell in the design.
• Useful skew: if the clock is skewed intentionally to resolve setup
violations.
Network latency: The delay from the clock definition points(create_clock) to the flip-flop clock pins .
•
Set_clock_latency 0.8 [get_clocks clk_name1] ----> network latency
• Set_clock_latency 1.9 –source [get_clocks clk_name1] -------> source latency
• Set_clock_latency 0.851 –source –min [get_clocks clk_name2] -----> min source latency
• Set_clock_latency 1.322 –source –max [get_clocks clk_name2] ------> max source latency
• One important distinction to observe between source and network latency is that once a
clock tree is built for the design, the network latency can be ignored. However the source
latency remains even after the clock tree is built.
• The network latency is an estimate of the delay of the clock tree before clock tree synthesis.
After clock tree synthesis, the total clock latency from the clock source to a clock in of a flip
flop is the source latency plus actual delay of the clock tree from the clock definition point to
the flip flop.
Clock Uncertainty:
• clock uncertainty is the difference between the arrivals of clocks
at registers in one clock domain or between domains. it can be
classified as static and dynamic clock uncertainties.
• Timing Uncertainty of clock period is set by the command
set_clock_uncertainty at the synthesis stage to reserve some
part of the clock period for uncertain factors (like skew, jitter,
OCV, CROSS TALK, MARGIN or any other pessimism) which
will occur in PNR stage. The uncertainty can be used to model
various factors that can reduce the clock period.
• It can define for both setup and hold.
• Set_clock_uncertainty –setup 0.2 [get_clocks clk_name1]
• Set_clock_uncertainty –hold 0.05 [get_clocks clk_name1]
• Clock uncertainty for setup effectively reduces the available clock
period by the specified amount as shown in fig. and the clock
uncertainty for hold is used as an additional margin that needs to
be satisfied.
• the setup check ensures that the data is available at the input of the
#ip-#op before it is clocked in the #ip-#op.
SETUP TIMING CHECK
• The data should be stable for a certain amount of me, namely the
setup me of the #ip-#op, before the acve edge of the clock arrives
at the #ip-#op.
• This requirement ensures that the data is captured reliably into the
#ip-#op.
SETUP TIMING CHECK
ESSENCE OF SETUP CHECK
• The setup check is from the rst acve edge of the clock in the launch
#ip-#op to the closest following acve edge of the capture #ip-#op.
• The setup check ensures that the data launched from the previous
clock cycle is ready to be captured a*er one cycle.
TRAVERSAL PATHS OF DATA AND
CLOCK SIGNALS
• The data launched by this clock edge appears at me Tlaunch + Tck2q +
Tdp at the D pin of the #ip-#op UFF1.
• The second rising edge of the clock (setup is normally checked a*er one
cycle) appears at me Tcycle + Tcapture at the clock pin of the capture
#ip-#op UFF1.
• The di.erence between these two mes must be larger than the setup
me of the #ip-#op, so that the data can be reliably captured in the
#ip-#op.
TRAVERSAL PATHS OF DATA AND
CLOCK SIGNALS
• From the above three statements we conclude that
• Since the setup check poses a max constraint means upper bound on
data path delay , the setup check always uses the longest or the max
ming path. For the same reason, this check is normally veried at
the slow corner where the delays are the largest.
HOLD TIMING CHECK
• A hold ming check ensures that a #ip-#op output value that is
changing does not pass through to a capture #ip-#op and overwrite
its output before the #ip-#op has had a chance to capture its original
value.
• Thus, a hold check is independent of the clock period. The hold check
is carried out on each acve edge of the clock of the capture #ip-#op.
TRAVERSAL PATHS OF DATA AND
CLOCK SIGNALS
• Consider the second rising edge of clock CLKM. The data launched by
the rising edge of the clock takes Tlaunch + Tcktoq + Tdp me to get to
the D pin of the capture #ip-#op UFF1.
• The same edge of the clock takes Tcapture me to get to the clock pin
of the capture #ip-#op.
• The intenon is for the data from the launch #ip-#op to be captured
by the capture #ip-#op in the next clock cycle.
TRAVERSAL PATHS OF DATA AND
CLOCK SIGNALS
• If the data is captured in the same clock cycle, the intended data in
the capture #ip-#op from the previous clock cycle is overwri2en.
• The hold me check is to ensure that the intended data in the capture
#ip#op is not overwri2en.
TRAVERSAL PATHS OF DATA AND
CLOCK SIGNALS
• The hold me check veries that the di.erence between these two mes
i.e data arrival me and clock arrival me at capture #ip-#op must be
larger than the hold me of the capture #ip-#op, so that the previous data
on the #ip-#op is not overwri2en and the data is reliably captured in the
#ip-#op.
Tlaunch + Tck2q + Tdp > Tcapture + Thold
Means
Tlaunch + Tck2q + Tdp-(Tcapture + Thold) >0
Where should hold timing check be
evaluated?
• The hold checks impose a lower bound or min constraint for paths to
the data pin on the capture #ip-#op; the fastest path to the D pin of
the capture #ip-#op needs to be determined.
• This implies that the hold checks are always veried using the
shortest paths. Thus, the hold checks are typically performed at the
fast ming corner.
NOW LET US DEEP DIVE INTO
CLOCK SKEW
• Even when there is only one clock in the design, the clock tree can
result in the arrival mes of the clocks at the launch and capture #ip-
#ops to be substanally di.erent. To ensure reliable data capture, the
clock edge at the capture #ip-#op must arrive before the data can
change. A hold ming check ensures that
1. Data from the subsequent launch edge must not be captured by the
setup receiving edge.
2.Data from the setup launch edge must not be captured by the
preceding receiving edge.
Soluon 1.The subsequent launch edge must not propagate data so
fast that the setup receiving edge does not have me to capture its
data reliably.
Soluon2. the setup launch edge must not propagate data so fast
that the preceding receiving edge does not get a chance to capture
its data.
SKEW
• This phenomenon occurs in synchronous circuits. The Di.erence in
arrival of clock at two consecuve pins of a sequenal element.
Positive skew
• This phenomenon occurs when capture clock comes late than launch
clock
NOW LET US DERIVE SETUP AND
HOLD SLACKS FOR POSITIVE SKEW
• Setup slack=Required me-Arrival me
• Where required me is the me within which data should arrive at capture
#op=Tclk-tsetup+tskew
• Arrival me is the me which is taken by the data to actually arrive at the
capture #op=Tmin=Tclq+tcomb
• so setup slack=Tclk+tskew-(tclq+tcomb+tsetup)
• CONCLUSION: setup slack is going to improve when there is a posive skew
• Now the required me becomes T-Tsu+Tskew.
• If there is a posive skew it means we are giving more me to data to
arrive at D pin of capture FF.
Effect of positive skew on hold slack
• The arrival me of this (n+1)th data should at least be greater than the
Thold me of capture #op FF2. Basically this current data (n) should
be held for enough me for it to be captured reliably, that enough
me is called hold me.
• nth data has to be stable at the capture clock for Tskew+ Thold me
otherwise data n will be corrupted. So we can say +ve skew is bad for
hold.
• Hold slack=Arrival me-Required me.
• Arrival me is the me which is taken by the data to actually arrive at
the capture #op=Tmin=Tclq+tcomb
• Where required me is the me within which data should arrive at
capture #op=Thold+tskew
• So, hold slack =Tclq+tcomb-Thold-tskew
• Where required me is the me within which data should arrive at capture
#op=Tclk-tsetup-tskew
• Arrival me is the me which is taken by the data to actually arrive at the
capture #op=Tmin=Tclq+tcomb
• so setup slack=Tclk-tskew-(tclq+tcomb+tsetup)
• CONCLUSION :setup slack is going to worsen.
EFFECT OF NEGATIVE SKEW ON HOLD
SLACK
• Hold slack=Arrival me-Required me.
• Arrival me is the me which is taken by the data to actually arrive at
the capture #op=Tmin=Tclq+tcomb
• Where required me is the me within which data should arrive at
capture #op=Thold-tskew
• So, hold slack =Tclq+tcomb-Thold+tskew