UNIT I COMPUTER FUNDAMENTALS

Computer Types - Functional Units – Basic Operational Concepts - Number Representation and Arithmetic
Operations - Performance Measurements- Instruction Set Architecture: Memory Locations and Addresses -
Instructions and Instruction Sequencing - Addressing Modes

1.1 COMPUTER TYPES

Modern computers can be divided roughly into four general categories:
Embedded computers are integrated into a larger device or system in order to automatically
monitor and control a physical process or environment. They are used for a specific purpose rather
than for general processing tasks. Typical applications include industrial and home automation,
appliances, telecommunication products, and vehicles. Users may not even be aware of the role that
computers play in such systems.
Personal computers have achieved widespread use in homes, educational institutions, and
business and engineering office settings, primarily for dedicated individual use. They support a
variety of applications such as general computation, document preparation, computer-aided design,
audiovisual entertainment, interpersonal communication, and Internet browsing. A number of
classifications are used for personal computers.
Desktop computers serve general needs and fit within a typical personal workspace.
Workstation computers offer higher computational capacity and more powerful graphical display
capabilities for engineering and scientific work.
Finally, Portable and Notebook computers provide the basic features of a personal computer in
a smaller lightweight package. They can operate on batteries to provide mobility.
Servers and Enterprise systems are large computers that are meant to be shared by a potentially
large number of users who access them from some form of personal computer over a public or
private network. Such computers may host large databases and provide information processing for
a government agency or a commercial organization.
Supercomputers normally offer the highest performance. They are the most expensive and
physically the largest category of computers. Supercomputers are used for the highly demanding
computations needed in weather forecasting, engineering design and simulation, and scientific
work. They have a high cost.
Grid computers provide a more cost-effective alternative. They combine a large number of
personal computers a disk storage unit in a physically distributed high-speed network, called a grid,
which is managed as a coordinated computing resource. By evenly distributing the computational
workload across the grid, it is possible to achieve high performance on large applications ranging
from numerical computation to information searching.
1.2 FUNCTIONAL UNITS
• A computer consists of five functionally independent main parts Input, Memory,
Arithmetic and Logic unit (ALU), Output and Control unit.
INPUT UNIT
• The source program/high level language program/coded information/simply data is fed to
a computer through input devices keyboard is a most common type. Whenever a key is
pressed, one corresponding word or number is translated into its equivalent binary code
over a cable & fed either to memory or processor.
 • Example:- Joysticks, trackballs, mouse, scanners etc are other input devices.
Mouse
• The original mouse was electromechanical and used a large ball that when rolled across a
surface would cause an x and y counter to be incremented.
• Nowadays, the electromechanical mouse is replaced by optical mouse. The
replacement of optical mouse, reduce cost and increase reliability.
• It includes Light emitting diode (LED) to provide lighting, a tiny black and white camera.
The LED is underneath the mouse, the camera takes 1500 sample pictures/second.
• The sample pictures are sent to optical processor that compare the images and
determine how far the mouse has moved.

CENTRAL PROCESSOR UNIT (CPU)

CPU is also called processor. The active part of the computer, which contains the
datapath and control units and which adds numbers, tests numbers, signals I/O devices
to activate, and so on.
ALU or DATAPATH UNIT
• It performs the arithmetic operations.
• It is also called as brawn of the processor.
• The entire operation can be done with the help of registers.
• Registers are faster than memory.
• Registers can hold variables and intermediate results.
• Memory traffic is reduced, so program runs faster.

CONTROL UNIT
• It is also called as a brain of the processor.
• It fetches and analyses the instructions one-by-one and issue control signals to all other
units to perform various operations.
• For a given instruction, the exact set of operations required is indicated by the control
signals. The results of instructions are stored in memory.
• The component of the processor that commands the datapath, memory, and I/O devices
according to the instructions of the program.

MEMORY UNIT
• Memory is nothing but a storage device. It stores the program and data.
• It is divided into ‘n’ number of cells. Each cell is capable of storing one bit information at
a time.
• There are 2 classes of memory.1.Primary 2.Secondary.
Primary Memory
• It is made up of semiconductor material. So it is called Semiconductor memory
• Data storage capacity is less than secondary memory.
• Cost is too expensive than secondary memory.
• CPU can access data directly. Because it is an internal memory.
• Data accessing speed is very fast than secondary memory.
• Ex.RAM & ROM
RAM ROM
Random Access Memory Read Only Memory
Volatile memory Non volatile memory
Data lost when the power turns off and that is It retains data even in the absence of a power
used to hold data and program while they are source and that is store programs between runs.
running.
Temporary storage medium Permanent storage medium
User perform both read and write operation User can perform only read operation
RAM: There are two types of memory available namely, 1. SRAM 2. DRAM
SRAM DRAM
Static RAM Dynamic RAM
Information is stored in 1 bit cell called Flip Information is represented as charge across a
Flop. capacitor
Information will be available as long as power It retains data for few ms based on the charge of
is available capacitor even in the absence of a power
No refreshing is needed Refreshing is needed
Less packaging density High packaging density
More complex Hardware Less complex hardware
More expensive Less expensive
No random access Random access is possible
Access time 10 ns Access time 50 ns
Cache Memory: A small, fast memory that acts as a buffer for a slower, larger memory.
Secondary memory
• Secondary memory (Nonvolatile storage) is a form of storage that retains data
• even in the absence of a power source and that is used to store the programs between
runs.
• It is made up of magnetic material. So it is called magnetic memory.
• Data storage capacity is high than primary memory.
• Cost is too low than primary memory.
• CPU cannot access data directly. Because it is an external memory.
• Data accessing speed is very slow than primary memory.
• Ex. Magnetic disk, Hard Disk, CD, DVD, Floppy Disk
Magnetic Disk
• It consists of a collection of platters, which rotate on a spindle at 5400 revolution/min.
• The metal platters are covered with magnetic recording material on both sides.
• Also called hard disk. A form of nonvolatile secondary memory composed of rotating
platters coated with a magnetic recording material.
 • Because they are rotating mechanical devices, access times are about 5 to 20
milliseconds and cost per gigabyte in 2012 was $0.05 to $0.10.
Optical Disk: Include both Compact Disk (CD) and Digital Video Disk(DVD).
Read-Only CD/DVD
• Data is recorded in a spiral fashion, with individual bits being recorded by burning
small pit.
• The disk is read by shining a laser at the CD surface and determining by examining the
reflected light whether there is a pit or flat surface.
Rewritable CD/DVD
• Use different recording surface that as a crystal line, reflective materials, pits are
formed that are not reflective.
Erase CD/DVD
• The surface is heated and cooled slowly, allowing an annealing process to restore the
surface recording layer to its crystalline structure.
Flash Memory
• A nonvolatile semiconductor memory. It is cheaper and slower than DRAM but more
expensive per bit and faster than magnetic disks. Access times are about 5 to 50
microseconds and cost per gigabyte in 2012 was $0.75 to $1.00.
OUTPUT UNIT
• A mechanism that conveys the result of a computation to a user, such as a display, or to
another computer.
Liquid Crystal Display
• A display technology using a thin layer of liquid polymers that can be used to transmit
or block light according to whether a charge is applied.
• All laptops and desktop computers use Liquid Crystal Display (LCD) to get a thin,
low-power display. A tiny transistor switch at each pixel to control current and make
sharper images.
• The image is composed of a matrix of picture elements or pixels, which can be
represented as a matrix of bits called bitmap.
• Depending on the size of the screen and the resolution, the display matrix ranges in size
from 640*480 to 2560*1600.
• A red, green, blue (RGB) associated with each dot on the display determines the
intensity of the three color components in the final image.
• Pixel: The smallest individual picture element. Screens are composed of hundreds of
thousands to millions of pixels, organized in a matrix.

1.3 BASIC OPERATIONAL CONCEPTS

To perform a given task an appropriate program consisting of a list of instructions is stored in the
memory. Individual instructions are brought from the memory into the processor, which executes
the specified operations. Data to be stored are also stored in the memory.
Examples: Add LOCA, R0
This instruction adds the operand at memory location LOCA, to operand in register R0 & places
the sum into register. This instruction requires the performance of several steps,
1. First the instruction is fetched from the memory into the processor
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

Fig: Connections between the processor and the memory

The fig shows how memory & the processor can be connected. In addition to the ALU & the control
circuitry, the processor contains a number of registers used for several different purposes.
Instruction Register (IR)
• Holds the instruction that is currently being executed.
• Its output is available for the control circuits which generates the timing signals that
control the various processing elements in one execution of instruction.
Program Counter PC
• This is another specialized register that keeps track of execution of a program.
• It contains the memory address of the next instruction to be fetched and executed.
Besides IR and PC, there are n-general purpose registers R0 through Rn-1. MAR PC IR
MEMORY MDR R0 R1 …
The other two registers which facilitate communication with memory are:
1. MAR – (Memory Address Register):- It holds the address of the location to be accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read out of the
address location.
Operating steps are
1. Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction of the
program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
4. After the time required to access the memory elapses, the address word is read out of the
memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be
decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the required
operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating a read
cycle.
8. When the operand has been read from the memory to the MDR, it is transferred from MDR
 to the ALU.
9. After one or two such repeated cycles, the ALU can perform the desired operation.
10. If the result of this operation is to be stored in the memory, the result is sent to MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is initiated.
12. The contents of PC are incremented so that PC points to the next instruction that is to be
executed.
1.5 PERFORMANCE
The machine (or CPU) is said to be faster or has better performance running this program if the
total execution time is shorter. When trying to choose among different computers, performance is
an important attribute.
1. Throughput and Response Time
Response time
• Response time also called execution time. The total time required for the computer to
complete a task, including disk accesses, memory accesses, I/O activities, operating
system overhead, CPU execution time, and so on.
Throughput or bandwidth
• The total amount of work done in a given time. Decreasing response time almost always
improves throughput.
• To maximize performance, we want to minimize response time or execution time for
some task. Thus, we can relate performance and execution time for a computer X:
In the above example, we could also say that computer B is 1.5 times slower than computer A

2. Measuring Performance
CPU execution time: Also called CPU time. The actual time the CPU spends computing for
a specific task.
User CPU time: The CPU time spent in a program itself.
System CPU time: The CPU time spent in the operating system performing tasks on behalf of
the program.
Clock cycle: Also called tick, clock tick, clock period, clock, or cycle. The time for one
clock period, usually of the processor clock, which runs at a constant rate.
Clock period: This is the length of each clock cycle.
Clock rate: This is the inverse of the clock period.
3. CPU Performance and Its Factors
• A simple formula relates the most basic metrics (clock cycles and clock cycle time) to
CPU time.
 • This formula makes it clear that the hardware designer can improve performance by
reducing the number of clock cycles required for a program or the length of the clock
cycle.

Example

4. Instruction Performance
• Execution time is that it equals the number of instructions executed multiplied by the
average time per instruction.
• Therefore, the number of clock cycles required for a program can be written as

Clock cycles per Instruction

• The term clock cycles per instruction, which is the average number of clock cycles
each instruction takes to execute, is often abbreviated as CPI.
 • Since different instructions may take different amounts of time depending on what
they do, CPI is an average of all the instructions executed in the program.
Example
Suppose we have two implementations of the same instruction set architecture.Computer A
has a clock cycle time of 250 ps and a CPI of 2.0 for some program,and computer B has a
clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster
for this program and by how much?

5. The Classic CPU Performance Equation

We can now write this basic performance equation in terms of instruction count (the number of
instructions executed by the program), CPI, and clock cycle time:

Amdahl’s Law
A rule stating that the performance enhancement possible with a given improvement is
limited by the amount that the improved feature is used.
1.6 INSTRUCTION SET ARCHITECTURE:
MEMORY LOCATIONS AND ADDRESSES
▪ The memory consists of many millions of storage cells, each of which can store a bit of
information having the value 0 or 1.
▪ Because a single bit represents a very small amount of information, bits are handled
individually.
▪ The usual approach is to deal with them in groups of fixed size. For this purpose, the
memory is organized so that a group of n bits can be stored or retrieved in a single, basic
operation.
▪ Each group of n bits is referred to as a word of information, and n is called the word length.
▪ Modern computers have word lengths that typically range from 16 to 64 bits. If the word
length of a computer is 32 bits, a single word can store a 32-bit 2’s-complement number or
four ASCII characters, each occupying 8 bits
▪ A unit of 8 bits is called a byte.
▪ Machine instructions may require one or more words for their representation.
▪ Accessing the memory to store or retrieve a single item of information, either a word or a
byte, requires distinct names or addresses for each item location.
▪ It is customary to use numbers from 0 through 2k −1, for some suitable value of k, as the
addresses of successive locations in the memory.
▪ The 2 k addresses constitute the address space of the computer, and the memory can have
up to 2 k addressable locations.
▪ For example, a 24-bit address generates an address space of 224 (16,777,216) locations. This
number is usually written as 16M (16 mega), where 1M is the number 220 (1,048,576). A
32-bit address creates an address space of 232 or 4G (4 giga) locations, where 1G is 230.
Other notational conventions that are commonly used are K (kilo) for the number 210
(1,024), and T (tera) for the number 240.
BYTE ADDRESSABILITY
• There are three basic information quantities to deal with: the bit, byte, and word.
• A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits.
• It is impractical to assign distinct addresses to individual bit locations in the memory.
• The most practical assignment is to have successive addresses refer to successive byte
locations in the memory.
• The term byte-addressable memory is used for this assignment. Byte locations have
addresses 0, 1, 2, . . .. Thus, if the word length of the machine is 32 bits, successive words
are located at addresses 0, 4, 8, . . ., with each word consisting of four bytes.
BIG-ENDIAN AND LITTLE-ENDIAN ASSIGNMENTS
• The name big-endian is used when lower byte addresses are used for the more significant
bytes (the leftmost bytes) of the word.
• The name little-endian is used for the opposite ordering, where the lower byte addresses are
used for the less significant bytes (the rightmost bytes) of the word.

WORD ALIGNMENT
• In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4,8, . . .,
as shown in the above Figure. The word locations have aligned addresses. In general, words
are said to be aligned in memory if they begin at a byte address that is a multiple of the
number of bytes in a word.
• The number of bytes in a word is a power of 2. Hence, if the word length is 16 (2 bytes),
aligned words begin at byte addresses 0, 2, 4, . . ., and for a word length of 64 (23 bytes),
aligned words begin at byte addresses 0, 8, 16, . . ..
Memory Operations
1. Load
2. Store
1. Load:
• The data transfer instruction that copies data from memory to a register is traditionally
called load.
• The format of the load instruction is the name of the operation followed by the register to
be loaded, then a constant and register used to access memory.
• The sum of the constant portion of the instruction and the contents of the second register
forms the memory address.
• The actual MIPS name for this instruction is lw, standing for load word.
Example: Let’s assume that A is an array of 100 words and that the compiler has associated the
variables g and h with the registers $s1 and $s2 as before. Let’s also assume that the starting
address, or base address, of the array is in$s3. Compile this C assignment statement:
g = h + A[8];
Solution:
lw $t0,32($s3) # Temporary reg $t0 gets A[8]
add $s1,$s2,$t0 # g = h + A[8]
The constant in a data transfer instruction (8) is called the off set, and the register added to
form the address ($s3) is called the base register.
2. Store:
• The instruction complementary to load is traditionally called store; it copies data from
a register to memory. The format of a store is similar to that of a load.
Example:
Assume variable h is associated with register $s2 and the base address of the array A is in $s3.
What is the assembly code for the C assignment statement below?
A[12] = h + A[8];
Solution:
lw $t0,32($s3) # Temporary reg $t0 gets A[8]
add $t0,$s2,$t0 # Temporary reg $t0 gets h + A[8]
The final instruction stores the sum into A[12], using 48 (4×12) as the offset and register $s3 as
the base register.
sw $t0,48($s3) # Stores h + A[8] back into A[12]

Stored program concept

The idea that instructions and data of many types can be stored in memory as numbers, leading to
the stored program computer.
1.7 INSTRUCTIONS AND INSTRUCTION SEQUENCING
1.7.1 INSTRUCTION
The words of a computer‘s language are called instructions, and its vocabulary is called an
instruction set. Instruction performs one of the following operations
• Data transfer between register and memory.
• ALU operation.
• Program control and sequencing.
• I/O transfer.
OPERATIONS OF THE COMPUTER HARDWARE
1. Arithmetic Operations
Add and Subtract instruction use three Operands - Two Sources and one Destination.
Example add $t0, $s1, $s2
2. Constant or Immediate Operands
• The constants would have been placed in memory when the program was loaded. For
example, to add the constant 4 to register $s3.
• we could use the code
lw $t0, AddrConstant4($s1) # $t0 = constant 4
add $s3,$s3,$t0 # $s3 = $s3 + $t0 ($t0 == 4)
• This quick add instruction with one constant operand is called add immediate or addi.
To add 4 to register $s3,We just write
addi $s3,$s3,4 # $s3 = $s3 + 4
3. Data Transfer Operations
These operations help in moving the data between memory and registers.
4. Logical Operations
Logical Instructions are used for bitwise manipulation. It is useful for extracting and inserting
groups of bits in a word.
REGISTER TRANSFER NOTATION
• Transfer of information from one location in the computer to another a data transfer instructions
is used. Possible locations that are involved in such transfers are memory locations, processor
registers, or registers in the I/O subsystem.
• To identify a location a symbolic name instead of its hardware binary address is used.
• For example, names for the addresses of memory locations may be LOC,PLACE, A,VAR2;
processor register names may be R0, R5; and I/O register names may be DATAIN, OUTSTATUS,
and so on.
• The contents of a location are denoted by placing square brackets around the name of the
location. Thus, the expression means that the contents of memory location LOC are transferred into
processor register R1.
R1 ← [LOC]
• As another example, consider the operation that adds the contents of registers R1 and R2, and
then places their sum into register R3. This action is indicated as
R3 ← [R1] + [R2]
• This type of notation is known as Register Transfer Notation (RTN). Note that the right-hand
side of an RTN expression always denotes a value, and the left-hand side is the name of a location
where the value is to be placed, overwriting the old contents of that location.
ASSEMBLY LANGUAGE NOTATION
• To represent machine instructions and programs Assembly Language Notation or an assembly
language format is used. For example, an instruction that causes the transfer, from memory location
LOC to processor register R1, is specified by the statement
Move LOC,R1
• The contents of LOC are unchanged by the execution of this instruction, but the old contents
of register R1 are overwritten.
• The second example of adding two numbers contained in processor registers R1 and R2 and
placing their sum in R3 can be specified by the assembly language statement
Add R1,R2,R3

BASIC INSTRUCTION FORMATS

• There are four types of Instruction Formats. They are:
• Three address Instructions
• Two address Instructions
• One address Instructions
• Zero address Instructions
Three address Instructions
• Assume that this instruction contains the memory addresses of the three operands—A, B,
and C. This three-address instruction can be represented symbolically as
Add A,B,C
• Operands A and B are called the source operands, C is called the destination operand, and
Add is the operation to be performed on the operands. A general instruction of this type
has the format
Operation Source1,Source2,Destination
Two address Instructions
• An alternative approach is to use a sequence of simpler instructions to perform the same
task, with each instruction having only one or two operands. Suppose that two-address
instructions of the form are available.
Operation Source, Destination
• An Add instruction of this type is
Add A, B
• which performs the operation B←[A] + [B]. When the sum is calculated, the result is sent
to the memory and stored in location B, replacing the original contents of this location.
This means that operand B is both a source and a destination.
• another two address instruction that copies the contents of one memory location into
another. Such an instruction is
Move B, C
• which performs the operation C←[B], leaving the contents of location B unchanged.
One address Instructions
• Another possibility is to have machine instructions that specify only one memory operand.
When a second operand is needed, as in the case of an Add instruction, it is understood
implicitly to be in a unique location, accumulator. A processor register, usually called the
accumulator, is used for this purpose. Thus, the one-address instruction
Add A
• means the following: Add the contents of memory location A to the contents of the
accumulator register and place the sum back into the accumulator. The following are the
examples of one-address instructions
Load A
and
Store A
 • The Load instruction copies the contents of memory location A into the accumulator, and
the Store instruction copies the contents of the accumulator into memory location A.
Using only one-address instructions, the operation C←[A]+[B] can be performed by
executing the sequence of instructions
Load A
Add B
Store C
Zero address Instruction
• It is also possible to use instructions in which the locations of all operands are defined
implicitly. Such instructions are found in machines that store operands in a structure called
a pushdown stack. In this case, the instructions are called zero-address instructions.
Push A
Push B
Add
Pop C
• Operand A is transferred from memory to pushdown stack and the second operand B from
memory is transferred to stack. Then the zero address instruction ‘Add’ , pops the top two
contents of the stack and adds them and stores the result by pushing it into the stack. The
result is then popped and stored into the memory location C.
Format Types:
1. R-Format
2. I-Format
3. J-Format
1. R-Type Format:
Opcode: The field that denotes the operation and format of an instruction.

Instruction Fields:
op: operation code (opcode)
rs: first source register number
rt: second source register number
rd: destination register number
shamt: shift amount (00000 for now)
funct: function code (extends opcode)

Example:

2. I-Type Format:
A second type of instruction format is called I-type (for immediate)or I-format and is used by the
immediate and data transfer instructions. The fields of I-format are
the hardware knows whether to treat the last half of the instruction as three fields(R-type) or as a
single field (I-type).
3. J-Format:
j target- J-type is short for "jump type". The format of an J-type instruction looks like:
Opcode Address
The semantics of the j instruction (j means jump) are:
PC <- PC31-28 IR25-0 00
where PC is the program counter, which stores the current address of the instruction being executed.
You update the PC by using the upper 4 bits of the program counter, followed by the 26 bits of the
target (which is the lower 26 bits of the instruction register), followed by two 0's, which creates a
32 bit address.
LOGICAL OPERATIONS
The packing and unpacking of bits into words. These instructions are called logical
operations.

1. SHIFT:

shamt: how many positions to shift

Shift left logical
Shift left and fill with 0 bits
sll by i bits multiplies by 2i
Shift right logical
Shift right and fill with 0 bits
srl by i bits divides by 2i (unsigned only)
• For example, if register $s0contained
0000 0000 0000 0000 0000 0000 0000 1001two = 9ten
• and the instruction to shift left by 4 was executed, the new value would be:
0000 0000 0000 0000 0000 0000 1001 0000two = 144ten
• The dual of a shift left is a shift right. The actual name of the two MIPS shift
instructions are called shift left logical (sll) and shift right logical (srl).
• The following instruction performs the operation above, assuming that the original
value was in register $s0 and the result should go in register $t2:
sll $t2,$s0,4 # reg $t2 = reg $s0 << 4 bits
 • The encoding of sll is 0 in both the op and funct fields, rd contains 10 (register
$t2), rt contains 16 (register $s0), and shamt contains 4. The rs field is unused
and thus is set to 0.Shifting left by i bits gives the same result as multiplying by 2i.
2. AND
• A logical bit by-bit operation with two operands that calculates a 1 only if there is a 1
in both operands.
Ex: and $t0, $t1, $t2

3. OR
• A logical bit-by bit operation with two operands that calculates a 1 if there is a 1 in
either operand.
Ex: or $t0,$t1,$t2

4. NOT
• A logical bit-by bit operation with one operand that inverts the bits; that is, it replaces
every 1 with a 0, and every 0 with a 1.

5. NOR
• A logical bit-by bit operation with two operands that calculates the NOT of the OR of
the two operands. That is, it calculates a 1 only if there is a 0 in both operands. If one
operand is zero, then it is equivalent to NOT:
A NOR 0= NOT (A OR 0) = NOT (A).
• If the register $t1 is unchanged from the preceding example and register $t3has the
value 0, the result of the MIPS instruction \
nor $t0,$t1,$t3 # reg $t0 = ~ (reg $t1 | reg $t3)
• register $t0
1111 1111 1111 1111 1100 0011 1111 1111two
1.7.2 INSTRUCTION SEQUENCING
Conditional Operations
1. Branch to a labeled instruction if a condition is true. Otherwise, continue sequentially.
beq rs, rt, L1
if (rs == rt) branch to instruction labeled L1;
bne rs, rt, L1
if (rs != rt) branch to instruction labeled L1;
2. Set result to 1 if a condition is true. Otherwise, set to 0.
slt rd, rs, rt
if (rs < rt) rd = 1; else rd = 0;
slti rt, rs, constant
if (rs < constant) rt = 1; else rt = 0;
3. Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L
4. Jump Instructions
Unconditional jump to instruction labeled L1
j L1
Jump Address Table: Also called jump table. A table of addresses of alternative instruction
sequences.
5. Procedure call: jump and link.
Jump-and-Link Instruction: An instruction that jumps to an address and simultaneously saves
the address of the following instruction in a register($rain MIPS).
jal ProcedureLabel
Address of following instruction put in $ra.
Jumps to target address.
6. Procedure return: jump register
Return address: A link to the calling site that allows a procedure to return to the proper address in
MIPS it is stored in register $ra.
jr $ra
Copies $ra to program counter. Can also be used for computed jumps. e.g., for case/switch
statements.
Procedure: A stored subroutine that performs a specific task based on the parameters with
which it is provided.
Caller: The program that instigates a procedure and provides the necessary parameter values.
Callee: A procedure that executes a series of stored instructions based on parameters provided by
the caller and then returns control to the caller.
Program counter (PC): The register containing the address of the instruction in the program being
executed.
Stack: A data structure for spilling registers organized as a last-in first-out queue.
Stack pointer: A valued noting the most recently allocated address in a stack that shows where
registers should be spilled or where old register values can be found. In MIPS, it is register $sp.
Push: Add element to stack.
Pop: Remove element from stack.
Global pointer: The register that is reserved to point to the static area.
INSTRUCTIONS FOR MAKING DECISIONS –CONTROL OPERATIONS
• It is ability to make decisions. Based on the input data and the values created during
computation.
• The first instruction is beq register1, register2, L1
• This instruction means go to the statement labeled L1 if the value in register1 equals the
value in register2. The mnemonic beq stands for branch if equal.
• The second instruction is bne register1, register2, L1
• It means go to the statement labeled L1 if the value in register1 does not equal the
value in register2. The mnemonic bne stands for branch if not equal. These two
instructions are traditionally called conditional branches.
Compiling if-then-else into Conditional Branches
• In the following code segment, f, g, h, i, and j are variables. If the five variables f through
j correspond to the five registers $s0 through $s4, what is the compiled MIPS code for
this C if statement?
if (i == j) f = g + h; else f = g – h;
Code
bne $s3,$s4,else # go to Else if i ≠ j
add $s0,$s1,$s2 # f = g + h (skipped if i ≠ j)
j Exit # go to Exit
else: sub $s0,$s1,$s2 # f = g – h (skipped if i = j)
Exit:
Conditional Branch
• An instruction that requires the comparison of two values and that allows for a
subsequent transfer of control to a new address in the program based on the outcome
of the comparison.

Loops
• Decisions are important both for choosing between two alternatives—found in if
statements and for iterating a computation found in loops. The same assembly
instructions are the building blocks for both cases.
Compiling a while Loop in C
• Here is a traditional loop in C:
 while (save[i] == k)
i += 1;
• Assume that i and k correspond to registers $s3 and $s5 and the base of the array save is
in $s6. What is the MIPS assembly code corresponding to this C segment?
Code:
Loop: sll $t1,$s3,2 # Temp reg $t1 = i * 4
add $t1,$t1,$s6 # $t1 = address of save[i]
lw $t0,0($t1) # Temp reg $t0 = save[i]
bne $t0,$s5, Exit # go to Exit if save[i] ≠ k
addi $s3,$s3,1 #i=i+1
j Loop # go to Loop
Exit:
Basic Block
• A sequence of instructions without branches (except possibly at the end) and without
branch targets or branch labels (except possibly at the beginning).
Set on Less Than Instruction
• Compares two registers and sets a third register to 1 if the first is less than the second;
otherwise, it is set to 0.
• The MIPS instruction is called set on less than, or slt. For example,
slt $t0, $s3, $s4 # $t0 = 1 if $s3 < $s4
• It means that register $t0 is set to 1 if the value in register $s3 is less than the value in
register $s4; otherwise, register $t0 is set to 0.
• Constant operands are popular in comparisons, so there is an immediate version of the
set on less than instruction. To test if register $s2 is less than the constant10, we can
just write
slti $t0,$s2,10 # $t0 = 1 if $s2 < 10
Signed versus Unsigned Comparison
• Suppose register $s0 has the binary number
1111 1111 1111 1111 1111 1111 1111 1111two and that register $s1 has the binary
number 0000 0000 0000 0000 0000 0000 0000 0001two
What the values are of registers $t0 and $t1 after these two instructions?
Solution
slt $t0, $s0, $s1 # signed comparison
sltu $t1, $s0, $s1 # unsigned comparison
• The value in register $s0 represents -1ten if it is an integer and 4,294,967,295tenif it is
an unsigned integer.
• The value in register $s1 represents 1ten in either case. Then register $t0 has the value
1, since -1ten<1ten, and register $t1 has the value 0, since 4,294,967,295ten>1ten.
1.8 ADDRESSING MODE
Multiple forms of addressing are generically called addressing modes. The following diagram
shows how operands are identified for each addressing mode.
1. Register mode
The operand is the contents of a processor register; the name (address) of the register is given in the
instruction.
e.g. Move R1, R2
The processor registers are used as temporary storage locations where the data in a register are
accessed using the register mode. In the above data transfer ‘Move’ instruction R1, R2 are register
names and hence are register addressing modes.
2. Absolute mode (Direct Mode)
The operand is in a memory location; the address of this location is given explicitly in the
instruction.
Move LOC, R2
uses these two modes. Processor registers are used as temporary storage locations where the data
in a register are accessed using the Register mode. The Absolute mode can represent global
variables in a program. ‘LOC’ is a name for the memory address, so the data in memory is referred
in Direct mode.
3. Immediate mode — The operand is given explicitly in the instruction. Address and data constants
can be represented in assembly language using the Immediate mode.
Move #200, R0
places the value 200 in register R0. Clearly, the Immediate mode is only used to specify the value
of a source operand. A common convention is to use the sharp sign (#) in front of the value to
indicate that this value is to be used as an immediate operand.
4. Indirect mode
In the following addressing modes, the instruction does not give the operand or its address
explicitly. Instead, it provides information from which the memory address of the operand can be
determined. This address is referred to as the effective address (EA) of the operand. The effective
address of the operand is the contents of a register or memory location whose address appears in
the instruction.
Add (R1), R0
5. Index mode
The effective address of the operand is generated by adding a constant value to the contents of a
register. It is useful in dealing with lists and arrays.
The register used may be either a special register provided for this purpose, or, more commonly;
it may be any one of a set of general-purpose registers in the processor. In either case, it is
referred to as an index register. The Index mode is symbolically represented as
X(Ri )
where X denotes the constant value contained in the instruction and Ri is the name of the register
involved. The effective address of the operand is given by
EA = X + [Ri ]
6. Base with Index
A variation of the basic index addressing mode provides a very efficient access to memory
operands in practical programming situations. For example, a second register may be used to
contain the offset X, in which case we can write the Index mode as
(Ri,R j )
The effective address is the sum of the contents of registers Ri and Rj . The second register is
usually called the base register.
Effective Address (EA) = Base register (Ri) + Index register (Rj)

7. Base with index and offset

This mode is another version of the Index mode which uses two registers plus a constant, which
can be denoted as
 X (Ri, R j )
In this case, the effective address is the sum of the constant X and the contents of registers Ri and
Rj . This added flexibility is useful in accessing multiple components inside each item in a record,
where the beginning of an item is specified by the (Ri, R j ) part of the addressing mode. In other
words, this mode implements a three-dimensional array.

8. Relative Addressing mode

The Index mode uses general-purpose processor registers. In relative addressing mode, the
program counter, PC, is used instead of a general purpose register. Then,
X (PC)
can be used to address a memory location that is X bytes away from the location presently pointed
to by the program counter. The effective address is determined similar to the Index mode but using
the program counter in place of the general-purpose register Ri. This mode can be used to access
data operands. But, its most common use is to specify the target address in branch instructions.
An instruction such as
Branch>0 LOOP
causes program execution to go to the branch target location identified by the name LOOP if the
branch condition is satisfied. This location can be computed by specifying it as an offset from the
current value of the program counter. Since the branch target may be either before or after the
branch instruction, the offset is given as a signed number.

9. Auto Indexed (increment mode)

Effective address of the operand is the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are automatically incremented to point to the
next consecutive memory location.
(R1)+.
Here one register reference, one memory reference and one ALU operation is required to access
the data.
Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
R2 = R2 + d

10. Auto indexed (decrement mode):

Effective address of the operand is the contents of a register specified in the instruction. Before
accessing the operand, the contents of this register are automatically decremented to point to the
previous consecutive memory location.
(R1)
Here one register reference, one memory reference and one ALU operation is required to access
the data.
Example:
Add R1,-(R2) //OR
R2 = R2-d
R1 = R1 + M[R2]
RISC vs CISC
Reduced Instruction Set Architecture (RISC)
Reduce the cycles per instruction at the cost of the number of instructions per program.

Complex Instruction Set Architecture (CISC)

CISC approach attempts to minimize the number of instructions per program but at the cost of an
increase in the number of cycles per instruction.
 RISC CISC

Focus on software Focus on hardware

Uses both hardwired and microprogrammed

Uses only Hardwired control unit
control unit

Transistors are used for storing complex

Transistors are used for more registers
Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Can perform REG to REG or REG to MEM
Arithmetic operations or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction executed in a single clock

Instruction takes more than one clock cycle
cycle

Instructions are larger than the size of one

An instruction fit in one word.
word

Simple and limited addressing modes. Complex and more addressing modes.

RISC is Reduced Instruction Cycle. CISC is Complex Instruction Cycle.

The number of instructions is less as The number of instructions is more as

compared to CISC. compared to RISC.

It consumes the low power. It consumes more/high power.

RISC is highly pipelined. CISC is less pipelined.

RISC required more RAM. CISC required less RAM.

Here, addressing modes are less. Here, addressing modes are more.