INTEGRATED CIRCUITS

83C654
CMOS single-chip 8-bit microcontroller

Product specification 1998 Jan 06

Supersedes data of 1996 Aug 15
IC20 Data Handbook

 
   
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

DESCRIPTION 8XC654 can be expanded using standard FEATURES

The P83C654 Single-Chip 8-Bit TTL compatible memories and logic.
ω80C51 central processing unit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
The device also functions as an arithmetic
processor having facilities for both binary and
ω16k ψ 8 ROM expandable externally to
of the 80C51 microcontroller family. The 64k bytes
BCD arithmetic plus bit-handling capabilities.
83C654 has the same instruction set as the The instruction set consists of over 100 ω256 ψ 8 RAM, expandable externally to
80C51. Two versions of the derivative exist: instructions: 49 one-byte, 45 two-byte and 17 64k bytes
83C654 Ð 16k bytes mask programmable three-byte. With a 16(24)MHz crystal, 58% of ωTwo standard 16-bit timer/counters
ROM the instructions are executed in 0.75(0.5)m s
and 40% in 1.5(1)m s. Multiply and divide ωFour 8-bit I/O ports
87C654 Ð EPROM version (described in a
separate data sheet)
instructions require 3(2)m s. ωI2C-bus serial I/O port with byte oriented
master and slave functions
ωFull-duplex UART facilities
This device provides architectural
enhancements that make it applicable in a
variety of applications for general control ωPower control modes
systems. The 83C654 contains a non-volatile Idle mode
16k ψ 8 read-only program memory, a volatile
Power-down mode
256 ψ 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters ωROM code protection
(identical to the timers of the 80C51), a ωExtended frequency range: 3.5 to 24 MHz
multi-source, two-priority-level, nested
interrupt structure, an I2C interface, UART ωThree operating ambient temperature
and on-chip oscillator and timing circuits. For ranges:
systems that require extra capability, the 0 to +705C
±40 to +855C
±40 to +1255C
BLOCK DIAGRAM
FREQUENCY
REFERENCE COUNTERS

XTAL2 XTAL1 T0 T1

OSCILLATOR PROGRAM DATA TWO 16-BIT

AND MEMORY MEMORY TIMER/EVENT
TIMING (16K x 8 ROM) (256 x 8 RAM) COUNTERS

SDA
SHARED
CPU I2C SERIAL I/O WITH
PORT 1
SCL

INTERNAL
INTERRUPTS

64K BYTE BUS PROG SERIAL PORT

EXPANSION PROGRAMMABLE I/O FULL DUPLEX UART
CONTRTOL SYNCHRONOUS SHIFT

INT0 INT1 SERIAL IN SERIAL OUT

CONTROL PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS SHARED WITH
EXTERNAL PORT 3
INTERRUPTS

1998 Jan 06 2
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

LOGIC SYMBOL

VDD VSS

RST

ADDRESS AND
DATA BUS
XTAL1
XTAL2

PORT 0
EA
PSEN
ALE
ALTERNATE
FUNCTIONS

PORT 1
PORT 3

SCL
SDA
RxD
ADDRESS BUS
TxD
PORT 2

INT0
INT1
T0
T1
WR
RD

PIN CONFIGURATIONS
Plastic dual in-line package Plastic shrink dual in-line package

P1.0 1 42 VDD
P1.0 1 40 VDD
P1.1 2 41 P0.0/AD0
P1.1 2 39 P0.0/AD0
P1.2 3 40 P0.1/AD1
P1.2 3 38 P0.1/AD1
P1.3 4 39 P0.2/AD2
P1.3 4 37 P0.2/AD2
P1.4 5 38 P0.3/AD3
P1.4 5 36 P0.3/AD3
P1.5 6 37 P0.4/AD4
P1.5 6 35 P0.4/AD4
SCL/P1.6 7 36 P0.5/AD5
SCL/P1.6 7 34 P0.5/AD5
SDA/P1.7 8 35 P0.6/AD6
SDA/P1.7 8 33 P0.6/AD6
RST 9 34 P0.7/AD7
RST 9 32 P0.7/AD7
PLASTIC 31 EA RxD/P3.0 10 SHRINK 33 EA
RxD/P3.0 10
DUAL DUAL
IN-LINE NC* 11 IN-LINE 32 NC*
TxD/P3.1 11 30 ALE PACKAGE
PACKAGE
INT0/P3.2 12 29 PSEN TxD/P3.1 12 31 ALE

INT1/P3.3 13 28 P2.7/A15 INT0/P3.2 13 30 PSEN

T0/P3.4 14 27 P2.6/A14 INT1/P3.3 14 29 P2.7/A15

T1/P3.5 15 26 P2.5/A13 T0/P3.4 15 28 P2.6/A14

WR/P3.6 16 25 P2.4/A12 T1/P3.5 16 27 P2.5/A13

RD/P3.7 17 24 P2.3/A11 WR/P3.6 17 26 P2.4/A12

XTAL2 18 23 P2.2/A10 RD/P3.7 18 25 P2.3/A11

XTAL1 19 22 P2.1/A9 XTAL2 19 24 P2.2/A10

VSS 20 21 P2.0/A8 XTAL1 20 23 P2.1/A9

VSS 21 22 P2.0/A8
SU00933

SU00934

* Do not connect.

1998 Jan 06 3
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

Plastic leaded chip carrier

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3
P1.4

P1.3

P1.2

P1.1

P1.0

NC*

V DD
6 5 4 3 2 1 44 43 42 41 40

P1.5 7 39 P0.4/AD4

P1.6/SCL 8 38 P0.5/AD5

P1.7/SDA 9 37 P0.6/AD6

RST 10 36 P0.7/AD7

P3.0/RxD 11 35 EA

NC* 12 PLASTIC LEADED CHIP CARRIER 34 NC*

P3.1/TxD 13 33 ALE

P3.2/INT0 14 32 PSEN

P3.3/INT1 15 31 P2.7/A15

P3.4/T0 16 30 P2.6/A14

P3.5/T1 17 29 P2.5/A13

18 19 20 21 22 23 24 25 26 27 28

P2.3/A11
P3.6/WR

P2.0/A8

P2.1/A9

P2.2/A10

P2.4/A12
XTAL2

XTAL1
P3.7/RD

NC*
V SS

SU00929

* Do not connect.

Plastic quad flat pack

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3
V SS3
P1.4

P1.3

P1.2

P1.1

P1.0

V DD

44 43 42 41 40 39 38 37 36 35 34

P1.5 1 33 P0.4/AD4

P1.6/SCL 2 32 P0.5/AD5

P1.7/SDA 3 31 P0.6/AD6

RST 4 30 P0.7/AD7

P3.0/RxD 5 29 EA/VPP

VSS4 6 QUAD FLAT PACK 28 VSS2

P3.1/TxD 7 27 ALE

P3.2/INT0 8 26 PSEN

P3.3/INT1 9 25 P2.7/A15

P3.4/T0 10 24 P2.6/A14

P3.5/T1 11 23 P2.5/A13

12 13 14 15 16 17 18 19 20 21 22
V SS1

P2.3/A11
P3.6/WR

P2.0/A8

P2.1/A9

P2.2/A10

P2.4/A12
XTAL2

XTAL1
P3.7/RD

NC*

SU00935

* Do not connect.
(QFP only): Due to EMC improvements, all VSS pins (6, 16, 28, 39) must be connected to VSS on the 80C652/83C654.

1998 Jan 06 4
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

ORDERING INFORMATION
PHILIPS PART ORDER NUMBER PHILIPS NORTH AMERICA
PART MARKING PART ORDER NUMBER DRAWING TEMPERATURE RANGE (5C) FREQ
NUMBER AND PACKAGE MHz2,3
23
ROMless1 ROM ROMless1 ROM EPROM3
P80C652EBP P83C654EBP/xxx P80C652EBPN P83C654EBPN S87C654-4N40 SOT129-1 0 to +70, 16
Plastic Dual In-line Package
P80C652EBA P83C654EBA/xxx P80C652EBAA P83C654EBAA S87C654-4A44 SOT187-2 0 to +70, 16
Plastic Leaded Chip Carrier
P80C652EBB P83C654EBB/xxx P80C652EBBB P83C654EBBB S87C654-4B44 SOT307-2 0 to +70, 16
Plastic Quad Flat Pack
P83C654EBR/xxx SOT270-1 0 to +70, 16
Plastic Shrink Dual In-Line Package
P80C652EFP P83C654EFP/xxx P80C652EFPN P83C654EFPN S87C654-5N40 SOT129-1 ±40 to +85, 16
Plastic Dual In-line Package
P80C652EFA P83C654EFA/xxx P80C652EFAA P83C654EFAA S87C654-5A44 SOT187-2 ±40 to +85, 16
Plastic Leaded Chip Carrier
P80C652EFB P83C654EFB/xxx P80C652EFBB P83C654EFBB S87C654-5B44 SOT307-2 ±40 to +85, 16
Plastic Quad Flat Pack
P80C652EHP P83C654EHP/xxx P80C652EHPN P83C654EHPN SOT129-1 ±40 to +125, 16
Plastic Dual In-line Package
P80C652EHA P83C654EHA/xxx P80C652EHAA P83C654EHAA SOT187-2 ±40 to +125, 16
Plastic Leaded Chip Carrier
P80C652EHB P83C654EHB/xxx P80C652EHBB P83C654EHBB SOT307-2 ±40 to +125, 16
Plastic Quad Flat Pack
S87C654-7N40 SOT129-1 0 to +70, 20
Plastic Dual In-line Package
S87C654-7A44 SOT187-2 0 to +70, 20
Plastic Leaded Chip Carrier
S87C654-8N40 SOT129-1 ±40 to +85, 20
Plastic Dual In-line Package
S87C654-8A44 SOT187-2 ±40 to +85, 20
Plastic Leaded Chip Carrier
P80C652IBP P83C654IBP/xxx P80C652IBPN P83C654IBPN SOT129-1 0 to +70, 24
Plastic Dual In-line Package
P80C652IBA P83C654IBA/xxx P80C652IBAA P83C654IBAA SOT187-2 0 to +70, 24
Plastic Leaded Chip Carrier
P80C652IBB P83C654IBB/xxx P80C652IBBB P83C654IBBB SOT307-2 0 to +70, 24
Plastic Quad Flat Pack
P80C652IFP P83C654IFP/xxx P80C652IFPN P83C654IFPN SOT129-1 ±40 to +85, 24
Plastic Dual In-line Package
P80C652IFA P83C654IFA/xxx P80C652IFAA P83C654IFAA SOT187-2 ±40 to +85, 24
Plastic Leaded Chip Carrier
P80C652IFB P83C654IFB/xxx P80C652IFBB P83C654IFBB SOT307-2 ±40 to +85, 24
Plastic Quad Flat Pack
NOTES:
1. For full specification, see the 80C652/83C652 data sheet.
2. 83C654 frequency range is 3.5MHz±16MHz or 3.5MHz±24MHz.
3. For specification of the EPROM version, see the 87C654 data sheet.
4. xxx denotes the ROM code number.

1998 Jan 06 5
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP PLCC QFP TYPE NAME AND FUNCTION
VSS 20 22 6, 16, I Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be
28, 39 connected.
VDD 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0±0.7 39±32 43±36 37±30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P1.0±P1.7 1±8 2±9 40±44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
1±3 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL).
Alternate functions include:
P1.6 7 8 2 I/O SCL: I2C-bus serial port clock line.
P1.7 8 9 3 I/O SDA: I2C-bus serial port data line.
P2.0±P2.7 21±28 24±31 18±25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
P3.0±P3.7 10±17 11, 5, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
13±19 7±13 written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51
family, as listed below:
10 11 5 I RxD (P3.0): Serial input port
11 13 7 O TxD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt
13 15 9 I INT1 (P3.3): External interrupt
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD.
ALE 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency. Note that one ALE pulse is skipped during each access to external data
memory.
PSEN 29 32 26 O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches
from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS
inputs without external pull±ups.
EA 31 35 29 I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 16384. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid ªlatch-upº effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS ± 0.5V, respectively.

1998 Jan 06 6
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

Table 1. 8XC652/654 Special Function Registers

DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET
SYMBOL DESCRIPTION
ADDRESS MSB LSB VALUE
ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR: Data pointer
(2 bytes)
DPH Data pointer high 83H 00H
DPL Data pointer low 82H 00H
AF AE AD AC AB AA A9 A8
IE*# Interrupt enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B
BF BE BD BC BB BA B9 B8
IP*# Interrupt priority B8H ± PS1 PS0 PT1 PX1 PT0 PX0 xx000000B
87 86 85 84 83 82 81 80
P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH
97 96 95 94 93 92 91 90
P1*# Port 1 90H SDA SCL FFH
A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH
B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON# Power control 87H SMOD ± ± ± GF1 GF0 PD IDL 0xxx0000B
9F 9E 9D 9C 9B 9A 99 98
S0CON*# Serial 0 port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 data buffer 99H xxxxxxxxB
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00H
S1DAT# Serial 1 data DAH 00H
SP Stack pointer 81H 07H
S1ADR# Serial 1 address DBH ∋∋∋∋∋∋∋∋ SLAVE ADDRESS ∋∋∋∋∋∋∋∋ GC 00H

S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H
DF DE DD DC DB DA D9 D8
S1CON*# Serial 1 control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00000000B
8F 8E 8D 8C 8B 8A 89 88
TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer high 1 8DH 00H
TH0 Timer high 0 8CH 00H
TL1 Timer low 1 8BH 00H
TL0 Timer low 0 8AH 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

1998 Jan 06 7
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

ROM CODE PROTECTION To drive the device from an external clock enabled interrupt (at which time the process
(83C654) source, XTAL1 should be driven while XTAL2 is picked up at the interrupt service routine
is left unconnected. There are no and continued), or by a hardware reset which
The 83C654 has an additional security
requirements on the duty cycle of the starts the processor in the same manner as a
feature. ROM code protection may be
external clock signal, because the input to power-on reset.
selected by setting a mask±programmable
the internal clock circuitry is through a
security bit (i.e., user dependent). This
divide-by-two flip-flop. However, minimum Power-Down Mode
feature may be requested during ROM code
and maximum high and low times specified in In the power-down mode, the oscillator is
submission. When selected, the ROM code
the data sheet must be observed. stopped and the instruction to invoke
is protected and cannot be read out at any
power-down is the last instruction executed.
time by any test mode or by any instruction in
Reset Only the contents of the on-chip RAM are
the external program memory space.
A reset is accomplished by holding the RST preserved. A hardware reset is the only way
The MOVC instructions are the only pin high for at least two machine cycles (24 to terminate the power-down mode. The
instructions that have access to program oscillator periods), while the oscillator is control bits for the reduced power modes are
code in the internal or external program running. To insure a good power-on reset, the in the special function register PCON. Table 2
memory. The EA input is latched during RST pin must be high long enough to allow shows the state of the I/O ports during low
RESET and is ªdon't careº after RESET the oscillator time to start up (normally a few current operating modes.
(also if the security bit is not set). This milliseconds) plus two machine cycles. At
implementation prevents reading internal power-on, the voltage on VDD and RST must
program code by switching from external come up at the same time for a proper
I2C SERIAL COMMUNICATION –
program memory to internal program memory start-up. SIO1
during a MOVC instruction or any other The I2C serial port is identical to the I2C
instruction that uses immediate data. Idle Mode serial port on the 8XC552. The operation of
In the idle mode, the CPU puts itself to sleep this subsystem is described in detail in the
while all of the on-chip peripherals stay 8XC552 section of this manual.
OSCILLATOR
active. The instruction to invoke the idle
CHARACTERISTICS Note that in both the 8XC652/4 and the
mode is the last instruction executed in the
XTAL1 and XTAL2 are the input and output, 8XC552 the I2C pins are alternate functions
normal operating mode before the idle mode
respectively, of an inverting amplifier. The to port pins P1.6 and P1.7. Because of this,
is activated. The CPU contents, the on-chip
pins can be configured for use as an on-chip P1.6 and P1.7 on these parts do not have a
RAM, and all of the special function registers
oscillator, as shown in the Logic Symbol, pull-up structure as found on the 80C51.
remain intact during this mode. The idle
page 3. Therefore P1.6 and P1.7 have open drain
mode can be terminated either by any
outputs on the 8XC652/4.

Table 2. External Pin Status During Idle and Power-Down Mode

PROGRAM
MODE MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

Serial Control Register (S1CON) See Table 3

S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3. Serial Clock Rates

BIT FREQUENCY (kHz) AT fOSC
CR2 CR1 CR0 6MHz 12MHz 16MHz 24MHz fOSC DIVIDED BY
0 0 0 23 47 62.5 94 256
0 0 1 27 54 71 1071 224
0 1 0 31.25 62.5 83.3 1251 192
0 1 1 37 75 100 1501 160
1 0 0 6.25 12.5 17 25 960
1 0 1 50 100 1331 2001 120
1 1 0 100 2001 2671 4001 60
1 1 1 0.24 < 62.5 0.49 < 62.5 0.65 < 55.6 0.98 < 50.0 96 ψ (256 ± (reload value Timer 1))
0 to 255 0 to 254 0 to 253 0 to 251 reload value range Timer 1 (in mode 2)
NOTES:
1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.

1998 Jan 06 8
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

ABSOLUTE MAXIMUM RATINGS1, 2, 3

PARAMETER RATING UNIT

Storage temperature range ±65 to +150 5C

Voltage on any other pin to VSS ±0.5 to + 6.0 V

Input, output current on any single pin +5 mA

Power dissipation 1 W
(based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.

DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) FREQUENCY (MHz)
TYPE TEMPERATURE RANGE (5C)
MIN. MAX. MIN. MAX.
P83C654EBx 4.5 5.5 3.5 16 0 to +70
P83C654EFx 4.5 5.5 3.5 16 ±40 to +85
P83C654FHx 4.5 5.5 3.5 16 ±40 to +125
P83C654IBx 4.5 5.5 3.5 24 0 to +70
P83C654IFx 4.5 5.5 3.5 24 ±40 to +85

1998 Jan 06 9
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

DC ELECTRICAL CHARACTERISTICS
VSS = 0V, VDD = 5V + 10%
TEST LIMITS
SYMBOL PARAMETER PART TYPE CONDITIONS MIN. MAX. UNIT
VIL Input low voltage, 0 to +705C ±0.5 0.2VDD±0.1 V
exceptt EA
EA, P1.6/SCL,
P1 6/SCL P1.7/SDA
P1 7/SDA ±40 to +855C ±0.5 0.2VDD±0.15 V
±40 to +1255C ±0.5 0.2VDD±0.25 V
VIL1 Input low voltage to EA 0 to +705C ±0.5 0.2VDD±0.3 V
±40 to +855C ±0.5 0.2VDD±0.35 V
±40 to +1255C ±0.5 0.2VDD±0.45 V
VIL2 Input low voltage to P1.6/SCL, P1.7/SDA6 ±0.5 0.3VDD V
VIH Input high voltage, except XTAL1, RST, 0 to +705C 0.2VDD+0.9 VDD+0.5 V
P1 6/SCL P1.7/SDA
P1.6/SCL, P1 7/SDA ±40 to +855C 0.2VDD+1.0 VDD+0.5 V
±40 to +1255C 0.2VDD+1.0 VDD+0.5 V
VIH1 Input high voltage, XTAL1, RST 0 to +705C 0.7VDD VDD+0.5 V
±40 to +855C 0.7VDD+0.1 VDD+0.5 V
±40 to +1255C 0.7VDD+0.1 VDD+0.5 V
VIH2 Input high voltage, P1.6/SCL, P1.7/SDA6 0.7VDD 6.0 V
VOL Output low voltage, ports 1, 2, 3, IOL = 1.6mA8, 9 0.45 V
except P1.6/SCL, P1.7/SDA
VOL1 Output low voltage, port 0, ALE, PSEN IOL = 3.2mA8, 9 0.45 V
VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA 0.4 V
VOH Output high voltage, ports 1, 2, 3, ALE, PSEN10 IOH = ±60m A 2.4 V
IOH = ±25m A 0.75VDD V
IOH = ±10m A 0.9VDD V
VOH1 Output high voltage; port 0 in external bus mode IOH = ±800m A 2.4 V
IOH = ±300m A 0.75VDD V
IOH = ±80m A 0.9VDD V
IIL Logical 0 input current, ports 1, 2, 3, 0 to +705C VIN = 0.45V ±50 m A
exceptt P1 6/SCL P1
P1.6/SCL, 7/SDA
P1.7/SDA ±40 to +855C ±75 m A
±40 to +1255C ±75 m A
ITL Logical 1-to-0 transition current, ports 1, 2, 3, 0 to +705C See note 7 ±650 m A
exceptt P1 6/SCL P1
P1.6/SCL, 7/SDA
P1.7/SDA ±40 to +855C ±750 m A
±40 to +1255C ±750 m A
IL1 Input leakage current, port 0, EA 0.45V < VI < VDD +10 m A
IL2 Input leakage current, P1.6/SCL, P1.7/SDA 0V < VI < 6.0V +10 m A
0V < VDD < 6.0V m A
IDD Power supply current: See note 1
Active mode @ 16MHz2, 11 VDD=5.5V 28.0 mA
Active mode @ 24MHz2, 11 VDD=5.5V 35.0 mA
Idle mode @ 16MHz3, 11 6 mA
Idle mode @ 24MHz3, 11 7 mA
Power down mode4, 5 50 m A
Power down mode4, 5 ±40 to +1255C 100 m A
RRST Internal reset pull-down resistor 50 150 kW
CIO Pin capacitance Freq.=1MHz 10 pF
NOTES:
1. See Figures 9 through 11 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5V; VIH = VDD ±0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V;
VIH = VDD ±0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD;
EA = RST = VSS. See Figure 11.
5. 2V 3 VPD 3 VDDmax.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VDD will be recognized as a
logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1.

1998 Jan 06 10
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum
IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the
test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
10. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
11. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA.

40 50

IDD IDD
(mA) (mA)
40

30

(1) 30

20 (1)

20

10
10
(2)
(2)

0
0 4 8 12 16 0
0 4 8 12 16 24
fXTAL1 (MHz)
fXTAL1 (MHz)
(1) MAXIMUM OPERATING MODE: VDD = VDDmax (1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax (2) MAXIMUM IDLE MODE: VDD = VDDmax
These values are valid within the specified These values are valid within the specified
frequency range. frequency range.

Figure 1. IDD vs. Frequency

1998 Jan 06 11
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

AC ELECTRICAL CHARACTERISTICS1, 2 (16 MHz type)

16MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/tCLCL 2 Oscillator frequency 3.5 16 MHz
tLHLL 2 ALE pulse width 85 2tCLCL±40 ns
tAVLL 2 Address valid to ALE low 8 tCLCL±55 ns
tLLAX 2 Address hold after ALE low 28 tCLCL±35 ns
tLLIV 2 ALE low to valid instruction in 150 4tCLCL±100 ns
tLLPL 2 ALE low to PSEN low 23 tCLCL±40 ns
tPLPH 2 PSEN pulse width 143 3tCLCL±45 ns
tPLIV 2 PSEN low to valid instruction in 83 3tCLCL±105 ns
tPXIX 2 Input instruction hold after PSEN 0 0 ns
tPXIZ 2 Input instruction float after PSEN 38 tCLCL±25 ns
tAVIV 2 Address to valid instruction in 208 5tCLCL±105 ns
tPLAZ 2 PSEN low to address float 10 10 ns
Data Memory
tRLRH 3, 4 RD pulse width 275 6tCLCL±100 ns
tWLWH 3, 4 WR pulse width 275 6tCLCL±100 ns
tRLDV 3, 4 RD low to valid data in 148 5tCLCL±165 ns
tRHDX 3, 4 Data hold after RD 0 0 ns
tRHDZ 3, 4 Data float after RD 55 2tCLCL±70 ns
tLLDV 3, 4 ALE low to valid data in 350 8tCLCL±150 ns
tAVDV 3, 4 Address to valid data in 398 9tCLCL±165 ns
tLLWL 3, 4 ALE low to RD or WR low 138 238 3tCLCL±50 3tCLCL+50 ns
tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL±130 ns
tQVWX 3, 4 Data valid to WR transition 3 tCLCL±60 ns
tDW 3, 4 Data setup time before WR 288 7tCLCL±150 ns
tWHQX 3, 4 Data hold after WR 13 tCLCL±50 ns
tRLAZ 3, 4 RD low to address float 0 0 ns
tWHLH 3, 4 RD or WR high to ALE high 23 103 tCLCL±40 tCLCL+40 ns
Shift Register
tXLXL 5 Serial port clock cycle time3 0.75 12tCLCL m s
tQVXH 5 Output data setup to clock rising edge3 492 10tCLCL±133 ns
tXHQX 5 Output data hold after clock rising edge3 80 2tCLCL±117 ns
tXHDX 5 Input data hold after clock rising edge3 0 0 ns
tXHDV 5 Clock rising edge to input data valid3 492 10tCLCL±133 ns
External Clock
tCHCX 6 High time3 20 20 tCLCL ± tCLCX ns
tCLCX 6 Low time3 20 20 tCLCL ± tCHCX ns
tCLCH 6 Rise time3 20 20 ns
tCHCL 6 Fall time3 20 20 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.

1998 Jan 06 12
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

AC ELECTRICAL CHARACTERISTICS1, 2 (24 MHz type)

24MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/tCLCL 2 Oscillator frequency 3.5 24 MHz
tLHLL 2 ALE pulse width 43 2tCLCL±40 ns
tAVLL 2 Address valid to ALE low 17 tCLCL±25 ns
tLLAX 2 Address hold after ALE low 17 tCLCL±25 ns
tLLIV 2 ALE low to valid instruction in 102 4tCLCL±65 ns
tLLPL 2 ALE low to PSEN low 17 tCLCL±25 ns
tPLPH 2 PSEN pulse width 80 3tCLCL±45 ns
tPLIV 2 PSEN low to valid instruction in 65 3tCLCL±60 ns
tPXIX 2 Input instruction hold after PSEN 0 0 ns
tPXIZ 2 Input instruction float after PSEN 17 tCLCL±25 ns
tAVIV 2 Address to valid instruction in 128 5tCLCL±80 ns
tPLAZ 2 PSEN low to address float 10 10 ns
Data Memory
tRLRH 3, 4 RD pulse width 150 6tCLCL±100 ns
tWLWH 3, 4 WR pulse width 150 6tCLCL±100 ns
tRLDV 3, 4 RD low to valid data in 118 5tCLCL±90 ns
tRHDX 3, 4 Data hold after RD 0 0 ns
tRHDZ 3, 4 Data float after RD 55 2tCLCL±28 ns
tLLDV 3, 4 ALE low to valid data in 180 8tCLCL±150 ns
tAVDV 3, 4 Address to valid data in 210 9tCLCL±165 ns
tLLWL 3, 4 ALE low to RD or WR low 75 175 3tCLCL±50 3tCLCL+50 ns
tAVWL 3, 4 Address valid to WR low or RD low 92 4tCLCL±75 ns
tQVWX 3, 4 Data valid to WR transition 12 tCLCL±30 ns
tDW 3, 4 Data setup time before WR 162 7tCLCL±130 ns
tWHQX 3, 4 Data hold after WR 17 tCLCL±25 ns
tRLAZ 3, 4 RD low to address float 0 0 ns
tWHLH 3, 4 RD or WR high to ALE high 17 67 tCLCL±25 tCLCL+25 ns
Shift Register
tXLXL 5 Serial port clock cycle time3 0.5 12tCLCL m s
tQVXH 5 Output data setup to clock rising edge3 283 10tCLCL±133 ns
tXHQX 5 Output data hold after clock rising edge3 23 2tCLCL±60 ns
tXHDX 5 Input data hold after clock rising edge3 0 0 ns
tXHDV 5 Clock rising edge to input data valid3 283 10tCLCL±133 ns
External Clock
tCHCX 6 High time3 17 17 tCLCL ± tCLCX ns
tCLCX 6 Low time3 17 17 tCLCL ± tCHCX ns
tCLCH 6 Rise time3 5 5 ns
tCHCL 6 Fall time3 5 5 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.

1998 Jan 06 13
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

AC ELECTRICAL CHARACTERISTICS I 2C INTERFACE

SYMBOL PARAMETER INPUT OUTPUT

SCL TIMING CHARACTERISTICS

tHD;STA START condition hold time . 14 tCLCL > 4.0m s1
tLOW SCL LOW time . 16 tCLCL > 4.7m s1
tHIGH SCL HIGH time . 14 tCLCL > 4.0m s1
tRC SCL rise time 3 1m s ±2
tFC SCL fall time 3 0.3m s < 0.3m s3
SDA TIMING CHARACTERISTICS
tSU;DAT1 Data set-up time . 250ns > 20 tCLCL ± tRD
tSU;DAT2 SDA set-up time (before rep. START cond.) . 250ns > 1m s1
tSU;DAT3 SDA set-up time (before STOP cond.) . 250ns > 8 tCLCL
tHD;DAT Data hold time . 0ns > 8 tCLCL ± tFC
tSU;STA Repeated START set-up time . 14 tCLCL > 4.7m s1
tSU;STO STOP condition set-up time . 14 tCLCL > 4.0m s1
tBUF Bus free time . 14 tCLCL > 4.7m s1
tRD SDA rise time 3 1m s ±2
tFD SDA fall time 3 0.3m s < 0.3m s3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1m s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 63ns (42ns) < tCLCL < 285ns (16MHz (24MHz) > fOSC > 3.5MHz) the SIO1
interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.

TIMING SIO1 (I2C) INTERFACE

repeated START condition

START or repeated START condition tSU;STA START condition
STOP condition
tRD

SDA 0.7 VDD

(INPUT/OUTPUT) 0.3 VDD

tBUF
tFD tRC tFC
tSU; STO

0.7 VDD
SCL
(INPUT/OUTPUT) 0.3 VDD

tSU;DAT3

tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2

1998 Jan 06 14
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The Q ± Output data
first character is always `t' (= time). The other R ± RD signal
characters, depending on their positions, t ± Time
indicate the name of a signal or the logical V ± Valid
status of that signal. The designations are: W ± WR signal
A ± Address X ± No longer a valid logic level
C ± Clock Z ± Float
D ± Input data Examples: tAVLL = Time for address valid
H ± Logic level high to ALE low.
I ± Instruction (program memory contents) tLLPL = Time for ALE low
L ± Logic level low, or ALE to PSEN low.
P ± PSEN

tLHLL
ALE

tPLPH
tAVLL
tLLPL
tLLIV
PSEN tPLIV
tPXIZ
tLLAX tPLAZ
tPXIX

PORT 0 A0A7 INSTR IN A0A7

tAVIV

PORT 2 A8A15 A8A15

Figure 2. External Program Memory Read Cycle

ALE

tWHLH

PSEN

tLLDV

tLLWL tRLRH
RD

tAVLL tLLAX tRLDV tRHDZ

tRHDX
tRLAZ
PORT 0 A0A7
FROM RI OR DPL DATA IN A0A7 FROM PCL INSTR IN

tAVWL
tAVDV
PORT 2 P2.0P2.7 OR A8A15 FROM DPH A8A15 FROM PCH

Figure 3. External Data Memory Read Cycle

1998 Jan 06 15
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

ALE

tWHLH

PSEN

tLLWL tWLWH
WR

tLLAX
tAVLL tQVWX tWHQX
tDW

PORT 0 A0A7
FROM RI OR DPL DATA OUT A0A7 FROM PCL INSTR IN

tAVWL

PORT 2 P2.0P2.7 OR A8A15 FROM DPH A8A15 FROM PCH

Figure 4. External Data Memory Write Cycle

INSTRUCTION 0 1 2 3 4 5 6 7 8

ALE

tXLXL

CLOCK

tXHQX
tQVXH
OUTPUT DATA

WRITE TO SBUF
tXHDV tXHDX
SET TI
INPUT DATA
VALID VALID VALID VALID VALID VALID VALID VALID
CLEAR RI

SET RI
Figure 5. Shift Register Mode Timing

1998 Jan 06 16
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

VIH1
0.8V
tCHCX
tCHCL tCLCX tCLCH

tCLCL

Figure 6. External Clock Drive at XTAL1

VDD0.5
0.2VDD+0.9 VLOAD+0.1V TIMING VOH0.1V
VLOAD REFERENCE
0.2VDD0.1 POINTS
VLOAD0.1V VOL+0.1V
0.45V

NOTE: NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT VDD±0.5 FOR A LOGIC `1' AND FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
0.45V FOR A LOGIC `0'. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A
100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > +
LOGIC `1' AND VIL MAX FOR A LOGIC `0'. 20mA.

Figure 7. AC Testing Input/Output Figure 8. Float Waveform

1998 Jan 06 17
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

VDD VDD

IDD IDD

VDD VDD
VDD VDD RST VDD

EA
P0 P0
RST
EA
P1.6 * P1.6 *
(NC) XTAL2 (NC) XTAL2
P1.7 * P1.7 *
CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1

VSS VSS

Figure 9. IDD Test Condition, Active Mode Figure 10. IDD Test Condition, Idle Mode
All other pins are disconnected All other pins are disconnected

VDD

IDD

VDD
RST VDD

EA
P0

(NC) XTAL2 P1.6 *

P1.7 *
XTAL1

VSS

Figure 11. IDD Test Condition, Power Down Mode

All other pins are disconnected. VDD = 2V to 5.5V

NOTE:
* Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not
exceed the IOL1 specification.

Purchase of Philips I2C components conveys a license under the Philips' I 2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.

1998 Jan 06 18
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

1998 Jan 06 19
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

1998 Jan 06 20
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

1998 Jan 06 21
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1

1998 Jan 06 22
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

NOTES

1998 Jan 06 23
Philips Semiconductors Product specification

CMOS single-chip 8-bit microcontroller 83C654

Data sheet status

Data sheet Product Definition [1]
status status

Objective Development This data sheet contains the design target or goal specifications for product development.
specification Specification may change in any manner without notice.

Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date.
specification Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make
specification changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions
Short-form specification – The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition – Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information – Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers
Life support – These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes – Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors Ω Copyright Philips Electronics North America Corporation 1998

811 East Arques Avenue All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 940883409 Date of release: 06-98
Telephone 800-234-7381
Document order number: 9397 750 04048

 
   
1998 Jan 06 24