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Fpga Lab1

The document details an experiment to implement a 4-bit Ripple Carry Adder (RCA) using Quartus Prime and ModelSim simulation tools on a Cyclone V SoC FPGA. The RCA successfully adds two 4-bit binary numbers with a carry-in and displays the result as a two-digit decimal value on 7-segment displays. The code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

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janardhanan1711
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13 views5 pages

Fpga Lab1

The document details an experiment to implement a 4-bit Ripple Carry Adder (RCA) using Quartus Prime and ModelSim simulation tools on a Cyclone V SoC FPGA. The RCA successfully adds two 4-bit binary numbers with a carry-in and displays the result as a two-digit decimal value on 7-segment displays. The code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

Uploaded by

janardhanan1711
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT -1
RIPPLE CARRY ADDER

VERIFICATION:

AIM: To perform the Ripple Carry Adder experiment using Quartus Prime with
the ModelSim simulation tool and the hardware 5CSXFC6D6F31C6 (Cyclone
V SoC FPGA)

CODE:
module RIPPLE_CARRY(a, b, cin, sum, cout, seg1, seg2);
input [3:0] a, b;
input cin;

Girijesh Kumar P R 22BEC1021


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output wire [3:0] sum;


output cout;
output [6:0] seg1, seg2;

wire cout1, cout2, cout3;


FullAdder FA1(a[0], b[0], cin, sum[0], cout1);
FullAdder FA2(a[1], b[1], cout1, sum[1], cout2);
FullAdder FA3(a[2], b[2], cout2, sum[2], cout3);
FullAdder FA4(a[3], b[3], cout3, sum[3], cout);

wire [3:0] tens_digit, ones_digit;

assign tens_digit = sum / 10;


assign ones_digit = sum % 10;

segment7 SEG1(tens_digit, seg1);


segment7 SEG2(ones_digit, seg2);
endmodule

module FullAdder(a, b, cin, sum, cout);


input a, b, cin;
output wire sum, cout;
wire s1, c1, c2, c3;

xor(s1, a, b);
xor(sum, s1, cin);
and(c1, a, b);
and(c2, b, cin);

Girijesh Kumar P R 22BEC1021


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and(c3, a, cin);
or(cout, c1, c2, c3);
endmodule

module segment7(bcd, seg);


input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;

always @(bcd)
begin
case (bcd)
4'b0000 : seg = 7'b0000001;
4'b0001 : seg = 7'b1001111;
4'b0010 : seg = 7'b0010010;
4'b0011 : seg = 7'b0000110;
4'b0100 : seg = 7'b1001100;
4'b0101 : seg = 7'b0100100;
4'b0110 : seg = 7'b0100000;
4'b0111 : seg = 7'b0001111;
4'b1000 : seg = 7'b0000000;
4'b1001 : seg = 7'b0000100;
default : seg = 7'b1111111;
endcase
end
endmodule

Girijesh Kumar P R 22BEC1021


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OUTPUT:
A=3 B=3 C=0  A+B+C=06

A=7 B=5 C=0  A+B+C=12

Girijesh Kumar P R 22BEC1021


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RESULT: The experiment successfully implemented a 4-bit Ripple Carry Adder


(RCA) with a 7-segment display decoder on an FPGA using Quartus Prime
and ModelSim for simulation. The RCA correctly performed the addition of two
4-bit binary numbers along with a carry-in input. The sum was displayed as a
two-digit decimal value on two 7-segment displays.

Girijesh Kumar P R 22BEC1021

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