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Fpga Lab2

The document outlines the design and implementation of a 4-bit Up/Down Counter using an FPGA, with the goal of incrementing or decrementing a count value based on a control input. The code includes modules for slow clock generation, counter logic, and a seven-segment display decoder. The experiment successfully demonstrated the counter's functionality, displaying the correct count values on the 7-segment display.

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4 views5 pages

Fpga Lab2

The document outlines the design and implementation of a 4-bit Up/Down Counter using an FPGA, with the goal of incrementing or decrementing a count value based on a control input. The code includes modules for slow clock generation, counter logic, and a seven-segment display decoder. The experiment successfully demonstrated the counter's functionality, displaying the correct count values on the 7-segment display.

Uploaded by

janardhanan1711
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Page 1 of 5

EXPERIMENT -2
UP-DOWN COUNTER

VERIFICATION:

AIM: To design and implement a 4-bit Up/Down Counter interfaced with a 7-


segment display on an FPGA using Quartus Prime for synthesis, ModelSim for
simulation, and hardware with a 5CSXFC6D6F31C6 device. The goal is to
increment or decrement a 4-bit count value based on a control input, displaying
the output on a 7-segment display.

CODE:
module UPDOWN(input clk,input rst,input up_down,output [6:0]seg);

wire c1;

Girijesh Kumar P R 22BEC1021


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wire [3:0]c2;
slow_clk s1(.clk(clk),.rst(rst),.slowclk(c1));
up_down_counter u1(.clk(c1),.rst(rst),.up_down(up_down),.count(c2));
seven_segment_decoder s2(.count(c2),.seg(seg));
endmodule

module slow_clk(clk,rst,slowclk);
input clk,rst;
output slowclk;
reg[25:0]count;
always@(posedge clk)
begin
if(rst)
count<=0;
else
count<=count+1;
end
assign slowclk=count[25];
endmodule

module up_down_counter(
input clk,
input rst,
input up_down,
output reg [3:0] count
);
always @(posedge clk or posedge rst) begin

Girijesh Kumar P R 22BEC1021


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if (rst) begin
count <= 4'b0000;
end
else begin
if (up_down) begin
count <= count + 1;
end
else begin
count <= count - 1;
end
end
end
endmodule

module seven_segment_decoder(
input [3:0] count,
output reg [6:0] seg
);
always @(count) begin
case(count)
4'b0000: seg = 7'b1000000; // 0
4'b0001: seg = 7'b1111001; // 1
4'b0010: seg = 7'b0100100; // 2
4'b0011: seg = 7'b0110000; // 3
4'b0100: seg = 7'b0011001; // 4
4'b0101: seg = 7'b0010010; // 5
4'b0110: seg = 7'b0000010; // 6
4'b0111: seg = 7'b1111000; // 7

Girijesh Kumar P R 22BEC1021


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4'b1000: seg = 7'b0000000; // 8


4'b1001: seg = 7'b0010000; // 9
default: seg = 7'b1111111; // Blank
endcase
end
endmodule

OUTPUT:
WHEN UP_DOWN SWITCH IS HIGH THE COUNTER INCREMENTS i.e.
FROM 0 TO 9

WHEN UP_DOWN SWITCH IS LOW THE COUNTER DECREMENTS i.e.


FROM 9 TO 0

Girijesh Kumar P R 22BEC1021


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RESULT:
The experiment successfully implemented a 4-bit Up/Down Counter on the
FPGA. The counter operated as expected, incrementing or decrementing the
count value based on the control input (UP/DOWN). The count values were
displayed correctly on the 7-segment display.

Girijesh Kumar P R 22BEC1021

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