NON-VON NEUMANN

COMPUTER
ARCHITECTURE

Presented by Group 6:

PRIYAL BANERJEE (BTECH/CSE/22/090)

SATAKSHI PODDAR (BTECH/CSE/22/074)
HIMEL DUTTA (BTECH/CSE/22/133)
SAYAN BHATTACHARJEE (BTECH/CSE/22/094)
SAPTARSHI DEY (BTECH/CSE/22/108)
 Synopsis of the Architecture
Key Differences from Von Neumann :
Non-Von Neumann Architecture refers to computing models that
Data I/P
deviate from the traditional concept of Von Neumann Architecture ALU
of Stored-Program Mechanism where both Instructions and Data Memory
share the same Memory and are Processed Sequentially
Instruction
It seeks to counter the "Von Neumann Bottleneck" and CU O/P
Memory
Performance Issues caused by slow data transfer between the
CPU and Memory
Memory CPU
Non-Von Neumann Overview : Fig 1: Von Neumann Architecture Block Diagram
The basic idea of various Non-Von Neumann Architectures like
Dataflow Architecture or the Harvard Architecture is to implement
Parallelism and use Separate Memory for Instructions and Data
Advanced Architectures using Quantum Bits (qubits), Light Photons, etc. for Quantum Computing and Optical
Computing provides a Fundamentally Different Processing Approach, offering Faster Processing Speeds at
Higher Bandwidth compared to Classical Architectures

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 Components Analysis
Input and Output Unit (I/O) :
These Units are used for basic Input-Output Operations
involving taking Instructions and Displaying their Results Data
ALU I/P
Memory
Central Processing Unit (CPU) :
>>> ALU : Instruction CU O/P
It performs all the Arithmetic (+, -, *, /) and Logical (and,
Memory
or, not) Operations
>>> CU : CPU
It basically supervises the working of the various parts of
the Computer like the Fetch-Decode-Execute Cycle Fig 2: Non Von Neumann Architecture Block Diagram

Memory Unit :
>>> Instruction Memory :
This is the Memory Unit used to store the Instructions given by the user which are Fetched during
Instruction Decoding by the CU (Fetch-Decode)
>>> Data Memory :
This is the Memory Unit used to store the Data Values needed during ALU Operations (Execute)

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 Mechanism and Work Flow
Input : D
I/P O/P is

n
io
pl
Initially, an Input is received from an external source ay

ct
ru
st
In
Instruction Storage : CU CU
The Data of the Input is stored in the Data Memory and the

e
od

Ou
Da
pc
Instruction is stored in the Instruction Memory which is

tpu
ta
O

t
controlled by the Control Unit (CU) Inst Data Da
ta
Data
Fe
Mem Mem tc
h Mem

Fetch-Decode : O
pc
od
e ALU Resul
t
Fe
The CU thereafter fetches the Instruction from the Instruction Memory tc
h CU e
ecod
and Decodes it to determine the Operation to be performed on the data D

Fig 3: Work Flow Diagram

Execute :
The ALU then performs the required Arithmetic or Logical Operations on the Data

Result Storage and Output :

After the computation, the Result is stored in the Data Memory and displayed to the Output Device by the CU

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 Advantages and Disadvantages
Advantages :
Enables massive parallel processing with simultaneous computations
The Von Neumann bottleneck of using shared memory is reduced by implementing separate data and
instruction pathways
Since this Architecture uses Separate Memory for Instructions and Data Storage, processing of an Instruction is
much faster
Provides mechanisms for optimization to perform tasks related to AI, ML and cryptography which are
implementable in Neuromorphic and Quantum Computing Architectures

Disadvantages :
Since it uses separate Memory for Data and Instructions, it may require a large Board Space for Memory
Implementation compared to Von Neumann Architecture
Non-Von Neumann Architectures excel in AI and Quantum Simulations but are less suited for general-purpose
computing, often needing hybrid or specialized setups
Implementation requires expensive specialized Hardwares, like Quantum Processors, FPGAs, etc
Many Non-Von Neumann Architectures are still in development, with very less Practical Feasibility due to the
requirement of new programming paradigms and lack of mature development tools

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 Applications and Future Scopes
Applications :
Used to handle large Data Sets in parallel, optimizing and boosting performance in tasks like Simulations and
Computations, thus reducing problem-solving time and implement parallel computations
Applied in power-sensitive environments, such as mobile and embedded systems which enable real-time
processing with minimal energy use
Essential for real-time systems, these architectures allow rapid decision-making in like self-driving cars and
medical diagnostics

Future Scopes :
Neuromorphic computing is poised to revolutionize AI by mimicking human brain functionality, allowing for
more efficient, faster, and low-power systems for deep learning and real-time decision-making
Dataflow and Parallel-Processing Architectures can improve efficiency in scientific simulations, big data
analytics, and real-time processing in various industries
Development of Low-power Non-Von Neumann Architectures are key to edge computing, enabling real-time
IoT processing with minimal energy
Development of Hybrid Architectures that combine Von Neumann and Non-Von Neumann Models can offer
versatile systems for handling both general and specialized tasks

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THANK YOU