UNIT 2

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 Microprocessor is a program-controlled
device, which fetches the instructions
from memory, decodes and executes the
instructions. Most Micro Processor are
single- chip devices.

The 8086 (also called iAPX86) is a

Definition & 16-bit microprocessor chip
designed by Intel between early
specification 1976 and mid-1978.

16-bit processor, 16-bit data bus, 16-bit

general purpose registers, 20-bit address
bus-which can address 1 MB of memory,
1st member of 80x86 family, concept of
segmented memory, new instruction set
supported by all upcoming processors of
the family 80x86.
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 Released by Intel in 1978
Produced from 1978 to 1990s
A 16-bit microprocessor chip.
Max. CPU clock rate : 5 MHz to 10 MHz
Key Package: 40 pin DIP

Features Intel 8086 Microprocessor

The 8086 gave rise to the x86 architecture of Intel's

future processors.

Common manufacturer(s): Intel, AMD, NEC, Fujitsu,

Harris (Intersil), OKI, Siemens AG, Texas
Instruments, Mitsubishi.

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 Comparison b/w 8085 & 8086

Parameters 8085 8086

Size It is an 8-bits Processor It is a 16-bits Processor
Address Bus The address bus is 16 bits The address bus is 20 bits
Memory The memory capacity is 64 KB. Also, The memory capacity is 1 MB.
8085 Can Perform Operation Up to Also, 8086 Can Perform
28 i.e. 256 numbers. A number operations up to 216 i.e. 65,536
greater than this is to be taken numbers.
multiple times in an 8-bit data bus.
I/Os The input/output port addresses are The input/output port addresses
8 bits. It can address 256 I/O ports are 16 bits. It can address 65536
I/Os
Coprocessor It does not support coprocessor It has coprocessor interface.
Interface interface Coprocessor 8087 can be
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 Comparison b/w 8085 & 8086
Parameters 8085 8086
Multiplication It does not have instruction that It supports instruction that
and Division computes multiplication and division computes multiplication and
division
Clock speed It operates on 3MHz, 5MHz low clock The operating frequency is 5 MHz,
speed 8 MHz, and 10 MHz.
Operating 8085 MP has a Single Mode Of 8086 MP has Two Modes Of
Modes Operation. Operation. 1. Minimum Mode =
Single CPU PROCESSOR 2.
Maximum Mode = Multiple CPU
PROCESSOR.
Pipelining It does not support pipelining (No It supports pipe-lining as it has two
Instruction Queue). independent units Execution Unit
(EU) and Bus Interface Unit (BIU).
(Instruction Queue)
Memory Memory space is not segmented. Memory space is segmented.
Segmentation
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 Comparison b/w 8085 & 8086
Parameters 8085 8086
Flags It consists of 5 flags(Sign Flag, Zero It consists of 9 flags(Overflow Flag,
Flag, Auxiliary Carry Flag, Parity Flag, Direction Flag, Interrupt Flag, Trap
and Carry Flag). Flag, Sign Flag, Zero Flag, Auxiliary
Carry Flag, Parity Flag, and Carry
Flag).
Addressing There are 5 Addressing Modes. There are 11 addressing modes.
Modes
Cost It is a low-cost Microprocessor It is a comparatively High-cost
Microprocessor.
Interrupts It provides 8 software vectored It supports 256 software vectored
interrupts and five hardware interrupts and 2 hardware
interrupts interrupts

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Architecture of 8086

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 BIU handle all Transfer of Data
& Address on buses
Sends Addresses

Fetch Instruction from memory

BIU ( Bus
Read Data from memory/ports
Interface Unit)
Write Data to memory/ports

Includes 4 Segment Register

BIU has an array of 6 Registers
called Queue.
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 An instruction pointer (IP)
Register

BIU ( Bus Address generation and bus

Interface Unit) control

It consists of ALU

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 Read instructions from Queue,
Decode & Execute.

EU 16-bit Arithmetic unit, 16-bit flag

Register, four General purpose
(Execution Register, four 16-bit offset
Register.
unit)
Pipelining (The process of
fetching the next instruction
while the current instruction is
executing).

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1.The process of fetching the next
FIFO
instruction when the present instruction
is being executed is called as pipelining.
2.Pipelining has become possible due to
the use of queue.
3.BIU (Bus Interfacing Unit) fills in the
queue until the entire queue is full.
4.BIU restarts filling in the queue when
at least two locations of queue are
vacant.

Advantages of pipelining:

•The execution unit always reads the next instruction byte from the queue in BIU. This is
faster than sending out an address to the memory and waiting for the next instruction byte
to come.
•In short pipelining eliminates the waiting time of EU and speeds up the processing. -The
8086 BIU will not initiate a fetch unless and until there are two empty bytes in its queue.
8086 BIU normally obtains two instruction bytes per fetch.
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Registers of 8086

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 AX (Accumulator)

BX (Base Register)

CX (Counter Register)

General DX (Data Register)

purpose
registers
DX:AX together can be used as a 32 bits operand
BX is used for indirect addressing mode. MOV [BX], AX
CX is used for looping instruction, shift and rotate(CL),
and string instruction (for size of string)
DX is used with AX in case MUL & DIV when size is
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greater than AX
 Flag register

CY (Carry Flag)

P (Parity Flag)
In 8086 there are 6 different flags AC (Auxiliary Carry Flag)
which are set or reset after 8-bit or Status Flags
16-bit operations. Z (Zero Flag)

S (Sign flag)

OF (Overflow Flag)
In 8086 there are 3 different flags DF (Direction Flag)
which are used to enable or disable
some basic operations of the Control Flags IF (Interrupt Flag)
microprocessor. TF (Trap Flag)
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Flag Register

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 Flag Register
Overflow flag
If the result of an arithmetic operation on signed binary numbers performed by the CPU falls
inside the range, then OF = 0. OF = 1 if the signed result is out of bounds. The 8-bit signed
number range is from +7F to -80H, and the 16-bit signed number range is from +7FFF to -
8000H.

Directional flag
This is used in string related operations. DF = 1, then the string will be accessed from higher
memory address to lower memory address, and if DF = 0, it will do the reverse.

Interrupt flag
The hardware interrupt pin INTR can be enabled or disabled using the interrupt flag. When the
interrupt flag is set to zero with the CLI (Clear interrupt flag) instruction, the INTR interrupt is
disabled and the microprocessor will not recognize interrupt request from peripheral.

Trap Flag
This trap flag is used for on-chip debugging. When TF = 1, it will work in a single step mode.
After each instruction, one internal interrupt is generated. It helps to execute some program
instruction by instruction.
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 Pointer and Index Register
In 8086 Microprocessor, they usually store the offset through which the actual address is
calculated.

Instruction Pointer (IP):

The instruction pointer usually stores the address of the next
instruction that is to be executed. Apart from this, it also acts as an
offset for CS register.
Base Pointer (BP):
The Base pointer stores the base address of the memory. Also, it acts as
an offset for Stack Segment (SS).
Stack Pointer (SP):
The Stack Pointer Points at the current top value of the Stack. Like the
BP, it also acts as an offset to the Stack Segment (SS).
The indexes are used with the extra segment and they usually are used
for copying the contents of a particular block of memory to a new
location.
Source Index (SI):
It stores the offset address of the source.
Destination Index (DI):
It stores the offset address of the Destination.
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 BIU has 4 segment buses, i.e. CS, DS, SS& ES. It
holds the upper 16-bits starting addresses of
instructions and data in memory, which are used
by the processor to access memory locations.

Code Segment (CS)

Segment
Data Segment (DS)
Register
Stack Segment (SS)

Extra Segment (ES)

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 Segment Registers
CS − It stands for Code Segment. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program andis accessed in
the data segment by an offset address or the content of other register that holds the offset
address.
SS − It stands for Stack Segment. It handles memory to store data and addresses during
execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used by the string
to hold the extra destination data.

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 Physical Address Calculation
Physical Address: The 20-bit address of a byte
is called its physical Address.
But, it is specified as a Logical Address.
Logical address is in the form of:
Base Address : Offset
Offset is the displacement of the memory
location from the starting location of the
segment.

Address Generation Circuit:

•The BIU has a Physical Address Generation Circuit.
•It generates the 20-bit physical address using Segment and Offset addresses using the
formula:
•In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the
calculation unit which is used to calculate the physical address of an instruction in memory.
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 Physical Address = Segment Address x 10H + Offset Address

Q. The value of Code Segment (CS) Register is 4042H and the value of different offsets is as
follows:
BX: 2025H , IP: 0580H , DI: 4247H
Calculate the effective address of the memory location pointed by the CS register.

Q. The value of the DS register is 3032H. And the BX register contains a 16 bit value
which is equal to 3032H. 0008H is added to BX.
ADD BX, 0008H
The register AX contains some value which needs to be stored at a location as follows:
MOV [BX], AX
Calculate the address at which the value of the AX will be stored.

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 Memory Segmentation
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance
the speed of execution of the computer system, so that the processor is able to fetch and
execute the data from the memory easily and fast.

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 Memory Segmentation
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one
of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of
the starting addresses of the four memory segments of 64 KB each with which the 8086 is
working at that instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It is an independent,
separately addressable unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However, it
works only with four 64KB segments within the whole 1MB memory.

Types of Segmentation

Non-
Overlapping overlapping
A segment starts at a particular address and its A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if maximum size can go up to 64kilobytes. But if
another segment starts along with this another segment starts before this 64kilobytes
64kilobytes location of the first segment, then location of the first segment, then the two
the two are said to be Overlapping Segment. segments are said to be Non-Overlapped
Segment.
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 Memory Segmentation
Advantages of the Segmentation:
The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows
the use of 16 bit registers to give an addressing capability of 1 Megabytes.
Without segmentation, it would require 20 bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond
64 KB by allotting more than one segment for each area.

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