Title: Designing Multiplexer (MUX) and De-multiplexer (DEMUX), Encoder and Decoder

Circuits.

Introduction: In this experiment, students will explore the design and implementation of
multiplexers (MUX) and demultiplexers (De-MUX) of various sizes using fundamental logic
gates. They will also learn how to build larger multiplexers by combining smaller ones.
Additionally, students will construct encoder and decoder circuits, which play a crucial role
in information transmission, conversion, compression, and ensuring the confidentiality of
data.

Theory and Methodology:

Part I: Multiplexer and De-multiplexer

A multiplexer (MUX) is a device that selects one input from multiple options and forwards it
to a single output line. With 2n inputs, it uses n selection lines to choose the input, earning it
the name "data selector."

A de-multiplexer (or de-mux) is a device taking a single input and selecting one of many
data-output- lines, which is connected to the single input.

Multiplexer:
In computer system, it is often necessary to choose data from exactly one of a number of
possible sources. Suppose that there are four sources of data, provided as input signals
D0 ,D1, D2 and D3. The values of these signals change in time, perhaps at regular intervals.
We want to design a circuit that produces an output that has the same value as either D0 or
D1 or D2 or D3, dependent on the values of two selection pins S1 and S0. Here, the number
of selection pin is two. Four combinations are possible using these two selection pins S1 and
S0, such as (S1, S0) = (0,0), (0,1), (1,0), (1,1). Each combination is dedicated for each input.
Let us consider the output variable is f. Now if S1 = 0 and S0 = 0 then f = D0, if S1 = 0 and
S0 = 1 then f = D1, if S1 = 1 and S0 = 0 then f = D2 and if S1 = 1 and S0 = 1 then f = D3.

It is important to know that there is a relationship between the number of input and the
number of selection pins. If the number of selection pin of a MUX is n, then maximum 2n
inputs are possible for that MUX. And the MUX will be called as 2n to 1 line MUX. The
MUX we are going to design is a 4-to-1 MUX. There could be also 2to1 MUX, 8to1 MUX,
16to1 MUX etc.

For our design, there are 4 inputs and 2 selection pins. So, we have 6 inputs. Now if we draw
the truth table for 6 different inputs, there will be 64 (26) input combinations. But, fortunately
we can do it in a more convenient way as given below.
From the above truth table, we can write the function as given below.

𝑓 = 𝑆̅1𝑆̅0𝐷0 + 𝑆̅1𝑆0𝐷1 + 𝑆1𝑆̅0𝐷2 + 𝑆1𝑆0𝐷3 (1)

The logic circuit of the equation (1) is given in figure 1.

De-multiplexer:

A De-multiplexer or De-mux is opposite to the multiplexer. It has only one input and several
outputs and one or more selection pins. Depending on the combination of selection input, the
data input will be routed to one of many outputs. Other inputs will be low. Depending on the
number of output, demultiplexers are termed as 1to2, 1to4 and 1to8 demultiplexers etc. If the
number of selection pin is n, then maximum 2n outputs can be accommodated.
We are going to design a 1to4 line de-mux having an input Din, two selection pins S1 and S0
and four outputs D0 ,D1, D2 and D3. Now if S1 = 0 and S0 = 0 then D0 = Din, if S1 = 0 and
S0 = 1 then D1 =Din, if S1 = 1 and S0 = 0 then D2 = Din and if S1 = 1 and S0 = 1 then D3 =
Din. We can draw the truth table as given below.
From the above truth table we can write the functions for D0, D1, D2 and D3 as given below.

It is also possible to construct 4-to-1 multiplexer (and 1-to-4 de-multiplexer) using 2-to-1
multiplexers (1- to-2 demultiplexers) only. Figures 3 and 4 show the construction of 4-to-1
multiplexer using 2-to-1 multiplexers and 1-to-4 de-multiplexer using 1-to-2 de-multiplexers
only.

Fig. 3: 4-to-1 multiplexer using 2-to-1 multiplexers.

Fig. 4: 1-to-4 de-multiplexer using 1-to-2 demultiplexers.

Part II: Encoder and Decoder:

An encoder is a circuit that transforms information from one format or code to another, while
a decoder performs the opposite function, recovering the original information from the
encoded data. Both are types of combinational circuits.

Encoding and decoding are widely utilized concepts with applications in electronic circuits,
software, medical devices, telecommunications, and more. In this experiment, a simple 2-to-4
line decoder and a decimal-to-BCD encoder will be built.
A decoder can convert binary information from n input lines to a maximum of 2n unique
output lines. The 2-to-4 line decoder will take inputs from two lines and convert them to 4
lines.

The expressions for implementing 2-to-4 line decoder are

Truth table for 2-to-4 line decoder is given below –

Priority encoder:
A priority encoder is a circuit or algorithm that reduces multiple binary inputs into fewer
outputs. It provides the binary representation of the most significant active input, starting
from zero. Priority encoders are commonly used to handle interrupt requests, prioritizing the
highest-priority signal.

In this experiment a 4-to 2 priority encoders with a priority sequence of 2,1,3,0 has been
shown. It means, in this priority encoder 2 has the highest priority and 0 has the lowest. If 2 is
high then other numbers are ignored (even if any of them are high at the same time) and
output would be binary representation of 2, i.e., Y1Y0=10. If 2 is found to be low, then next
priority is given to 1. So, in this case if 1 is high, then 3 and 0 are ignored and output will be
binary representation of 1, i.e., Y1Y0=01 and so on.

In this experiment a 4-to 2 priority encoder with a priority sequence of 2,1,3,0 has been
shown. It means, in this priority encoder 2 has the highest priority and 0 has the lowest. If 2 is
high then other numbers are ignored (even if any of them are high at the same time) and
output would be binary representation of 2, i.e., Y1Y0=10. If 2 is found to be low, then next
priority is given to 1. So, in this case if 1 is high, then 3 and 0 are ignored and output will be
binary representation of 1, i.e., Y1Y0=01 and so on.

Fig. 7: 4-to 2 priority encoder with a priority sequence of 2,1,3,0

The expressions for implementing the above priority encoder–

Y0 = A2’.A1 + A3.A2’.A1’ Y1 = A2 + A3.A2’.A1’

Truth table for this priority encoder is given below –

Pre-Lab Homework:
Read about the characteristics of encoder and decoder circuits from any book or websites and
use PSIM to generate the output of the circuits provided in this lab sheet. Save the simulation
results and bring it to the lab.

Precautions:
1. Make sure that all the LEDs and the toggle switches of the trainer board are working
properly.
2. Do not short any connections. Short connection can produce heat (due to high current
flow) which is harmful for the components.
Experimental Procedure:
1. The circuits were connected to according to the figures.
2. The toggle switches on the trainer board were used for providing input signal to the
circuits.
The outputs were connected to the LEDs on the trainer board.
3. The input signals were applied and the corresponding output signals were observed and
noted.
Simulation and Measurement:
Results/ Findings:

All circuits were successfully simulated, truth tables matched simulation results without
discrepancies. Multiplexers enhance data transmission by enabling multiple connections over
a single channel, improving efficiency. A demultiplexer (demux) distributes a single input to
multiple outputs, allowing signals to reach various devices. Encoders compress 2n inputs into
n output lines, producing a binary code for the active High input. Decoders perform the
reverse, using \( n \) inputs to activate one of \( 2^n \) outputs based on the input combination.
Encoder was not done physically but simulation has been attached.

References:
1. Thomas L. Floyd, “Digital Fundamentals” 9th edition, Prentice Hall.
2. M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall.