RISC AND CISC

RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction

Set Computer) are two distinct architectural approaches used in the design of
computer processors. Here’s a detailed comparison of the two:

RISC (Reduced Instruction Set Computer):

 Definition: A computer architecture that uses a small, highly optimized set
of instructions.
 Key Characteristics:
Simple Instructions: Each instruction performs a simple operation and executes in
a single clock cycle.

"Each instruction performs a simple operation"

 Simple Operation: Instructions in RISC architecture are designed to
perform one basic task at a time. These tasks could be:
o Loading data from memory to a register (LOAD).
o Storing data from a register to memory (STORE).
o Performing arithmetic or logical operations (ADD, SUB, AND, etc.)
between registers.
 RISC avoids complex multi-step instructions (as in CISC) where a
single instruction might perform tasks like fetching data, processing it,
and writing it back to memory.
"Executes in a single clock cycle"
 Clock Cycle: A clock cycle is the smallest unit of time in a processor,
governed by the system clock. It determines how quickly the processor
performs operations.
 In RISC:
 o Each instruction is designed to complete in one clock cycle.
o This is possible because:
 Instructions are simple and uniform.
 Hardware is optimized for these instructions, avoiding the need
for additional processing time.

Load/Store Architecture: Memory operations are limited to load and store

instructions; arithmetic and logical operations are performed only on registers.
 "Memory operations are limited to load and store instructions"
 In RISC architecture, the processor interacts with memory only through
specific instructions:
 LOAD: Transfers data from memory to a register.
 STORE: Transfers data from a register to memory.
 Reason for Limiting Memory Operations:
 Memory access is slower compared to operations performed within the CPU
(registers).
 By minimizing direct interaction with memory, RISC processors can
improve execution speed.
 "Arithmetic and logical operations are performed only on registers"
 After data is loaded from memory into registers:
 Arithmetic operations (e.g., addition, subtraction) and logical operations
(e.g., AND, OR, NOT) are performed using registers only, not directly on
memory.
 Registers are small, high-speed storage locations within the CPU, allowing
faster data access and processing compared to memory.

  Example
 Task: Add two numbers stored in memory and save the result back to
memory.
 In RISC Architecture:
 The steps would be:
 LOAD R1, A (Load the value from memory location A into register R1.)
 LOAD R2, B (Load the value from memory location B into register R2.)
 ADD R3, R1, R2 (Perform addition: R3 = R1 + R2.)
 STORE C, R3 (Store the result from R3 into memory location C.)
 Arithmetic operation (ADD) is performed only between registers.
 In CISC Architecture:
 The task might be performed with a single instruction:
 ADD A, B, C (Fetch A and B from memory, add them, and store the result in
memory location C.)
 Arithmetic operations can be performed directly on memory.
Fixed Instruction Length: Instructions have a uniform size, simplifying decoding.

 In RISC architecture, all instructions are of the same length (e.g., 32 bits or
16 bits).
 Uniformity: Each instruction occupies the same amount of memory,
regardless of its type or complexity.
 Contrast with CISC: In CISC (Complex Instruction Set Computer),
instructions can vary in length (e.g., 1 byte to 15 bytes in x86), depending on
the operation.

"Simplifying Decoding"

 The instruction decoder in the CPU translates binary instructions into

operations the processor can execute.
High Register Count: Many general-purpose registers to reduce memory access.
High Register Count"
 Definition: RISC processors are designed with a large number of general-
purpose registers (GPRs). These registers are small, fast storage locations
within the CPU, used to hold temporary data for computations.
 Purpose:
o To minimize the need to access slower main memory.
o To store frequently used data, intermediate results, and program
variables for quick access.
2. "To Reduce Memory Access"
 Accessing main memory (RAM) is much slower than accessing registers.
 By increasing the number of registers:
o Most computations can be performed directly within the CPU.
o Data is transferred to and from memory less frequently, reducing
memory bottlenecks and improving performance.

Pipelining: Designed to support efficient pipelining, improving instruction

throughput.
Pipelining is a technique where multiple instructions are overlapped in execution,
with different stages of an instruction processed simultaneously. Think of it as an
assembly line, where different parts of a task are completed in parallel.

Simple Addressing Modes.

 Advantages:
o Faster execution due to simple and uniform instructions.
o Easier hardware implementation.
 o Energy efficiency, making it suitable for embedded systems and
mobile devices.
 Disadvantages:
o Larger program size due to more instructions needed for complex
operations.
o Requires efficient compilers for optimized code generation.

CISC (Complex Instruction Set Computer):

 Definition: A computer architecture with a large set of instructions,
including many specialized ones.
 Key Characteristics:
Complex Instructions: Single instructions can perform multiple operations (e.g.,
load, multiply, and store in one step).
Breaking Down the Statement
1. "Complex Instructions"
 Definition: In CISC, a single instruction can execute multiple operations,
which might include:
o Loading data from memory.
o Performing a computation (e.g., multiplication).
o Storing the result back to memory.
 This is in contrast to RISC (Reduced Instruction Set Computer), where
instructions are simple and perform only one operation at a time.
2. "Single Instructions Can Perform Multiple Operations"
 In CISC, instructions are multi-step operations. For example:
 o A single instruction might load data from memory, process it, and
save it back, all within one command.
o These instructions are often designed to resemble high-level
programming constructs, such as loops or function calls.
3. "Example: Load, Multiply, and Store in One Step"
 Consider an instruction like MUL A, B, C in a CISC system:
o It fetches values from memory locations A and B.
o Multiplies them.
o Stores the result in memory location C.
 This single instruction replaces multiple simpler instructions in a RISC
system:
o LOAD R1, A (Load A into register R1)
o LOAD R2, B (Load B into register R2)
o MUL R3, R1, R2 (Multiply R1 and R2 and store the result in R3)
o STORE C, R3 (Store the result from R3 into memory location C)

Why Complex Instructions?

CISC architectures aim to:
1. Reduce Program Size:
o Fewer instructions are needed to perform complex operations,
reducing the size of the compiled code.
2. Simplify Programming:
o Complex instructions map closely to high-level language constructs,
making assembly programming easier.
3. Optimize Memory Usage:
 o Fewer instructions mean fewer memory accesses, which was critical
when memory was expensive and limited.

Advantages of Complex Instructions

1. Compact Code:
o Complex instructions can reduce the total number of instructions in a
program, saving memory.
2. Ease of Use:
o High-level, multi-step instructions make assembly-level programming
more intuitive.
3. Backward Compatibility:
o Legacy programs can continue to run on newer processors without
modification, as older instructions are preserved.

Challenges of Complex Instructions

1. Decoding Complexity:
o The CPU must handle variable-length instructions and decode multi-
step operations, requiring more complex hardware.
2. Slower Execution:
o Even though one instruction does more, it may take multiple clock
cycles to execute, potentially slowing down performance.
3. Pipeline Inefficiency:
o Complex instructions disrupt pipelining because their execution times
are unpredictable.

Variable Instruction Length: Instruction sizes can vary, complicating decoding.

Variable Instruction Length"
 Definition:
o In CISC, the length of instructions can vary depending on the
operation being performed and the addressing modes used.
o For example:
 Simple operations like ADD A, B might be encoded in 1 byte.
 Complex operations like MOV EAX, [123456] (move a value
from memory to a register) might require several bytes.
 Reason for Variability:
o The CISC architecture allows instructions of different complexities,
combining multiple operations and supporting complex addressing
modes. This flexibility leads to varying instruction sizes.
2. "Complicating Decoding"
 The instruction decoder in the CPU translates binary instructions into
actions the processor executes.
 With variable instruction lengths:
o The decoder must first determine the size of each instruction before
processing it.
o This adds complexity and increases decoding time, as compared to
architectures like RISC where instructions have fixed sizes.

Challenges of Variable Instruction Length

1. Decoding Complexity:
o The CPU needs additional logic to identify where one instruction ends
and the next begins.
o This makes the instruction decoder slower and more complex.
2. Pipeline Inefficiency:
 o In pipelined architectures, variable instruction lengths can cause
misalignment in instruction fetching and execution stages, introducing
delays.
3. Memory Access Overhead:
o Variable-sized instructions mean the CPU must fetch varying amounts
of data, complicating memory access and cache optimization.

Why Use Variable Instruction Length?

 Flexibility:
o Allows the inclusion of both simple and complex instructions,
reducing the overall number of instructions required to complete a
task.
 Compact Code:
o Smaller instructions are used for simple operations, minimizing
memory usage.
o Larger, more complex instructions reduce the number of instructions
in a program.

Advantages of Variable Instruction Length

1. Code Density:
o Programs can be smaller because fewer instructions are needed for
complex tasks.
2. Support for Complex Operations:
o Variable-length instructions allow a wide range of operations and
addressing modes, making CISC processors versatile.

Example
Variable-Length Instructions in CISC:
Instruction Length Description
MOV AL, 5 2 bytes Move the immediate value 5 into register AL.
MOV AX, [1234] 3 bytes Move data from memory address 1234 into AX.
MOVEAX, Move data from a 32-bit memory address into
6 bytes
[12345678] EAX.
 The instruction length varies based on the operation and addressing mode.
Fixed-Length Instructions in RISC:
 RISC instructions are typically fixed at 4 bytes (32 bits):
o LOAD R1, #5 → 4 bytes.
o ADD R2, R1, R3 → 4 bytes.
o STORE R2, [100] → 4 bytes.

Fewer Registers: More reliance on memory access.

"Fewer Registers"
 In CISC processors, the architecture typically includes a smaller number of
general-purpose registers compared to RISC processors.
o Registers: High-speed storage locations inside the CPU that store
temporary data for processing.
o CISC processors rely more on memory for storing variables,
intermediate results, and other data due to the limited number of
registers.
 Reason for Fewer Registers:
o CISC designs prioritize complex instructions that often directly
operate on memory.
 o These instructions reduce the need for many registers, as operations
don’t rely solely on registers for input/output.

Microprogramming: Instructions are often implemented using microcode.

What is Microprogramming?
Microprogramming is a method used to implement the control unit of a CPU.
Instead of using fixed hardware circuits to execute each machine-level instruction,
a set of instructions (called micro-operations) is executed under the control of a
microprogram stored in memory (known as microcode).
In simple terms, instead of the CPU having direct hardware circuits for each
instruction, the microprogram (or microcode) breaks down complex instructions
into simpler steps (micro-operations), and these steps are executed one by one to
complete the instruction. The process is similar to software running inside the CPU
to control its operations.

How Does Microprogramming Work?

1. Microcode Control
 Microcode is a low-level set of instructions that tell the control unit of the
CPU how to execute machine-level instructions.
 Each machine instruction (e.g., ADD, MOV, MULTIPLY) is mapped to a
series of simpler steps (called micro-operations), and these micro-operations
are executed sequentially.
 These micro-operations can involve fetching data, performing arithmetic, or
moving data between registers, memory, and the ALU (Arithmetic Logic
Unit).
2. Process of Execution
When a machine instruction is fetched from memory, the control unit:
 Decodes the instruction.
  Fetches the corresponding microprogram (microcode) from the control
store.
 Executes the micro-operations defined by the microprogram.

Example: Microcode for an ADD Instruction

Let’s take an example of a CISC processor executing an ADD instruction:
 Instruction: ADD R1, R2, R3 (Add the values in registers R1 and R2, and
store the result in R3).
Without microprogramming, the hardware would need separate circuits for every
type of operation, like addition, subtraction, etc. With microprogramming, the
processor uses a microprogram to break down the ADD instruction into smaller
steps.
1. Fetch the instruction ADD R1, R2, R3.
2. Decode the instruction to understand which registers are involved.
3. Load values from registers R1 and R2 into the ALU.
4. Perform the addition in the ALU.
5. Store the result back into register R3.
Each of these actions is handled by a specific micro-operation, and the sequence of
micro-operations is controlled by the microcode.

Hardwired vs. Microprogrammed Control

Feature Hardwired Control Microprogrammed Control
Uses fixed hardware
Control Uses microcode (software) to
circuits for each
Mechanism control operations.
instruction.
Feature Hardwired Control Microprogrammed Control
Faster, as it executes Slower, as it involves fetching
Speed
instructions directly. and executing micro-operations.
Inflexible; changes
Flexible; changes can be made by
Flexibility require redesigning
updating microcode.
hardware.
More complex hardware More complex in terms of
Complexity design for complex microcode management, but
instructions. simpler hardware.
Lower cost for hardware, but may
Higher cost due to more
Cost require more memory and time
complex hardware.
for microcode.

Complex Addressing Modes.

Complex Addressing Modes refer to the various ways that a processor can access
operands (data) in memory or registers. Addressing modes define how the effective
address of an operand is computed and how it can be accessed during the execution
of an instruction.
In some CPU architectures, particularly CISC (Complex Instruction Set
Computers), addressing modes can be quite sophisticated, enabling a single
instruction to perform multiple operations (such as fetching from memory,
performing an arithmetic operation, and storing the result). These complex
addressing modes are often designed to improve the efficiency of instructions and
reduce the need for multiple instructions.

 Advantages:
o Reduced program size due to powerful instructions.
o Easier programming as fewer instructions are required.
  Disadvantages:
o Slower execution due to complex instructions.
o Harder to implement pipelining, resulting in less efficient instruction
throughput.
o Higher power consumption and heat generation.
Comparison Table:
Feature RISC CISC
Instruction
Simple and limited Complex and extensive
Set
Execution
One clock cycle per instruction Multiple clock cycles
Time
Instruction
Fixed Variable
Length
Memory
More memory (longer code) Less memory (compact code)
Usage
Pipelining Easy to implement Difficult to implement
Power
Low High
Consumption
Desktop and general-purpose
Use Case Embedded systems, mobile devices
PCs

RISC processors like ARM, MIPS, and SPARC are optimized for speed and
efficiency through simplicity, while CISC processors like Intel x86, AMD64, and
VAX offer greater flexibility with more complex instruction sets, but typically at
the cost of slower execution per instruction.