Practice/Sample questions: CSE332

1. What do you understand by Instruction Set Architecture?

Instruction Set Architecture refers to instruction types, instruction format in low level as well as
in machine code and detailed descriptions of operand fields (addressing modes of instructions).
Instruction Set Architecture also defines:
• Operations that the processor can execute (add, sub, mult, …, how is it specified)
• Data Transfer mechanisms
• How to access data
• Number of operands (0, 1, 2, 3)
• Operand storage (where besides memory)
• Memory address (how is memory location specified)
• Type and size of operands (byte, int, float, …)
• Control Mechanisms (branch, jump, etc)

2. Discuss types/classification of processors based on Instruction set architecture.

Processors are divided into following classes based on instruction set architecture
Stack-based: The CPU is designed to read
Accumulator-based
Register-Register
Register-Memory
3. What is addressing mode? Discuss different types of addressing modes.

Operands in instructions may be indicated differently. For example, operands may be provided
directly, operands may be indicated by CPU registers, operands may be indicated by memory
addresses, assuming operands are saved in memory, operands may be saved in memory but
memory addresses are initially loaded into registers and operands are indicated indirectly by
registers in the operand fields.
How the operands are addressed/indicated in the operand fields, called addressing mode of
instruction. It is not related to operation or opcode of the instruction.
Addressing modes may be classified in three broad categories:
 Immedicate addressing mode
 Register addressing mode
 Memory addressing mode.
If operands or one of the operands is provided in operands/one of the operand fields, called
immedicate addressing mode. Example:
Opcode Result field Data-1 Data-2
..
Opcode Result field Data-1 Register

If all operands are indicated by CPU registers, called register addressing mode.
Opcode Result field Register for Data-1 Register for Data-2
..
Assume that, all or one of the operands are saved in memory. In an instruction, if operands or one
of the operands is indicated by memory address in operand fields/one of the operand fields, called
memory addressing mode. Example:
Opcode Memory address for Memory address for Memory address for
Result field Data-1 Data-2
..
Opcode Result field Memory address for Register
Data-1
If memory address is 16 bits or less, the address is directly provided in the operand field, called
direct memory addressing mode. Just to differentiate from data in immediate mode, memory
address is either enclosed within bracket or different opcode is used.

Opcode Result field [Memory address for Register

Data-1]
..
Different Opcode Result field Memory address for Register
Data-1
For large memory addresses (20 bits or more), memory addresses are initially loaded into some
special registers, called base or pointer or index or special purpose registers. In instructions,
operand or operands are indicated by one of those registers or register instead. This addressing
mode is called register indirect memory addressing mode.
Opcode Register pointing Register pointing Register pointing
Memory address for Memory address for Memory address for
Result field Data-1 Data-2
..
Opcode Result field Register pointing Register
Memory address for
Data-1

In such addressing modes, registers pointing memory addresses are marked differently, mostly
enclosed within bracket ‘[ ]’.
If base register is used in one of the operand fields to point memory address, called indirect base
register addressing mode.
If index register is used in one of the operand fields to point memory address, called indirect index
register addressing mode.
A number (8 bits/16bits) is also used with base or index register. This number is added to the
contents of base or index register to point memory location of operand, called relative base or
relative index register addressing mode.
Opcode Result field Number[BaseRegister] Register pointing
pointing Memory Data-2
address for Data-1
..
Opcode Result field Number[IndexRegister] Register
pointing Memory
address for Data-1

To use structured data or arrays, more than one registers are used to point memory location of
operand. The contents of these registers are simply added or content of one register is added to a
pre-defined multiple (scaled) of the content of another register and memory address is calculated.
In instructions, either both the registers are indicated within bracket and separated by comma of
plus sign or one is indicated while other remains implicit. Depending on registers used, addressing
mode is named. For example, in based-indexed addressing mode, one of the base and one of the
index registers are used to point memory address of one of the operands.

Opcode Result field [baseReg+indexReg] Register

pointing Memory
address for Data-1

Opcode [baseReg+indexReg] Register Register

pointing Memory
address for Result
field

Moreover, in some processor family, a number (8 bits or 16 bits) is also added to the contents of
multiple registers (base and index registers for example) and memory address is calculated. In such
instructions, number is also indicated with base and index register to indicate one of the operands,
called relative base-indexed addressing mode.

Opcode Result field Number[baseReg+indexReg] Register

pointing Memory address
for Data-1

Opcode Number[baseReg+indexReg] Register Register

pointing Memory address
for Result field

Memory address may have following variants

 direct memory addressing mode
 indirect base register addressing mode
 indirect index register addressing mode
  relative base register indirect addressing mode
 relative index register indirect addressing mode
 based-indexed indirect register addressing mode
 relative base-indexed indirect register addressing mode

4. What do you understand by instruction format? Discuss different types of instruction formats of
Instruction set architecture and CPU.
Following Instruction formats are used in different instruction set architecture and CPU design.

a) Three address formats: One destination and up to two operand sources per instruction
Opcode Result field Operand-1 Operand-2
..
Opcode Operand-1 Operand-2 Result field

b) Two address formats: the destination is same as one of the operand sources
Opcode Operand-1 (initially) Operand-2
Result field (after operation)
…
Opcode Operand-1 Operand-2 (initially)
Result field (after operation)

c) One address formats: Accumulator machines

Opcode 2nd operand
Here, accumulator is always other implicit operand and accumulator is implicit result field.

d) Zero address formats:

Both operands and result field remain implicit. Example: stack-based ALU instructions where both
operands are read from stack and result is also saved to stack. In such case, operands must be stored
to stack using special instruction: PUSH and then ALU instruction is used. The result is stored to stack
by default. However, for further/later uses, results or partial results can be saved to RAM using POP
instructions. A special register called Stack Pointer (SP) is used to point top location of stack. The SP
is designed to auto-increment or auto-decrement following PUSH, POP and ALU instructions.
Opcode
add M[sp-1] = M[sp] + M[sp-1]
load M[sp] = M[M[sp]]
– Stack can be in registers or in memory
– usually top of stack cached in registers

In some processors, zero address format is used to set or reset a particular bit of flag or status
register.

5. What do you understand by memory addressing mode? Discuss different variants of memory
addressing mode.
6. Show instruction
7. What is Accumulator-based CPU? Discuss some instructions and addressing modes of a commercial
accumulator based CPU (you can used 8085 as reference).
8. What are the functions of following registers:
Program Counter (PC), Instruction register (IR), Memory Address Register (MAR), Accumulator.
9. What do you understand by Instruction fetch?
10. How does the CPU calculate memory address of next instruction to be fetched?
11. How a CPU is designed to run program? Discuss the steps that the CPU is designed to follow in
processing an instruction.
12. How the Program Counter (PC) is updated while the CPU runs a program.
13. What is Control unit? What are the approaches to design control unit of CPU?
14. What do you understand by (i) microprogram (ii) microinstruction (iii) microoperation (iv) control
memory and (v) micro-programmed control unit?
15. List the important characteristics of CISC and RISC processors.
16. Discuss addressing modes of CISC and RISC processors.
17. What is pipelining architecture? List its benefits and challenges.
18. What do you understand by data dependency? Show how it affects pipeline architecture.
19. What is Branch Instruction? Show how it affects pipeline architecture.
20. What do you understand by Cycles Per Instruction (CPI) of an instruction? How does pipeline
architecture reduces average CPI of a program.
21. Write CPU performance equation and explain each term.
22. Compare the run time a program on RISC and CISC processor. Also comment on relative values.
23. Show the instruction formats of MIPS R2000 processor.