MODULE – 1

MICROPROCESSOR
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 TEXT BOOKS
1. Ramesh S. Gaonkar, ‘Microprocessor Architecture
Programming and Applications with 8085’, Penram Intl.
Publishing, 6th Edition, 2013.
2. Krishna Kant, ‘Microprocessors and Microcontrollers,
Architecture, Programming and System Design - 8085,
8086, 8051, 8096’, Prentice Hall India Ltd Publications,
1st Edition, 2010.
3. Kenneth Ayala, ‘The 8051 Microcontroller’, Cengage
Learning Publications, 2nd Edition, 2008.
4.John.B.Peatman , “ Design with PIC Microcontroller ,
Prentice hall, 2012.Dr. R. Sumathi,SKCET
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 REFERENCE BOOKS
1. Ray A.K., Bhurchandi K.M., ‘Advanced
Microprocessor and Peripherals’, Tata McGraw-Hill
Publications, 3rd Edition, 2013..
2. Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin
McKinlay, ‘The 8051 Microcontroller and Embedded
Systems using Assembly and C’, Prentice Hall
Publications, 2nd Edition, 2008.
3. Krishna Kant, ‘Microprocessor and Microcontrollers’,
Eastern Company Edition, Prentice Hall of India,
New Delhi, 2nd edition,2013.
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8085:
Functional block diagram
Signals
Memory interfacing
I/O ports
Timing Diagram
Interrupt structure
Instruction format and addressing modes
Assembly language format
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 8086:
Architecture
Instruction format and addressing
modes
Assembly language format.
Introduction to ARM
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 INTRODUCTION
• Language:
1. Low level language
• machine language - The software
developed using 1's and 0's
• assembly language - The software
developed using mnemonics
2. High level language - closer to human
languages
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 INTRODUCTION
• Bit – binary digit (0 and 1)
• Nibble – 4 bits
• Byte – 8 bits
• Word – 16 bits
• Double word – 32 bits
• Multiple word – 64, 128, 256….. bits
• Data – Quantity operated by an instruction of a program
• Address – Memory location for the binary information
• Memory word size – Size of the binary information that
can be stored in memory location
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 INTRODUCTION
• Microprocessor: It is a program controlled
semiconductor device (IC), which fetches, decodes
and executes instructions.
• It is used as a Central Processing Unit (CPU) of a
computer.

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 INTRODUCTION
• Bus : It is a group of conducting lines that carries
data, address and control signals.
• Busses can be classi ed into data bus, address bus
and control bus.

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 INTRODUCTION
• CPU Bus : Group of conducting lines that are directly
connected to the microprocessor. The signals are
multiplexed ie. More than one signal are passed through
the same line but at di erent timings.
• System Bus : A group of conducting lines that carries data,
address and control signals. Multiplexing is not allowed
here.
• Clock : A clock is a square wave which is used to
synchronize various devices in the microprocessor and in
the system. Every microprocessor requires clock for its
functioning. The time taken by the microprocessor and the
system to execute an instruction or program is measured
only in terms of time period of its clock.
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 Generation of Microprocessor
1st Generation:
• Between the year 1971 to 1973
• Designed using PMOS technology
• They are low cost, slow speed and low output
currents and not compatible with TTL
• 4 bit processors  16 pins
• 8 and 16 bit processors  40 pins
• Due to limitations of pins, signals are multiplexed
• 4 bit processor : INTEL 4004, INTEL 4040
• 8 bit processor : INTEL 8008, National IMP 8
• 16 bit processor : National IMP 16, NATIONAL PACE
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 Generation of Microprocessor
2nd Generation:
• During the year 1973 to 1978
• Designed USING NMOS technology  Faster speed,
Higher density, Compatible with TTL
• E cient 8-bit microprocessors were implemented like
Motorola 6800 and 6801, INTEL-8085 and Zilogs-Z80
• 4 / 8/ 16 bit processors  40 pins
• Ability to address large memory spaces and I/O ports
• Better interrupt handling capabilities
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 Generation of Microprocessor
3rd Generation:
• During the year 1979 to 1980
• 16 bit processors were created and designed using
HMOS (High density MOS) technology.
• INTEL 8086/80186/80286, Motorola 68000 and 68010
were developed.
• Speeds of those processors were four times better
than the 2nd generation processors.
• 16 bit processors  40/ 48/ 64 pins
• Easier and Dynamically relatable programs
• Processor has multiply/ divide arithmetic hardware
• More powerful interrupt handling capabilities
• Flexible I/O port addressing
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 Generation of Microprocessor
4th Generation:
• From 1981 to 1995
• 32 bit microprocessors by using HCMOS (low power
version of HMOS) fabrication.
• INTEL-80386 and Motorola’s 68020/68030 were the
popular processors.
• Physical memory space 224 bytes = 16 Mb
• Virtual memory space 240 bytes = 1 Tb
• Floating point hardware
• Supports increased number of addressing modes
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 Generation of Microprocessor
5th Generation:
• From 1993 to until now
• this generation has been bringing out high-
performance and high-speed processors
that make use of 64-bit processors.
• Such processors include Pentium, Celeron,
Dual and Quad core processors.
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 8085 Microprocessor

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 8085 BUS STRUCTURE

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 8085 BUS STRUCTURE
Address Bus:
• The address bus is a group of 16 lines generally
identi ed as A to A .
0 15
• The address bus is unidirectional. Bits ows in one
direction, from the MPU to peripheral devices.
• The MPU uses the address bus to identify a peripheral or
a memory location.
Data Bus:
• The data bus is a group of eight lines used for data ow.
• These lines are bi-directional - data ow in both
directions between the MPU and memory and
peripheral devices.
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 8085 BUS STRUCTURE
• The MPU uses the data bus to transfer binary
information.
• For accessing IO mapped device, the eight data
lines generate (00 to FF) 2 = 256 IO address.
8

• The largest number that can appear on the data bus is

11111111.
Control Bus:
• The control bus carries synchronization signals and
providing timing signals.
• The MPU generates speci c control signals for every
operation it performs. These signals are used to identify
a device type with which the MPU wants to
communicate.
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 8085 MICROPROCESSOR
Features of 8085 Processor:
• 8-bit microprocessor
• 8-bit data bus and 16-bit address bus
• Memory capacity = 216 = 65,536 = 64KB
• Originally designed using NMOS technology but now
manufactured using HMOS technology.
• Contains approximately 6500 transistors.
• It is a 40 pin DIP (Dual in-line package)
• Requires +5V supply
• The internal clock frequency range is 3.03 MHz and 5
MHz for NMOS 8085A and 8085A-2 respectively. HMOS
8085AH, 8085AH-2, 8085AH-1 is available with 3MHz,
5MHz and 6MHz respectively.
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 8085 - Functional block
diagram

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 8085 MICROPROCESSOR
Arithmetic and Logic Unit (ALU):
• It is used to perform the arithmetic operations
like addition, subtraction, multiplication,
division, increment and decrement and logical
operations like AND, OR and EX-OR.
• It receives the data from accumulator and
registers.
• According to the result it set or reset the ags.

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 8085 MICROPROCESSOR
Registers of 8085:
• The 8085 have six general-purpose registers
to store 8-bit data during program execution.
• These registers are identi ed as B, C, D, E, H,
and L.
• They can be combined as register pairs BC, DE,
and HL to perform some 16-bit operations.

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 8085 MICROPROCESSOR
Accumulator (A):
• The accumulator is an 8-bit register
• This register is used to store 8-bit data and
to perform arithmetic and logical operations.
• The result of an operation is stored in the
accumulator.

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 8085 MICROPROCESSOR
Flags:
• The ALU includes ve ip- ops that are set
or reset according to the result of an
operation.
• They are Zero (Z), Carry (CY), Sign (S), Parity
(P), and Auxiliary Carry (AC) ags.
• The bit position for the ags in ag register
is,
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 8085 MICROPROCESSOR
• Sign Flag (S): After execution of any ALU
operation, if D7 of the result is 1, the sign ag
is set. Otherwise it is reset. If D7 is 1, the
number will be viewed as negative number.
If D7 is 0, the number will be viewed as
positive number.
• Zero Flag (Z): If the result of arithmetic and
logical operation is zero, then zero ag is set.
Otherwise it is reset.
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 8085 MICROPROCESSOR
Auxiliary Carry Flag (AC): If D3 generates any carry
when doing any arithmetic and logical operation,
this ag is set. Otherwise it is reset.
Parity Flag (P): If the result of arithmetic and logical
operation contains even number of 1’s then this
ag will be set and if it is odd number of 1’s it will
be reset.
Carry Flag (CY): If any arithmetic and logical
operation results any carry then carry ag is set,
otherwise it is reset.
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 8085 MICROPROCESSOR
Program Counter (PC):
• This 16-bit register sequencing the execution of
instructions.
• When a opcode is being fetched, the program
counter is incremented by one to point to the
next memory location.
Stack Pointer (SP):
• It is a 16-bit register used as a memory pointer.
• It points to a memory location in R/W memory
de ned by the programmer.
• The beginning of the stack is de ned by loading
a 16-bit
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address in the stack pointer.
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 8085 MICROPROCESSOR
Temporary Register: It is used to hold the data
during the arithmetic and logical operations.
Instruction Register: When an instruction is
fetched from the memory, it is loaded in the
instruction register.
Instruction Decoder: It gets the instruction from the
instruction register and decodes the instruction. It
identi es the instruction to be performed.
Serial I/O Control: It has two control signals named
SID and SOD for serial data transmission.
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 8085 MICROPROCESSOR
Timing and Control unit:
• It provides timing and control signal to the
microprocessor to perform operations.
• Control Signals : READY, , ALE
• Status Signals : S0, S1,
• DMA Signals : HOLD, HLDA
• RESET Signals : , RESET OUT
• Clock Signals : X1, X2, CLK
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 8085 MICROPROCESSOR
• The processor sets the READY signal after
completing the present job to access the data.
• are used to indicate whether the
operation is reading the data from memory or
writing the data into memory respectively.
• ALE (Address Latch Enable) is used to
demultiplex the address and data lines.
• HOLD and HLDA are used for DMA process.
• Reset signals are used to reset the processor.
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 8085 MICROPROCESSOR
• along with S0 and S1 is used to indicate
whether the operation is belongs to the memory or
peripherals.

• Clock signals are used for provide control signal to

synchronize the components of microprocessor and
timing for instruction
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 8085 MICROPROCESSOR
Interrupt Control Unit:
• It controls the interrupts during a process.
• When a microprocessor is executing a main
program and whenever an interrupt occurs, the
microprocessor shifts the control from the main
program to process the incoming request.
• After the request is completed, the control goes
back to the main program.
• There are 5 interrupt signals in 8085
microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
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 PINS AND SIGNALS
OF 8085
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 8085 MICROPROCESSOR
The signals can be grouped as follows
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated
signals
6. Serial I/O ports
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 PINS AND SIGNALS OF 8085
1. Power supply and Clock frequency signals:
• Vcc : + 5 volt power supply
• Vss : Ground
• X1, X2 : Crystal or RC network or LC network
connections to set the frequency of internal clock
generator. The frequency is internally divided by
two. Since the basic operating timing frequency is
3 MHz, a 6 MHz crystal is connected externally.
• CLK : Clock output is used as the
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peripheral and devices interfaced with the
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 PINS AND SIGNALS OF 8085
2. Address Bus:
A8- A15 : It carries the most signi cant 8 bits of the
memory address or the 8 bits of the I/O address.
3. Multiplexed Address / Data Bus:
AD0 - AD7
• These multiplexed set of lines used to carry the
lower order 8 bit address as well as data bus.
• During the opcode fetch operation, in the rst
clock cycle, the lines deliver the lower order
address A0 - A7.
• In the subsequent IO / memory, read / write clock
cycle the lines are used as data bus.
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 PINS AND SIGNALS OF 8085
4. Control and Status signals:
• ALE (Address Latch Enable)- This signal helps to
de-multiplex the address and data bus.
• - This indicates that the selected memory
location or I/O device is to be read and that the
data bus is ready for accepting data from the
memory or I/O device.
• - This indicates that the data on the data
bus is to be written into the selected memory
location or I/O device.
• - This status signal indicates that the read /
write operation relates to whether the memory
or I/O device. It goes high to indicate an I/O
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 PINS AND SIGNALS OF 8085
• The status signals are used to know the type of
current operation of the microprocessor.

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 PINS AND SIGNALS OF 8085
5. Interrupts and Externally initiated operations:
• They are the signals initiated by an external device to
request the microprocessor to do a particular task or
work.
• There are ve hardware interrupts called,

• On receipt of an interrupt, the microprocessor

acknowledges the interrupt by the Interrupt
Acknowledge signal .
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 PINS AND SIGNALS OF 8085
• This signal is used to reset the
microprocessor.
• The program counter inside the
microprocessor is set to zero.
• The buses are tri-stated.
• It indicates CPU is being reset.
• Used to reset all the connected devices
when the microprocessor is reset.
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 PINS AND SIGNALS OF 8085
READY
• Memory and I/O devices will have slower
response compared to microprocessors.
• The processor sets the READY signal
after completing the present job to
access the data.
• The microprocessor enters into WAIT
state while the READY pin is disabled.
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 PINS AND SIGNALS OF 8085
6. Single Bit Serial I/O ports:
SID (input) - Serial input data
line
SOD (output) - Serial output data
line
• These signals are used for serial
communication.
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 INSTRUCTION SET

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 INSTRUCTION FORMAT
• An instruction is a command to the
microprocessor to perform a given task on a
speci ed data.
• Each instruction has two parts:
1. Task to be performed, called the
operation code (opcode),
2. Data to be operated on, called the
operand.
• The operand (or data) can be speci ed in
various ways. ItDr.may
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 INSTRUCTION FORMAT
• 8085 has 74 basic instructions
• 246 total instructions
• De ned by the manufacturer INTEL corporation
• The 8085 instruction set is classi ed into the
following three groups according to word size:
 1-byte instructions
 2-byte instructions
 3-byte instructions

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 INSTRUCTION SET
• The 8085 instruction set can be classi ed
into the following ve functional
headings.
1. Data Transfer Instruction
2. Arithmetic Instructions
3. Logical Instructions
4. Branching Instructions
5. Machine Control Instructions
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 INSTRUCTION SET
1. DATA TRANSFER INSTRUCTIONS :
• Includes the instructions that copies
data between registers or between
memory locations and registers.
• In all data transfer operations the
content of source register is not altered.
• Hence the data transfer is copying
operation.
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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 DATA TRANSFER INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS
2. ARITHMETIC INSTRUCTIONS:
• Includes the instructions, which
performs the addition, subtraction,
increment or decrement operations.
• The ag conditions are altered after
execution of an instruction in this group.

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 ARITHMETIC INSTRUCTIONS

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 LOGICAL INSTRUCTIONS
3. LOGICAL INSTRUCTIONS:
• The instructions which performs the
logical operations like AND, OR,
EXCLUSIVE- OR, complement, compare
and rotate instructions are grouped
under this heading.
• The ag conditions are altered after
execution of an instruction in this group.
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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 LOGICAL INSTRUCTIONS

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 BRANCHING INSTRUCTIONS
4. BRANCHING INSTRUCTIONS:
• The instructions that are used to
transfer the program control from one
memory location to another memory
location are grouped under this
heading.
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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 BRANCHING INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS
5. MACHINE CONTROL INSTRUCTIONS:
• Includes the instructions related to
interrupts and the instruction used to
halt program execution.

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 MACHINE CONTROL
INSTRUCTIONS

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 ADDRESSING
MODES
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 ADDRESSING MODES
• Every instruction of a program has to
operate on a data.
• The method of specifying the data to be
operated by the instruction is called
Addressing.
• The 8085 has the following 5 di erent
types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
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 ADDRESSING MODES
Immediate Addressing:
• In immediate addressing mode, the
data is speci ed in the instruction itself.
• The data will be a part of the program
instruction.
Example:
MVI B, 3EH - Move the data 3EH given in
the instruction to B register.
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 ADDRESSING MODES
Direct Addressing:
• In direct addressing mode, the address of the
data is speci ed in the instruction.
• The data will be in memory.
• In this addressing mode, the program instructions
and data can be stored in di erent memory.
Example:
LDA 1050 - Load the data available in
H

memory location 1050 in to H

accumulator.
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 ADDRESSING MODES
Register Addressing:
• In register addressing mode, the
instruction speci es the name of the
register in which the data is available.
Example:
MOV A, B - Move the content of B
register to A register.
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 ADDRESSING MODES
Register Indirect Addressing:
• In register indirect addressing mode, the
instruction speci es the name of the register
in which the address of the data is available.
• Here the data will be in memory and the
address will be in the register pair.
Eg.
MOV A, M - The memory data addressed by
HL pair is moved to A register.
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 ADDRESSING MODES
Implied Addressing:
• In implied addressing mode, the
instruction itself speci es the data to
be operated.
Example:
CMA - Complement the content of
accumulator.
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 ASSEMBLY
LANGUAGE
PROGRAMMING
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 ASSEMBLY LANGUAGE PROGRAMMING

ASSEMBLER:
• An ASSEMBLER is a program, which is
used to translate assembly language
program to correct binary code for each
instruction.
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 ASSEMBLY LANGUAGE PROGRAMMING
Flow chart:
• It is a graphical representation of the operation ow
of the program.
• It is a graphical form of algorithm.
• Symbols used for ow chart are,

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 ASSEMBLY LANGUAGE PROGRAMMING

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 TIMING DIAGRAM

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 TIMING DIAGRAM
Instruction Cycle:
• The time required to execute an instruction is called
instruction cycle.
Machine Cycle:
• The time required to access the memory or input/
output devices is called machine cycle.

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 TIMING DIAGRAM
MACHINE CYCLES OF 8085:
• The 8085 microprocessor has 5 basic machine cycles.
They are
• Opcode fetch cycle (4T)
• Memory read cycle (3 T)
• Memory write cycle (3 T)
• I/O read cycle (3 T)
• I/O write cycle (3 T)
• When the 8085 processor executes an instruction, it
will execute some of the machine cycles in a speci c
order.
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 TIMING DIAGRAM
• The processor takes a de nite time to execute the
machine cycles. The time taken by the processor to
execute a machine cycle is expressed in T-states.
• One T-state is equal to the time period of the internal
clock signal of the processor.
• The T-state starts at the falling edge of a clock.

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 TIMING DIAGRAM
Opcode fetch machine cycle:
• Each instruction of the processor has one byte opcode.
• The opcodes are stored in memory. So, the processor
executes the opcode fetch machine cycle to fetch the
opcode from memory.
• Hence, every instruction starts with opcode fetch
machine cycle.
• The time taken by the processor to execute the opcode
fetch cycle is 4T.
• In this time, the rst, 3 T-states are used for fetching
the opcode from memory and the remaining T-states
are used for internal
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of EEE,the processor. 133
 TIMING DIAGRAM
• Timing Diagram for Opcode Fetch Machine Cycle

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 TIMING DIAGRAM
Memory Read Machine Cycle:
• The memory read machine cycle is
executed by the processor to read a data
byte from memory.
• The processor takes 3T states to execute
this cycle.
• The instructions which have more than one
byte word size will use the machine cycle
after the opcode fetch machine cycle.
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 TIMING DIAGRAM
• Timing Diagram for Memory Read Machine Cycle

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 TIMING DIAGRAM
Memory Write Machine Cycle:
• The memory write machine cycle is
executed by the processor to write a
data byte in a memory location.
• The processor takes, 3T states to
execute this machine cycle.

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 TIMING DIAGRAM
• Timing Diagram for Memory Write Machine Cycle

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 TIMING DIAGRAM
I/O Read Cycle of:
• The I/O Read cycle is executed by the
processor to read a data byte from I/O port or
from the peripheral, which is I/O, mapped in
the system.
• The processor takes 3T states to execute this
machine cycle.
• The IN instruction uses this machine cycle
during the execution.
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 TIMING DIAGRAM
• Timing Diagram for I/O Read Machine Cycle

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 TIMING DIAGRAM
I/O Write Cycle:
• The I/O write machine cycle is executed
by the processor to write a data byte in
the I/O port or to a peripheral, which is I/
O, mapped in the system.
• The processor takes, 3T states to
execute this machine cycle.
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 TIMING DIAGRAM
Timing Diagram for I/O Write Machine Cycle

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 INTERRUPTS

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 INTERRUPTS
• Interrupt is signals send by an external device to
the processor, to request the processor to perform
a particular task or work.
• Mainly in the microprocessor based system the
interrupts are used for data transfer between the
peripheral and the microprocessor.
• The processor will check the interrupts
always at the 2 T-state of last
nd

machine cycle.
• If there is any interrupt it accept the interrupt and
send the INTA (active low) signal to the peripheral.
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 INTERRUPTS
• The vectored address of particular interrupt is
stored in program counter.
• The processor executes an interrupt service
routine (ISR) addressed in program counter.
• It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
1. Hardware
2. Software
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 INTERRUPTS
Software interrupts:
• The software interrupts are program instructions.
These instructions are inserted at desired
locations in a program.
• The 8085 has eight software interrupts from RST
0 to RST 7. The vector address for these
interrupts can be calculated as follows.
Interrupt number * 8 = Vector address
For RST 5, 5 x 8 = 40 = 28 H

Vector address for interrupt RST 5 is

0028H

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 INTERRUPTS
• The Table shows the vector addresses of all
interrupts.

• The software interrupts of 8085 are vectored

interrupts.
• The software interrupts cannot be masked and
they cannot be disabled.
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 INTERRUPTS
Hardware interrupts:
• An external device initiates the hardware
interrupts and placing an appropriate signal
at the interrupt pin of the processor.
• If the interrupt is accepted then the processor
executes an interrupt service routine.
• The 80S5 has ve hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5
(4) RST 5.5 (5) INTR
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 INTERRUPTS
TRAP :
• This interrupt is a non-maskable interrupt.
• TRAP has the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This
means hat the TRAP must go high and remain high
until it is acknowledged.
• In sudden power failure, it executes a ISR and send
the data from main memory to backup memory.

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 INTERRUPTS
• The signal, which overrides the TRAP, is HOLD
signal. (i.e., If the processor receives HOLD and
TRAP at the same time then HOLD is recognized
rst and then TRAP is recognized).
• There are two ways to clear TRAP interrupt.
• By resetting microprocessor (External signal)
• By giving a high TRAP ACKNOWLEDGE (Internal
signal)

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 INTERRUPTS
RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• Maskable interrupt. It is disabled by,
– DI instruction
– System or processor reset.
– After reorganization of interrupt.
• Enabled by EI instruction.
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 INTERRUPTS
RST 6.5 and 5.5 :
• The RST 6.5 and RST 5.5 both are level triggered. ie.
Input goes to high and stay high until it recognized.
• Maskable interrupt. It is disabled by,
– DI, SIM instruction
– System or processor reset.
– After reorganization of interrupt.
• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5
has the fourth priority.
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 INTERRUPTS
INTR:
• INTR is a maskable interrupt. It is disabled by,
– DI, SIM instruction
– System or processor reset.
– After reorganization of interrupt.
• Enabled by EI instruction.
• Non- vectored interrupt. After receiving INTA (active low)
signal, it has to supply the address of ISR.
• It has lowest priority.
• It is a level sensitive interrupts. ie. Input goes to high
and it is necessary to maintain high state until it
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 INTERRUPTS

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 INTERRUPTS
SIM and RIM for interrupts:
• The 8085 provide additional masking facility for
RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
• The status of these interrupts can be read by
executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5
and RST 5.5 interrupts can be performed by
moving an 8-bit data to accumulator and then
executing SIM instruction.
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 INTERRUPTS
• The format of the 8-bit data to be loaded into
accumulator before execution of SIM instruction
is.

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 INTERRUPTS
• The status of pending interrupts can be read from
accumulator after executing RIM instruction.
• When RIM instruction is executed an 8-bit data is
loaded in accumulator, which can be interpreted as
shown in g.

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 MEMORY
INTERFACING
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 MEMORY INTERFACING
• The memory is made up of
semiconductor material used to store
the programs and data.
• Three types of memory is,
– Process memory
– Primary or main memory
– Secondary memory

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 MEMORY INTERFACING
TYPICAL EPROM AND STATIC RAM:
• A typical semiconductor memory IC will have n
address pins, m data pins (or output pins).
• Having two power supply pins (one for connecting
required supply voltage V and the other for
connecting ground).
• The control signals needed for static RAM are chip
select (chip enable), read control (output enable)
and write control (write enable).
• The control signals needed for read operation in
EPROM are chip select (chip
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 MEMORY INTERFACING

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 MEMORY INTERFACING
DECODER:
• It is used to select the memory chip of
processor during the execution of a program.
• No of IC used for decoder is,
2-4 decoder (74LS139)
3-8 decoder (74LS138)

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 MEMORY INTERFACING

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 MEMORY INTERFACING
Consider a system in which the full memory space 64kb is utilized for EPROM memory.
Interface the EPROM with 8085 processor.
– The memory capacity is 64 Kbytes. i.e
• 2 = 64 x 1000 bytes where n = address lines. So, n =
n

16
• In this system the entire 16 address lines of the processor are connected to address
input pins of memory IC in order to address the internal locations of memory.
• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
• Since the processor is connected to EPROM, the active low RD pin is connected to
active low output enable pin of EPROM.
– The range of address for EPROM is 0000H to FFFFH.

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 MEMORY INTERFACING
• Interfacing 64Kb EPROM with 8085

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 MEMORY INTERFACING
Consider a system in which the available 64kb memory
space is equally divided between EPROM and RAM.
Interface the EPROM and RAM with 8085 processor.
– Implement 32kb memory capacity of EPROM using
single IC 27256.
– 32kb RAM capacity is implemented using single IC 62256.
– The 32kb memory requires 15 address lines and so the
address lines A – A of the processor are connected to 15
address pins of both EPROM and RAM.
0 14

– The unused address line A is used as to chip select. If A

is 1, it select RAM and If A is 0, it select EPROM.
15 15

– Inverter is used for selecting the memory.

15

– The memory used is both Ram and EPROM, so the low

RD and WR pins of processor are connected to low WE
and OE pins of memory respectively.
– The address range of EPROM will be 0000H to 7FFFH
and that of RAM will be 7FFFH to FFFFH.

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 MEMORY INTERFACING
• Interfacing 32Kb EPROM and 32Kb
RAM with 8085

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 MEMORY INTERFACING
Consider a system in which 32kb memory space is
implemented using four numbers of 8kb memory.
Interface the EPROM and RAM with 8085 processor.
• The total memory capacity is 32Kb. So, let two number
of 8kb n memory be EPROM and the remaining two
numbers be RAM.
• Each 8kb memory requires 13 address lines and so the
address lines A0- A12 of the processor are connected to
13 address pins of all the memory.
• The address lines and A13 – A14 can be decoded using a
2-to-4 decoder to generate four chip select signals.
• These four chip select signals can be used to select one
of the four memory IC at any one time.
• The address line A15 is used as enable for decoder.
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The simpli ed schematic
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 MEMORY INTERFACING
• Interfacing 16Kb EPROM and 16Kb RAM
with 8085

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 MEMORY INTERFACING
• The address allotted to each memory IC is shown in
following table.

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 MEMORY INTERFACING
Consider a system in which the 64kb memory space is
implemented using eight numbers of 8kb memory.
Interface the EPROM and RAM with 8085 processor.
• The total memory capacity is 64Kb. So, let 4 numbers of
8Kb EPROM and 4 numbers of 8Kb RAM.
• Each 8kb memory requires 13 address lines. So the
address line A0 – A12 of the processor are connected to
13address pins of all the memory lCs.
• The address lines A13, A14 and A]5 are decoded using a 3-
to-8 coder to generate eight chip select signals. These
eight chip select signals can be used to select one of
the eight memories at any one time.
• The memory interfacing is shown in
Dr. R. Sumathi, Department of EEE,
following gure.
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 MEMORY INTERFACING
• Interfacing 3 no. 8Kb EPROM and 5 no. 8Kb RAM
with 8085

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 MEMORY INTERFACING
• The address allocation for Interfacing 4 no. 8Kb
EPROM and 4 no. 8Kb RAM with 8085 is,

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 MEMORY INTERFACING

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 8086 Microprocessor

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 8086 MICROPROCESSOR
Features of 8086 Processor:
• 16 bit processor
• It consists of 40 pin Dual in line package
• 16 bit data bus
• 20 bit address bus
• More memory addressing capability ( 220 = 1Mb)
• Requires one +5V supply voltage
• Require one clock phase with 33% duty cycle to
provide
internal timings. Range of clock rate is 5 MHz
• More powerful instruction set
• High speed of execution
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 8086 Microprocessor

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 8086 MICROPROCESSOR
• The 8086 processor is divided into two
independent functional units. They are,
1. The bus interface unit (BIU)
2. The Execution Unit (EU)
• These two units are linked using an internal
data bus.
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 8086 MICROPROCESSOR
• The BIU interfaces the 8086 to the outside world.
• The Bus interface unit (BIU) fetches instruction,
reads data from memory and peripherals and writes
data into memory and peripherals.
• It contains segment registers, instruction pointer,
instruction queue and address generation / bus
control circuit to provide functions such as fetching
and queuing of instruction and bus control.

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 8086 MICROPROCESSOR
• BIU contains an adder,
which is used to produce
the 20-bit address. The
bus control logic of the
BIU generates all the
bus control signals such
as read and write
signals for memory and
I/O.
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 8086 MICROPROCESSOR
•The Instruction queue is a First In First Out (FIFO) group of registers in
which up to six bytes of instruction code are projected from memory
ahead of time.
•This is done to speed up program execution by overlapping instruction
fetch with execution. This mechanism is referred to as pipe lining.
•If queue is full, then BIU does not prefetch any instructions.
•While fetching the instruction from memory, the Execution Unit (EU)
interrupts the BIU for memory access, the BIU rst complete fetching and
then services the EU.
•If a subroutine call or Jump instructions are encountered, the BIU will
reset the queue and begin re lling after passing the new instruction to
the EU.

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 8086 MICROPROCESSOR
• It has four, 16 bit segment
registers.
• They are,
1. Code segment (CS) registers,
2. Data segment (DS) registers
3. Stack segment (SS) registers
4. Extra segment (ES) registers
• 8086 processor consists of 1
Mega Byte memory and is
divided into segments of up to
64 Kbytes each.
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 8086 MICROPROCESSOR

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 Bus Interface Unit (BIU)
Code Segment Register (16 bit) :

All program instructions located in main memory is

pointed by the 16 bit CS register.
20-bit physical address is calculated with a o set of 16
bit Instruction pointer content.
The CS contains the start of the current code segment
and IP contains the o set from this address to the next
instruction byte to be fetched.
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 Bus Interface Unit (BIU)
Code Segment Register (16 bit) :
BIU computes the 20-bit physical address by logically
shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
Eg :
If
CS = 456A
IP = 1620
then the 20bit physical address is calculated by
adding the IP with one position shifted value of CS.
20 bit address = 456A0 + 1620 = 46CC0
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 Bus Interface Unit (BIU)
Data Segment Register (16 bit) :
The DS register points to current data segment, i.e.
operands for most instructions are fetched from
this segment.
The 16 bit contents of Source Index (SI) or
Destination Index (DI) are used as o set for
calculating the 20 bit physical address

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 Bus Interface Unit (BIU)
Stack Segment Register (16 bit) :
Points to the current stack.
The 20-bit physical stack address is calculated
from the Stack Segment (SS) and the Stack Pointer
(SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical
stack address is calculated from the Stack
segment (SS) and the Base Pointer (BP).
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 Bus Interface Unit (BIU)
Extra Segment Register (16 bit) :

This register points to the extra segment, which

excess data is stored.
The destination index (DI) is used as o set for
calculating the 20-bit physical address. String
instruction always uses ES and DI to calculate the
20-bit address for the destination.
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 Bus Interface Unit (BIU)
Instruction Pointer (16 bit) :
Always points to the next instruction to be
executed within the currently executing code
segment.
So, this register contains the 16-bit o set address
pointing to the next instruction code within the
64Kb of the code segment area.
Its content is automatically incremented as the
execution of the next instruction takes place.
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 Execution Unit (EU)
• The EU decodes and executes instructions.
• A decoder in the EU translates the instructions.
• It has a 16 bit ALU to perform arithmetic and logic
operations.
• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI &
DI).
• These 16 bit registers are used to store 16 bit / 8 bit
data.
• Each 16 bit register (AX, BX, CX, DX) is combination of
two 8 bit register i.e., AH (higher byte) and AL (lower
byte) combines together
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 Execution Unit (EU)
• AX acts as the 16 bit accumulator in which the
Arithmetic & Logical operation are carried out. AL is the
8-bit accumulator.
• BX is the only general-purpose register, which is used
for addressing 8086 memory.
• CX register is the counter register in which the contents
always be decremented by 1.
• DX is the data register is used to hold excess 16 bit
result while performing multiplication, division, etc.
• SP & BP are point registers, which are used to access
data in stack segment.
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of used
EEE, as o set for SS.
191
 Execution Unit (EU)
• The EU also contains a 16-bit ag register which holds the
status ags typically after an ALU operation.
• The ag register of 8086 microprocessor is,

O – Over ow ag
D – Direction ag
I – Interrupt ag
T - Trap ag
S – Sign ag
Z – Zero ag
AC – Auxiliary carry ag
P – Parity ag
CY – Carry ag
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 Execution Unit (EU)
The ags are divided into two classi cations. They
are,
1. Condition code Flags:
These ags re ect the result of Operations
Performed by ALU. They are,
Over ow ag (O): This ag is set, if an over ow
occurs during the arithmetic operation of two
signed numbers.
Sign ag (S): This ag is set, if an MSB of the
accumulator
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is set after any computation.
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 Execution Unit (EU)
Sign ag (S): This ag is set, if an MSB of the
accumulator is set after any computation.
Zero ag (Z): This ag is set, if the result of any
computation is zero.
Auxiliary carry ag (AC): This ag is set, if there is a carry
from the third bit, during addition or borrow.
Parity ag (P): The ag is set, if the lower byte result
contains even number of 1’s.
Carry ag (CY): This ag is set, if any computation result
contains a carry.
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 Execution Unit (EU)
2. Machine control ags:
Direction Flag: This ag is set, if the string is processed
from higher address towards lower address. Otherwise,
the ag is reset. This is used only in string manipulation
instructions.
Interrupt ag: This ag is set, only when maskable
interrupts are recognized.
Trap ag: When a trap interrupt is received by the
processor, this ag is set, which indicates, the processor
to execute the current instruction and to transfer the
control
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 PINS AND SIGNALS OF 8086

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 PINS AND SIGNALS

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 PINS AND SIGNALS
Common Signals:
1. AD15-AD0:Acts as address lines during rst part of
machine cycle and data lines for remaining part of
machine cycles.
2. A19/ S6- A16/S3 :During the rst part of machine cycle
they are used to hold the upper 4-bits of address.
During remaining part of machine cycles they are used
as status lines. S5 gives the current setting of interrupt
ag IF and S6 always zero.

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 PINS AND SIGNALS
•

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 PINS AND SIGNALS
4. NMI : It is a positive edge triggered non maskable interrupt
request.
5. INTR :It is a level triggered maskable interrupt request.
6. CLK : 8086 requires 5 MHz clock signal from some external
crystal controlled generator to synchronize internal
operations.
7. RESET : It clears PSW, IP, DS, SS, ES and instruction queue. It
sets CS to FFFF. This signal must be high atleast for 4 clock
cycles. If reset signal is removed then 8086 fetch the
instruction from the physical address FFFF0.

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 PINS AND SIGNALS
•

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 PINS AND SIGNALS
•

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 PINS AND SIGNALS
•

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 PINS AND SIGNALS
Signals for maximum mode:
• QS0, QS1 :It indicates the status of the instruction
queue.

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 PINS AND SIGNALS
•

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 PINS AND SIGNALS
•

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 INSTRUCTION SET

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 Data Transfer Instructions
• The data transfer involve two operands – source
and destination
• Source and destination operand should be same
size
• The source can be a register or memory or
immediate data
• The destination can be a register or memory
• Transmitting data from a memory to another
memory is not possible with in a single instruction
(Except PUSH instruction)
• The data transferDr. R.instruction
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 Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Data Transfer Instructions

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 Arithmetic Instructions
• Addition or subtraction of binary, BCD or ASCII
data
• Multiplication or division of signed or unsigned
binary data
• Increment or decrement or comparison binary
data

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 Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV,
CMP…
ADD reg2, reg1 (reg2)  (reg2) + (reg1)
ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)
ADD reg, data (reg)  (reg)+ data
ADD mem, data (mem)  (mem)+data
ADD AL, data8 (AL)  (AL) + data8
ADD AX, data16 (AX)  (AX) +data16

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 Arithmetic Instructions
ADC reg2, reg1 (reg2)  (reg2) + (reg1) + CF
ADC reg2, mem (reg2)  (reg2) + (mem) +CF
ADC mem, reg1 (mem)  (mem) + (reg1) + CF
ADC reg, data (reg)  (reg) + data + CF
ADC mem, data (mem)  (mem) + data + CF
ADC AL, data8 (AL)  (AL) + data8 + CF
ADC AX, data16 (AX)  (AX) + data16 + CF
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 Arithmetic Instructions
SUB reg2, reg1 (reg2)  (reg2) - (reg1)
SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)
SUB reg, data (reg)  (reg) - data
SUB mem, data (mem)  (mem) - data
SUB AL, data8 (AL)  (AL) - data8
SUB AX, data16 (AX)  (AX) - data16

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 Arithmetic Instructions
SBB reg2, reg1 (reg2)  (reg2) - (reg1) - CF
SBB reg2, mem (reg2)  (reg2) - (mem) - CF
SBB mem, reg1 (mem)  (mem) - (reg1)- CF
SBB reg, data (reg)  (reg) – data - CF
SBB mem, data (mem)  (mem) – data - CF
SBB AL, data8 (AL)  (AL) - data8 - CF
SBB AX, data16 (AX)  (AX) - data16 - CF
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 Arithmetic Instructions
For byte : (AX)  (AL) x (reg8)
MUL reg For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AL) x (mem8)
MUL mem For word : (DX)(AX)  (AX) x
(mem16)
For byte : (AX)  (AL) x (reg8)
IMUL reg For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AX) x (mem8)
IMUL mem For word : (DX)(AX)  (AX) x
(mem16)
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 Arithmetic Instructions
For 16-bit :- 8-bit :
(AL)  (AX) ∕ (reg8) Quotient
(AH)  (AX) MOD (reg8) Remainder
DIV reg For 32-bit :- 16-bit :
(AX)  (DX)(AX) / (reg16) Quotient
(DX)  (DX)(AX) MOD (reg16) Remainder
For 16-bit :- 8-bit :
(AL)  (AX) / (mem8) Quotient
(AH)  (AX) MOD (mem8) Remainder
DIV mem For 32-bit :- 16-bit :
(AX)  (DX)(AX) / (mem16) Quotient
(DX)  (DX)(AX) MOD (mem16) Remainder
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 Arithmetic Instructions
For 16-bit :- 8-bit :
(AL)  (AX) / (reg8) Quotient
(AH)  (AX) MOD (reg8) Remainder
IDIV reg
For 32-bit :- 16-bit :
(AX)  (DX)(AX) / (reg16) Quotient
(DX)  (DX)(AX) MOD (reg16) Remainder
For 16-bit :- 8-bit :
(AL)  (AX) / (mem8) Quotient
(AH)  (AX) MOD (mem8) Remainder
IDIV mem
For 32-bit :- 16-bit :
(AX)  (DX)(AX) / (mem16) Quotient
(DX)  (DX)(AX) MOD (mem16) Remainder
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 Arithmetic Instructions

DAA

AAA

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 Arithmetic Instructions

AAS

DAS

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 Arithmetic Instructions

AAM
After multiplication

AAD
Before division

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 Arithmetic Instructions

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 Arithmetic Instructions

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 Arithmetic Instructions

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 Arithmetic Instructions

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 Arithmetic Instructions

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 Arithmetic Instructions

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 Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 Logical Instructions

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 String Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

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 String Instructions

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 String Instructions

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 String Instructions

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 String Instructions

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 String Instructions

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 String Instructions

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 Control Transfer Instructions
Mnemonics: CALL, RET

(Near call-
within the
segment)

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 Control Transfer Instructions
Mnemonics: CALL, RET

(Far call-
another segment)

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 Control Transfer Instructions
Mnemonics: CALL, RET

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 Control Transfer Instructions
Mnemonics: CALL, RET

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 Control Transfer Instructions
Mnemonics: JMP (unconditional jump)

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 Control Transfer Instructions
Mnemonics: JMP (unconditional jump)

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 Control Transfer Instructions
Mnemonics: JE, JL, JLE… (conditional jump)

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 Control Transfer Instructions
Mnemonics: JE, JL, JLE… (conditional jump)

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 Control Transfer Instructions
Mnemonics: JE, JL, JLE… (conditional jump)

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 Control Transfer Instructions
Mnemonics: JE, JL, JLE… (conditional jump)

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 Control Transfer Instructions
Mnemonics: LOOP

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 Control Transfer Instructions
Mnemonics: INT (Software interrupts)

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 Control Transfer Instructions
Mnemonics: INT (Software interrupts)

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 Control Transfer Instructions
Mnemonics: INT (Software interrupts)

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 Control Transfer Instructions
Mnemonics: INT (Software interrupts)

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 Process Control Instructions
CLC CF ← 0
CMC CF ← ~ CF
STC CF ← 1
CLD DF ← 0
STD D←1
CLI IF ← 0
STI IF ← 1
HLT Halt program execution
WAIT Wait for TEST line active
LOCK Masters cannot take the system bus
NOP No operation is performed for 3 clock
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 ADDRESSING MODES

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1. Register addressing mode
2. Immediate addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Based addressing mode
6. Indexed addressing mode
7. Based indexed addressing mode
8. String addressing mode
9. Direct I/O port addressing mode
10. Indirect I/O port addressing mode
11. Relative addressing mode
12. Implied addressing mode
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 ADDRESSING MODES
Register addressing mode :
The registers, which is having the data to be
operated is speci ed in the instruction.
MOV CL, BL : [CL] [BL]
MOV BX, CX : [BX] [CX]

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 ADDRESSING MODES
Immediate addressing mode :
An 8 bit or 16 bit data is speci ed in the
instruction.
MOV CL, 07H : [CL] 07H
MOV BX, 1234H : [BX] 1234H

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 ADDRESSING MODES
Direct addressing mode :
An E ective Address (EA), which is the o set (an
unsigned 16 bit data or signed 8 bit data) from the
data segment register, is directly speci ed in the
instruction.

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 ADDRESSING MODES
Register Indirect addressing mode :
• E ective Address (EA), which is the o set (an
unsigned 16 bit data or signed 8 bit data) from the
data segment register, is indirectly speci ed in the
instruction.
• The registers used to hold the e ective address are
BX, SI and DI.
.

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 ADDRESSING MODES
Based addressing mode :
• In this addressing mode the BX or BP register is
used to hold the base value for EA and an
unsigned 16 bit data or signed 8 bit displacement
will be speci ed in the instruction.
.

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 ADDRESSING MODES
Indexed addressing mode :
• In this addressing mode the SI or DI register is used
to hold the base value for EA and an unsigned 16
bit data or signed 8 bit displacement will be
speci ed in the instruction.
.

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 ADDRESSING MODES
Based Indexed addressing mode :
• In this addressing mode,
 SI or DI register is used to hold the index value
for EA
 BX or BP register is used to hold the base value
for EA
 and an unsigned 16 bit data or signed 8 bit
displacement
will be speci ed in the instruction.

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 ADDRESSING MODES
String addressing mode :
• In this addressing mode the EA for source is stored
in SI register and EA for destination is stored in DI
register.

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 ADDRESSING MODES
Direct I/O port addressing mode :
• The address of port is directly given in instruction
itself.

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 ADDRESSING MODES
Indirect I/O port addressing mode :
• The address of port is indirectly given in instruction
itself.

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 ADDRESSING MODES
Relative addressing mode :
• The e ective address of a program instruction is
speci ed relative to IP by an 8 bit signed
displacement.

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 ADDRESSING MODES
Implied addressing mode :
• The instruction itself is having the data to be
operated.

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 ARM PROCESSOR
(Advanced RISC
Machine)
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 FEATURES
• RISC (Reduced Instruction set)
• High performance, low power and small size
• load/store architecture
• Pipelining
• Uniform and xed length instructions
• ALU and Shifter control
• Multiple load/store register instructions
• Coprocessor instruction interface
• THUMB support (16-bit dense compressed instruction
set)
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 FEATURES
Data Sizes and Instruction Sets:
• The ARM is a 32 bit architecture.
• Terms of ARM are,
 Byte means 8 bits
 Half word means 16 bits (two bytes)
 Word means 32 bits (four bytes)
• Most ARM’s implement two instruction sets
 32 bit ARM Instruction Set
 16 bit Thumb Instruction Set
 Java byte code (Jazelle cores)
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 ARCHITECTURE
Core Architecture:
Von Neumann Harvard
Instructions and data are Data and instructions are
stored in the same memory. stored into
separate memories.
Simple and inexpensive Faster and More energy
e cient

Access to data or instruction, Di erent bus sizes

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 PIPELINING ARCHITECTURE
Usually ARM instructions are executed in 3 stages :
1. Fetch : fetch instruction from memory to pipeline
2. Decode : decode the instruction to ARM
3. Execute : ALU result written to destination
registers

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 PROCEESOR MODE

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 ARM Registers
• ARM has 37 registers, each 32-bit long
30 – General purpose
5 – SPSR (saved process status register)
1 – CPSR (current process
status register)
1 – PC (program counter)

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 ARM Registers

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 ARM Registers
• It has 16 data registers are accessible at any time to the
programmer as r0 to r15.
• Registers r0-r13 are general-purpose registers used to
hold either data or address values.
• Register r14 is used as the subroutine Link Register (LR).
Register r14 receives the return address when a Branch
with Link (BL or BLX) instruction is executed
• Register r15 holds the Program Counter. PC contains the
address of the instruction being executed at the current
time. As each instruction gets fetched, the program
counter increments by 4 bytes in ARM state and 2 bytes
in THUMB state.
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 ARM Registers
• The processor contains one CPSR (current program
status register), and ve SPSR (saved program status
registers) for exception handlers to use. The program
status registers:
 hold information about the most recently performed
ALU operation
 control the enabling and disabling of interrupts
 set the processor operating mode
• 20 registers are hidden from a program at di erent
times. These registers are called banked registers. They
are available only when the processor is in a particular
mode
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 ARCHITECTURE
• Fig. shows, an ARM core as
functional units connected by
data buses.
• Data enters the processor
core through the Data bus.
The data may be an
instruction to execute or a
data item.
• It is a Von Neumann
implementation of the ARM.
Data items and instructions
share the same bus.
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 ARCHITECTURE
• The instruction decoder translates instructions before
they are executed.
• Data items are placed in the register le—a storage bank
made up of 32-bit registers.
• Since the ARM core is a 32-bit processor, most instructions
treat the registers as holding signed or unsigned 32-bit
values. The sign extend hardware converts signed 8-bit
and 16-bit numbers to 32-bit values as they are read from
memory and placed in a register.
• ARM instructions typically have two source registers, Rn
and Rm, and a single result or destination register, Rd.
• Source operands are read from the register le using the
internal buses A andDR.B,R.respectively.
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 ARCHITECTURE
• The ALU (arithmetic logic unit) or MAC (multiply-
accumulate unit) takes the register values Rn and Rm
from the A and B buses and computes a result.
• Data processing instructions write the result in Rd
directly to the register le.
• Load and store instructions use the ALU to generate
an address to be held in the address register and
broadcast on the Address bus.
• One important feature of the ARM is that register Rm
alternatively can be shift/rotate by any number of bits
in the barrel shifter before it enters the ALU.
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 ARCHITECTURE
• Together the barrel shifter and ALU can calculate a
wide range of expressions and addresses.
• After passing through the functional units, the
result in Rd is written back to the register le using
the Result bus.
• For load and store instructions the incremented
updates the address register before the core reads
or writes the next register value from or to the next
sequential memory location.
• The processor continues executing instructions
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EEE the normal297
 ARM Exceptions
• ARM supports ve types of exceptions, and a
privileged processing mode for each type
1. Fast interrupt
2. Normal interrupt
3. Memory abort - Used to implement memory
protect or virtual memory
4. Attempted execution of an unde ned
instruction
5. Software interrupt (SWI) instruction - Make a
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 ARM Exceptions
• ARM handles exceptions by making use of the banked
registers to save state.
• The old PC and CPSR contents are copied into the
appropriate R14 and SPSR and the PC and mode bits in
the CPSR bits are forced to a value that depends on the
exception.
• When an exception occurs
 Some of the standard registers are replaced with
registers speci c to the exception mode
 The ARM processor halts execution after the current
instructions
 Then begin execution at a xed memory address,
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 ARM Instruction Set
• The ARM instruction set can be divided into six
classes
1. Branch instructions
2. Data-processing instructions
3. Status register transfer instructions
4. Load and store instructions
5. Coprocessor instructions
6. Exception-generating exceptions
• Software interrupt instructions (SWI)
• Software breakpoint
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 THANK YOU
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