Digital Design and Computer Organization

Course code BCS302

MODULE-3
Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure,
Performance – Processor Clock, Basic Performance Equation, Clock Rate, Performance
Measurement.
Machine Instructions and Programs: Memory Location and Addresses, Memory Operations,
Instruction and Instruction sequencing, Addressing Modes.
Text book Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5th Edition,
Tata McGraw Hill. : 1.2, 1.3, 1.4, 1.6, 2.2, 2.3, 2.4, 2.5

3 BASIC STRUCTURE OF COMPUTERS

3.1 Functional Units

A computer consists of five functionally independent main parts as shown in fig 3.1
i. input,
ii. memory,
iii. arithmetic logic,
iv. output,
v. control units:

Figure 3.1 Basic functions units of Computers

Input unit accepts user inputs via say keyboard and the information is stored in memory. The
arithmetic and logic unit operates on the input data and the result is forwarded to output unit. The
control unit manages all these units.
Data/ Information handled by a computer can be categorized as:
Instructions or machine instructions
• These govern the transfer of information with a computer and between a computer and its
I/O device.
• It also specifies the arithmetic and logic operations to be performed.
• Set of such instructions is called a program and is stored in memory. A processor fetches
these instructions and executes them one after another.

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Data
• Number and encoded characters used as operands by the instructions.
• Source program (high level program ex program or object program (machine language
program can also be treated as data)
Encoding of data
• Data handled by a computer is encoded as a series of 0’s and 1’s called bits.
• Numbers can be represented encoded binary coded decimal (BCD)
• Alphanumeric characters can be coded using ASCII(American standard code for
Information Interchange) or EBCDIC (Extended Binary Coded Decimal Interchange Code).
• In ASCII 7-bits are used to code alphanumeric characters and EBCDIC, 8 bits are used.
3.1.1 Input Unit
Keyboard is one of the input units. When a key is pressed on keyboard a corresponding binary code
is transmitted over a cable to the memory/processor. Ex:: joysticks, trackball mouse, microphones,
camera.
3.1.2 Memory Unit
Memory stores “programs” and “Data”.There are two types of memory
i. Primary Memory
ii. Secondary Memory
Primary Memory
It is a fast memory where programs are stored when they are being executed. It is made of large
number of storage cells where each cell stores one bit. The memory is organized into chunks of m
bits called words. Data is read /written from memory in terms of words. Each memory location is
associated with an address. This needs to be specified while doing a read/write operation. The length
of word determines the type of machine. The length could be 16 bits, 32 bits or 64 bits etc.

The primary memory is also called random access memory(RAM). The time required to
access one word is called memory access time. This memory access time ranges from few
nanoseconds(ns) to 100ns.

Hierarchy of RAM
• Cache: small and fast RAM units. These are highly coupled to processors and are part of
the same processor chip.
• Main Memory: This is largest and slowest unit.
Secondary Storage
Primary storage is expensive hence large amount of data and programs are stored in nonvolatile
memory called secondary storage. For example: magnetic disks,tapes, optical disks(CD-ROMs)
3.1.3 Arithmetic and Logic Unit
Most computer operations are executed in arithmetic and logic unit (ALU). Operations like
addition, subtraction, multiplication, division, comparison of numbers etc. are performed in ALU.
To perform these operations, the operands are placed in high speed storage elements called registers
and output could be stored in memory/register.

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3.1.4 Output Unit:
Output unit sends processed results to outside world. The speed of output devices is slower
compared to processor speeds. Ex: printers, monitors
3.1.5 Control Unit
Memory, ALU and I/O devices are controlled and coordinated by control unit by sending timing
signals. Control unit coordinates the operations. It is generally not a single unit but it is distributed
throughout the machine.
Note:
• The computer accepts information in the form of programs and data through an input unit
and stores it in memory.
• Information stored in memory is fetched under program control into an arithmetic and logic
unit, where it is processed.
• Processed information leaves the computer through an output unit.
• All activities inside the machine are directed by control unit.
3.2 Basic Operational Concepts
A computer performs task by executing instruction from memory. These are moved from memory
to processor. For example:
Add LOCA, R0
In the above instruction contents of memory location “LOCA” are added to that of R0 once the sum
is stored in Register R0.
The above instruction is generally done in two steps.
i. Load LOCA,R1
ii. Add R1,R0
So, the contents of memory LOCA are stored in R1, subsequently contents of R1 are added to R0.
The figure 3.2 below shows the connections between memory and processor.

Figure 3.2 Connection between processor and memory

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Other than control unit and ALU, processor contains some special registers.
• Instruction Register (IR): This register holds the current instruction being executed. The
output of IR is available to control unit to generate control information.
• Program Counter (PC): This register contains address of next instruction to be executed
when current instruction is being executed. PC moves to the next instruction that shall be
executed.
• General purpose registers. Registers R0 to Rn-1 are general purpose registers which are
used during computation/program execution. For example,
Add R1, R0
Move LOC, R1
• Memory Address Register (MAR): It holds the address of an operand/location that needs
to be accessed. For example:
Move LOC, R1

When above instruction is being executed, the value needs to be fetched from memory. So
address of “LOC” is stored in MAR so that value from this location can be read and put into register
R1.

• Memory Data Register (MDR): It holds the data to be written to/read from memory.
For example:
Move R1, LOC
The contents of R1 need to be moved to LOC memory location. So, R1 register contents are first
moved to MDR then the address of LOC is moved to MAR and the move instruction is executed
so that value stored in MDR is written to “LOC” memory location.
Let’s look in details the operation steps:
Step 1: The first line of code needs to be executed, so the address where the line of code resides is
placed in MAR.
Step 2: Read control signal is issued a line of code (ex: Move LOC, R1) is copied into MDR.
Step 3: The contents of MDR are moved to IR. So, by Step3 the instruction that needs to be
executed has been fetched and stored in IR, now this instruction needs to be executed.
Let “Add LOC, R1” be the instruction. Let’s see how this is executed.
Step 4: If the instruction involves memory access, the address of operand (ex: address of LOC) is
stored in MAR.
Step 5: Then read signal is issued and the contents of memory (i.e. value stored in LOC) are copied
to MDR.
Step 6: The value in MDR is passed to ALU to perform the operation (Add in the above example)
Step 7: If the result needs to be stored back in memory then the output is put back in MDR and
the location of memory is placed in MAR and “write” signal is executed to write back the
result to memory.
Interrupt:
There are scenarios when normal execution needs to be interrupted to handle situation that needs
immediate attention. In such a scenario an interrupt signal is generated and an appropriate routine
called interrupt service routine is executed.

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Since an interrupt, interrupts normal execution of a program, the current values of PC,
registers and control information(flags) are backed up/ saved before executing an interrupt service
routine (ISR). When the ISR execution is over the values of PC, registers and control information
are restored.

3.3 Bus Structures

All the units (I/O, Processor, memory) are connected to each other by many parallel wires/lines
called bus. These lines carry
• Data
• Address (of say memory location)
• Control information(read/write)
• Single bus architecture
Single Bus Architecture

Figure 3.3 Single bus structure

In single bus architecture all devices are connected to a single bus. So, at any point only two
units/devices can communicate with each other as shown in figure 3.3.

Each device operates at its own speed. Electromechanical devices like keyboard, printer
operate at low speeds compared to magnetic and optical disks. Optical disks and magnetic disks are
slower compared to memory and processor speeds.

However, all these operate over common bus. Hence a control/synchronization mechanism
is required to coordinate these devices that operate at varying speeds.

Generally, buffers are used to manage the devices operating at different speeds. Ex: when
the processor needs to print a character on printer, first the character is placed in printer buffer. This
frees up the bus and processor to perform its operation. The printer reads the character from the
buffer and prints it.

3.4 Performance
The performance of a computer is how quickly it can execute programs. The speed with which a
computer executes programs is affected by the design of its hardware and machine language
instructions.

The total time required to execute the program is called elapsed time. This measure the
performance of the entire computer system. ( i.e speed of processor, disk and printer).

Performance of processor only the periods during which the processor is active. The sum of these
periods as the processor time needed to execute the program. This processor time depends on the
hardware that is involved in execution of machine instructions. The pertinent/relevant parts is
included the cache memory as a part of processor unit which impact the processor time are shown
in fig 3.4.

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Figure 3.4 The processor cache

As execution proceeds, instruction are fetched one by one over the bus into processor, and
a copy is placed in the cache. When execution of an instruction calls for data located in the main
memory, the data are fetched and copy is placed in the cache. Later , if the same instruction or
data item is needed a second time, it is read directly from the cache.

Hence, “cache memory” speeds up the program execution. Since it is within the processor,
access time to cache is much less compared to memory (main memory) access.

3.4.1 Processor Clocks

Processor circuits are controlled by a timing signal called a clock. A clock defines a regular time
interval called clock cycle. A machine instruction(ex: Move Loc,R1) is divided into many basic
steps and each step is executed within a clock cycle, such that each step can be completed in one
clock cyle.

The length/duration of clock cycle plays a very important role and impacts the processor
performance.
1
Inverse of clock cycle is clock rate(R): 𝑅 = . Clock rate is measured in cycles per second.
𝑃

In new processors the clock rate ranges from few hundred million cycles per second i.e. Hertz(Hz).
For example:
500 million cycles per second =500 MHz
1250 million cycles per second = 1.2GHz
Clock period for above two are 2 and 0.8 nanoseconds (ns)
3.4.2 Basic Performance Equation
Let
T = Processor time required to execute the complete program written in high level language.
N= Number of machine instructions executed to complete the execution of the program
S= Average number of basic steps needed to execute one machine instruction.
R=Clock Rate R cycles per second. The progam execution time
𝑵×𝑺
Hence, 𝑻 = 𝑹

This is basic performance equation.

To achieve high performance, the computer designer must seek ways to reduce the value T, which
means reducing N & S and increasing R.

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3.4.3 Clock Rate: (R)
Clock rate can be increased in two ways
i. Improve the Integrated Technology(IC) to make logic circuits faster and hence time needed
to execute basic step is reduced.
ii. Reduce the amount of processing done in one basic step which in turn results in increase in
clock rate(R) and a reduction in P (where P is the length of one clock cycle).
3.4.4 Performance Measurement
In order to compare computer architectures and measure performance certain benchmarks are used.
To make comparisons possible, standardized programs must be used.

A nonprofit organization called System Performance Evaluation Corporation (SPEC)

selects and publishes representative application programs for different application domains,
together with test results for many commercial available computers.

The programs range from Game Playing, Compilers, Database Applications, Numerically
Intensive Programs(example: astrophysics, quantum chemistry)

The program is compiled on target devices and tested. The results are compared with
reference device(ex:SPEC95 uses SUN SPARC station 10/40; For SPEC2000 uses ULTRA
SPARC 10 workstation with 300 MHz ULTRA SPARC- III Processor)

The SPEC rating is computed as:

𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑛 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟
𝑆𝑃𝐸𝐶 𝑟𝑎𝑡𝑖𝑛𝑔 =
𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑛 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 𝑢𝑛𝑑𝑒𝑟 𝑡𝑒𝑠𝑡

So a value of 50 on spec rating indicates test device is 50 times faster than the reference device.

The tests are done for all programs (ex: gaming, database, numerically intensive programs
etc.) and final rating is arrived as
𝑛
1
𝑆𝑃𝐸𝐶 𝑟𝑎𝑡𝑖𝑛𝑔 = (∏ 𝑆𝑃𝐸𝐶𝑖 )𝑛
𝑖=1

Where “n” is the number of programs run.

A SPEC rating is a measure of the combined effect of all factors affecting performance
including compiler, operating system, the processor and the memory of the computer being tested.

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M 3.2: Machine Instructions and Programs

3.5 Memory Locations and Addresses
Instruction, number and characters are stored in the memory of a computer. The memory consists
of many millions of storage cells, each can store a bit of information having value 0 or 1.

Dealing with each cell is a tough job and unnecessary. For this purpose, the memory is
organized so that group of n bits can be stored and retrieved in single basic operation.

Each group of n bits is referred to as word of information and n is called world length. The
memory of computer can be schematically represented as a collection of words as shown in figure
3.5.

Figure 3.5 Memory words

Modern computers are machines which are called 16-bit, 32-bit or 64-bit machines. A 32-
bit machine operates on words which are 32bits long. So, a single word stores 32-bit 2’s
complement number as shown in fig 3.6(a) or 4 ASCII characters each occupying 8 bits as shown
in fig 3.6(b). A unit of 8-bits is usually called byte. Machine instructions may require one or more
words for their representation.

(a)

(b)
Figure 3.6 Examples of encoded information in a 32-bit word
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Accessing the memory to store or retrieve a single item of information either a word or a
byte, requires distinct name or addresses for each item location. The 2k address constitute the
address space of the compute and the memory can have upto 2k addressable location.

Ex : 4 bit address has 24 locations 0-15, So 16 words can be stored.

10 bit address has 1024words or 1k locations
20 bit address has 1MB
32 bit address line has 4 GB
3.5.1 Byte Addressability
There are 3- terms we have come across till now
i. Bit
ii. Byte – 8 bits make a byte
iii. Word – multiple bytes make up a word (ex: 32-bit word has 4 bytes)

So, we can address a memory at bit level, or byte level or word level. The most practical
way of assigning is to refer to memory as successive bytes’ location. This way of addressing
memory in terms of bytes is called Byte-Addressable Memory.

Byte locations have address 0,1,2,3….. Since a word is a set of multiple bytes, in a 32-bit
machine a word address will be 0,4, 8...

3.5.2 Big-Endian AND Little-Endian Assignment

This word can be stored in two ways in memory, namely
i. Big Endian
ii. Little Endian
Big- Endian
In this system the lower byte of memory stores the higher order byte (i.e. byte 0). We can visualize
it as shown in fig 3.7(a)
Little Endian
In this system, the lower byte of memory stores the lower order byte(byte 3). We can visualize it as
shown in fig 3.7(b)
In both the cases, byte addresses 0,4,8,… are taken as the addresses of successive words in the
memory and are the addresses used when specify memory read and write operations for words.

(a) Big endian assignment (b) Little endian assignment

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Figure 3.7 Byte and word addressing

Example : Consider a 32-bit integer (in hex): 0x 12345678.
Big endian :
Word address – 0 12 34 56 78
Litten endian
Word address – 0 78 56 34 12
3.5.3 Word Alignment
If a word is 32-bit long and if the word boundaries occur at address 0, 4, 8, 12… etc. then we say
that the words have aligned address
Ex: word1→ 0-3 bytes, word 2 → 4-7 bytes, word 3→ 8-11 bytes.
Unaligned address: However, if a word (say, a 32-bit word) does not align at word boundaries 0,
4, 8, etc., then such words are called unaligned words.
Ex: word 1→ 2-5 bytes, word 2 → 6-9 bytes etc.
3.5.4 Accessing Numbers, Characters and Character Strings
Numbers: A number can occupy one word of memory. It can be accessed (read/write) using the
address of the word.
Character: A character occupies one byte of memory. We can access a character by specifying the
byte address of the character.
Character String: A character string is a sequence of characters. The beginning of the string is
indicated by giving the address of beginning character. The ending of the string is indicated by 2
ways:
i. add a special character ex: “\0” to indicate the character string ends
ii. store the length of the string along with the string to indicate the length of character string.
3.6 Memory Operations
Both program instructions and data operands are stored in the memory.
• To execute an instruction, the processor control circuits must transfer the word (or words)
from memory to the processor.
• Operands and results must also be moved between the memory to the processor.
Two basic operations involving memory are needed:
i. Load ( or Read or Fetch) : Load operation transfers a copy of the contents of a specific
memory location to the processor. The contents of memory do not change (only a copy
of it is transferred to processor). To perform the load operation, the processor sends the
memory address and the data to be readfrom the memory.
• Store ( or write) : Store operation transfers an item of information from the processor
to a specific memory location. The previous content of that memory location is over
written. To perform the store operation, the processor sends the memory address and the
data to be written to the memory.
Note:
i. An information item that is transferred between a memory location & a processor could
be either a word or a byte.

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ii. A processor contains registers with each register size equal to the length of the word.
Hence, when a load or store operation is done, content of these registers are operated
upon.
3.7 Instructions and Instruction Sequencing:
A computer generally performs four types of operations:
i. Transfer data between the Memory &Processor registers
ii. Arithmetic and Logic operations on data.
iii. Program Sequence & Control
iv. I/O transfers
To understand these, we first define some notations:
3.7.1 Register Transfer Notation (RTN)
Data could be transferred between memory location, processor register & special registers in
memory system.
• A memory location could be identified by a symbolic name like LOC and a register could
be identified by names like R0, R5.
• I/O register may be identified by names like DATAIN, OUTSTATUS.
• Ex: R1 [LOC], this expression means the content of location “LOC” is copied to R1.
• Ex: R3  [R1] + [R2], this expression means add the contents of R1 register and contents
of R2 register and store it in R3.
• [R1] means value stored in register R1.
3.7.2 Assembly language Notation
• To represent the machine instructions, we use another notation called “assembly language”.
• Generally, a “C” program is first converted to assembly language
RTN Assembly Language
R1 [LOC] Move LOC, R1
R3 [R1] + [R2] Add R1, R2,R3
3.7.3 Basic Instruction Type:
There are four types of instructions
i. Three address instruction
ii. Two address instruction
iii. One address instruction
iv. Zero address instruction

i. Three Address Instruction

Operation operand1, operand2, operand 3
Ex : Operation source1, source2, destination
In ‘C’ program
C = A + B, (we are trying to add the contents of A & B & store it in C).

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This can be represented in RTN as

C  [A] + [B].
The corresponding assembly language instruction is
Add A, B ,C.
where A & B are “source operands” and ‘C’ is the destination operand.
If k-bits are required to specify an address and p-bits for operation, then the length of the instruction
would be represented as:
Operation Source1, Source 2, destination
 p bits →  k bits →  k bits →  k bits →
Note : 3 address instruction is too large to fit in one word for a reasonable word length.
ii. Two Address Instruction
Operation operand1, operand2
Ex: Operation source, destination
A three address operation like Add A,B,C can be represented in multiple two address instructions
as below:
Assembly Instruction Operation operand1 RTN
Add A, B B  [A] + [B]
Move B, C C  [B]
iii. One Address Instruction
Operation operand
In a one address instruction, only one operand is specified.
Ex: Load A
In case of one address instruction, the other operand is a standard register called “Accumulator
register”. So, when we execute “Load A”, then the content of memory location “A” is loaded to
the accumulator register.

We can do the 3-instruction operation. Add A, B, C using multiple one Address instruction
as below:

RTN Description
Load A Raccum[A] Copy A’s data to accumulator register
Add B Raccum[Raccum] + [B] Add B’s data to
accumulator register& store it in register
Store C C[Raccum] accumulator register content is stored

In case of one address instruction, based on the operation being done, a memory location could be
a source location or destination location. For example:
Load A : A is a source location
Store C : C is a destination location

Some CPUs/Processors have the luxury of many registers. These registers (R1, R2, …. Rn)
are closest to the processor, so if an operation involves registers it will be very fast.
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Ex: Add Ri,Rj Rj [Ri] + [Rj] Will execute very fast because all operands are registers.

Instruction to transfer content is of two types “Move” & “Load”. If one of the operands is a
register, then it’s better to use “Move” rather than “Load”

In some processors operations can be performed only on registers. In such processor the
content from memory is first moved to registers. Before performing the operation.

Ex: If we want to do C <= A + B with only registers it is done as:

Move A, Ri Ri [A]
Move B, Rj Rj [B]
Add Ri, Rj Rj[Ri] + [Rj]
Move Rj, C C  [Rj]
In some processors if the flexibility is there to have one memory location as an operand
and other one is register
Ex: the C<-A + B can be represented as:
Move A,Ri Ri [A]
Add B,Ri Ri [B] + [Ri]
Move Ri,C C [Ri]
iv. Zero Address Instructions
Some CPU’s store the operands on a special structure called push down stack. In this case, zero
address instructions are possible.
3.7.4 Instruction Execution and Straight Line Sequencing:
In this section, we will see the following:
• How instruction execution happens using Program Counter (PC) and Instruction register
(IR).
• Meaning of straight line sequencing.
In the previous section, we saw how C  [A] + [B], was written as
Move A, R0
Add B, R0
Move R0, C
These instructions are stored in the RAM before they are executed on the processor as shown fig3.8.

Figure 3.8 A program for C  [A] + [B]

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In the above representation, we can note the following:

• Program that does the addition is stored in 3 contiguous word locations, named as program
segment.
• The program uses memory locations A, B and C, which are again stored in the Data part of
the program.
• Each instruction is assumed to occupy one word of 32 bits (that’s why the instruction starts
at i, i+4 & i+8).
• There is a special register called as “Program Counter (PC)”. It points to the instruction
being executed. So, when the program starts executing PC points to address i, i.e. the value
stored in PC register is address i.
• The execution of this program happens in two phases:
Phase 1: Instruction Fetch
The Program Counter (PC) points to the instruction to execute. The processor picks the content
located or pointed to by PC (i.e. Move A, R0) and dumps it into another special register called
“Instruction Register (IR)”. This phase is called Instruction Fetch.
Phase 2: Instruction Execute
In this phase, the operation to be performed is identified (Move, Add etc.). The required operands
are fetched (Ex: value from memory location A). Then, the operation is executed and finally the
result is stored (ex: Add B,R0).
Note:
• All these steps are for one operand like Add B, R0. When phase 2 is going on PC moves to
the next word (i.e. say from “i” to “i+4”). So by the time phase 2 is done, PC would have
moved to next instruction and phase 1 & phase 2 are repeated for the next instruction.
• This method of executing one instruction after another from start to finish is called straight
line sequence.
3.7.5 Branching
Let us assume that we need to add “n” numbers NUM1 to NUMn and store the result in a variable
SUM, the code and corresponding data can be written as shown below:

Figure 3.9 A Straight-line program for Figure 3.10 Using a loop to add n number
adding n numbers

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Instead of doing it in straight line fashion, it can also be done as:

• The variable N stores the number of times SUM operation needs to be performed (i.e. n)
• Register “R0” stores the intermediate sum as it keeps getting added. Final result is stored in
SUM as shown in figure 3.9.
• The looping block is shown in figure 3.10 by the brace “{“. In the looping block the next
“NUM” is fetched from memory & added to Register “R0”. The variable R1 is then
decremented by 1.
• A special instruction is executed called “Branch >0 Loop”, what this instruction means is
that, if the result of the instruction above it (i.e. Decrement R1) resulted in a value in the
register greater than zero then go back to “Loop”, else go to next instruction, i.e. “Move
R0, SUM”.
• Execution of the loop is repeated as long as the result of the decrement operation is greater
than zero.
• So, this special instruction is called a “branch instruction” and the place where we branch
i.e. “Loop” is called “branch target”. Since branching is based on a condition that R1 > 0,
the branching is also called “conditional branching” ex: Branch > 0 Loop is a condition
branch instruction .
3.7.6 Conditional codes:
Processor has a special register called as “condition codes register” or “status register”. This
register is a set of flags. Each flag has a special meaning.
Four out of these flags are:
Flag Description
N(negative) set to 1 if result is negative, otherwise cleared to 0
Z(zero) set to 1 if result is 0, otherwise cleared to 0
V(overflow) set to 1 if arithmetic overflow occurs, otherwise cleared to 0.
C(Carry) set to 1 if a carryout results for the operation, otherwise cleared to 0.

The N and Z flags values updated while

i. result of an arithmetic or logic operation is negative or zero.
ii. By instructions that transfer the data such as move, load and store.
V flag : when result of arithmetic operation is outside the range of values that can be represented
by the number of bits available for the operands.
C flag is set 1 if a carry occurs from the most significant bit position during an arithmetic operations.
The instruction “Branch > 0 Loop” instruction is executed, it checks the “zeroflag” AND
“negative flag”. Since negative flag is set, it will NOT jump to loop, instead “Next instruction” is
executed.
3.8 Addressing Modes
The different ways in which the location of an operand is specified in an instruction are
referred to as addressing modes. The data that reside in the computer memory is organized in a

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variety of ways. Programmer declare data as constant, local variable, global variable, array and
pointers.
The table 3.1 gives different types of addressing modes
Opcode addresss

Table 3.1 Generic addressing modes

3.8.1 Implementation of variables and constants

i. Implicit addressing mode: Instruction knows where to access the operands
Ex : INCA // increment the accumulator
ii. Immediate Mode : In immediate mode, the operand is given explicitly in the instruction.
It represents the constant or address
Example 1: Move #200, R0
The above instruction places 200 in register R0 or initialization R0 by 200.
Example 2: In C language we do something like A=B + 6 in assembly language. The
same statement is executed as:
Move B,R1
Add #6,R1 // Immediate Mode
Move R1,A
iii. Register addressing mode : The operand is the contents of a processor register, the name
(address) of the register is given in the instruction. i.e. if one of the operand is a register then
the mode is called Register Mode.
Ex: Move R1, R2
iv. Direct addressing Mode or Absolute addressing mode
The operand is a memory location; the address of this location is given explicitly in the instruction
(it is also called Direct Mode)
Ex: Move LOC, R2
3.8.2 Indirection & Pointers
The instruction does not give the operand or its address explicitly. Instead, it provides information
from which the memory address of the operand can be determined
v. Indirect Mode : The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction.

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Ex1 : ADD (R1), R0

From figure 3.11(a) , To execute the add instruction the processor uses the value B. which is in
register R1, as the effective address of the operand. It requests a read operation from the memory
to read the contents of location B.
Ex2 : ADD (A), R0
Indirect addressing through a memory location is also possible as shown in figure 3.11(b)

( a) (b)
Figure 3.11 Indirect Addressing

Note: Parenthesis is used to refer operands accessed that are accessed in indirect mode.

The register or memory location that contains the address of an operand is called a pointer.
Indirection and the use of pointers are important and powerful concepts in programming.

Example 1:
Let us see an example of adding n numbers using a pointer:

Figure 3.12 Use of indirect addressing in the program of adding n numbers

In the above program, Add (R2),R0 will add the contents of memory pointed to by register R2
withthe register R0, and the instruction “Add #4,R2” is executed, then R2 points to next location
which has next number to be added to R0 (provided the index in R1 has not reached 0).
Example 2: In a “C” program, the instruction
A = *B
copies the value pointed to by pointer B into variable A.
The above can be done in assembly language in two ways:
Method 1: Method 2:
Move B, R1 Move (B), A
Move (R1), A

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3.8.3 Indexing and Arrays

This addressing modes are useful when dealing with list and arrays
vi. Index Mode: The effective address of the operand is generated by adding a constant value
to the contents of register.
Indexing mode symbolically as X(Ri).
Where X denotes the constant value contained in the instruction and Ri is the name of the register
involved. The Effective address is
Effective Address EA = [Ri] + X
There are two possibilities:
Possibility 1: Register contains base address : In Figure 3.13, the index R! contains the address
of a memory location and the the value X defines an offset ( displacement) from this address to the
location where the operand is found.
Ex: Add 20(R1),R2
In this case, we shall add the value stored at location 1020 with the value in Register R2. Register
R1 contains base address 1000.

Figure 3.13 offset is given as a constant

Hence, when Add 20(R1),R2 instruction is executed, then the following steps happen:
Step 1: 20 is added to R1 register value 1000 to get 1020.
Step 2: Value stored in location 1020 is picked
Step 3: This value is added to the value stored in register R2.
Possibility 2: Register contains offset address
Ex: Add 1000(R1),R2 //R1 contains offset 20
In this case, we shall add the value stored at location 1020 with the value in Register R2. Register
R1 contains the offset 20.

Hence, when Add 1000(R1),R2 instruction is executed, then the following steps happen:
Step 1: 1000 gets added to the register value 20 to get 1020.
Step 2: Value stored in location 1020 is picked
Step 3: This value is added to the value stored in register R2

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Example 3: We have a student database with following fields: Student ID, Test 1 marks,
Test 2 marks and Test 3 marks as shown below:

Student ID Test 1 Test 2 Test 3

Calculate the total of Test 1, calculate Total of Test 2 and calculate Total of Test 3.
Solution: The aim is to separately add all the Test 1 score, Test 2 score & Test 3 score.
If there are “n” students in the class, let us list the student details for all students one after the other
in the memory as shown in figure 3.14.

Figure 3.14 A list of students and marks

Points to note: Each Student details occupies 4 words = 4 x 4 bytes = 16 bytes.
So, student1 details take “LIST” to “LIST + 15”
Student2 details take “LIST + 16” to “LIST + 31” and so on…
• Consider the base address of student as LIST, then test1 details is obtained by adding 4 to LIST,
the test2 details by adding 8 to LIST, the test3 details by adding 12 to LIST.
• To jump from student 1’s details to student 2’s details we need to add “16” to base address, i.e.
LIST + 16 onwards gives the student 2 details.
• The code for the program is given in figure 3.15

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Figure 3.15 Index addressing used in accessing test scores in the list in fig 3.14
To understand the above code, we can divide the code into 3 parts:
Part 1: Initialization
• Move #List,R0 makes R0 contain base address of the student array
• Clear R1, Clear R2, Clear R3 makes R1, R2, R3 to 0.
• R1, R2, R3 will be used for temporary calculations.
• Move N, R4 makes R4 contain N (no. of students)
Part 2: Calculation
• Add 4(R0),R1: This means, to base address add 4 to reach Test1 marks of student1, then add
it to R1.Now, R1 contains 1st students test1 marks
• Add 8(R0),R2: This means, to base address add 8 to reach Test2 marks of student 1. Add the
marks to R2. Now, R2 contains 1st students test2 marks.
• Add 12(R0),R3: This means to base address add 12 to reach Test3. Now, R3 contains 1st
students Test3 marks.
• Add #16,R0: R0 was pointing to 1st student’s base address. When we add 16 to it, R0 now
jumps to 2nd student’s base address.
• Decrement R4 to indicate we are done with 1st student.
• Now repeat part 2 again, since R0 now points to 2nd student, we will end up adding
2ndstudent’s marks to 1st student.
• Again when we do Add #16,R0 we will jump to 3rd student and add 3rd student’s marks to
that of 2nd& 1st.
• This goes on till “Decrement R4” results in 0 which means we are done with all students.
Part 3: At this point, R1 has the sum of Test 1 marks of all students, R2 has the sum of Test 2
marks of all students, R3 has the sum of Test 3 marks of all students.
Move R1,SUM1 // Copies the contents of R1 to SUM1
Move R2,SUM2 // Copies the contents of R2 to SUM2
Move R3,SUM3 // Copies the contents of R3 to SUM3.

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Note: In all the examples, we were using a register to store base address & the index value was
being specified directly. Example: Add 4(R0),R1
The constant can also be stored in a register. In which case the operand looks as (Ri,Rj)
Example: Add (R5,R0), R1
Where R5 can store the value 4, generally this is used for 2-D array manipulation.
Note: Another improvisation is that to the two register notation, we could add a constant value.
This is represented as X(Ri,Rj).
3.8.4 Relative Addressing
In this mode the program counter is used instead of a general purpose register i.e X(PC)
vii. Relative Mode: The effective address is determined by the index mode using the program
counter in place of the general purpose register Ri.
Example : Branch >0 LOOP
An instruction causes program execution to go the branch target location identified by the name
LOOP if the branch instruction satisfied. This location can be computed by specifying it as an
offset from the current value of the program counter.
Note : The relative mode is similar to index mode discussed previously, but here the base address
is specified by program counter (PC) instead of some register Ri.
Relative mode as X(PC) where as in index mode was represented as X(Ri)
3.8.5 Additional modes
viii. Auto-increment mode: The effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
The instruction is shown as (Ri)+,
if Ri register points to an operand which is 32-bit, then (Ri)+ will move the pointer by 4 bytes to
the next word.
ix. Auto-decrement mode: The contents of the register specified in the instruction are first
automatically decremented and then used as the effective address of the operand.
It is shown as – (Ri).
It is similar to Auto-increment except that
• The address is decremented first before using the value of the address, and
• It is a decrement operation.
The below program is to add “n” numbers using auto-increment operation.

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