JIM

MA UNIVERSITY

AGARO CAMPUS

COMPUTER SCIENCE DEPARTMENT

Microprocessor and Assembly Language

Individual Assignment
NAME : Segni Abera

ID RU1829/15
Submitted Date Jan 20/2025
Contents
1. Define Interrupts:.......................................................................................................................1
2. Types of Interrupts:....................................................................................................................2
3. Interrupt Instructions:.................................................................................................................2
4. Real Mode vs. Protected Mode:................................................................................................4
5. Interrupt Flag Bits:.....................................................................................................................5
6. Interrupt Vector Table:...............................................................................................................6
7. Steps in Interrupt Processing:...................................................................................................7
8. Handling Hardware Interrupts:...................................................................................................8
References:...................................................................................................................................9

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1. Define Interrupts:

An interrupt in a microprocessor system is essentially a signal that causes the CPU to

temporarily halt its current operation and execute a special routine, known as an interrupt handler
or interrupt service routine (ISR), to address a particular event or condition. The main purposes
of interrupts in such systems include handling asynchronous events, managing I/O operations,
responding to hardware signals like timer events, and dealing with exceptions or errors. For
instance, when a user types on a keyboard, an interrupt is generated to inform the CPU that
there's data to be read, allowing the system to respond promptly without constantly checking the
keyboard status. This mechanism enhances system efficiency by enabling the CPU to focus on
other tasks until an interrupt signals an immediate need for attention.

Interrupts are beneficial in various scenarios: they allow for real-time processing where timing is
critical, like in control systems where a sensor might trigger an interrupt when a certain threshold
is reached, ensuring immediate action. In multitasking environments, interrupts help manage task
switching by signaling the CPU when a task needs attention, improving system responsiveness.
They are also crucial in handling errors or exceptions, where an interrupt can notify the system to
execute recovery procedures or log the event for later analysis. For example, in a computer

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game, interrupts could handle user input from a joystick or manage the timing of game events,
ensuring smooth gameplay without the CPU needing to poll these devices continuously.

2. Types of Interrupts:

There are primarily two types of interrupts in computer systems: hardware interrupts and
software interrupts. Hardware interrupts, also known as external interrupts, are triggered by
external hardware devices. These could include pressing a key on the keyboard, moving the
mouse, or a timer reaching its count. They are crucial for real-time interaction with the system's
peripherals. For example, when a hard drive completes a data transfer, it sends a hardware
interrupt to inform the CPU, allowing the system to proceed with the next operation without
delay. Hardware interrupts typically have priority levels, with critical devices like system clocks
often having higher priority.

Software interrupts, on the other hand, are initiated by software executing on the CPU. They are
used for system calls, where a program requests services from the operating system, like opening
a file or displaying a message. They allow for controlled interaction between user-level
applications and the system kernel. An example would be when a program uses an interrupt to
call an operating system function to allocate memory. Software interrupts can be thought of as a
way for software to 'interrupt' the normal flow of execution to request privileged operations or
services that require kernel intervention. They are often used in debugging (like breakpoints) and
in system calls in operating systems like Unix or Windows, where specific interrupt numbers
correspond to different system services.

3. Interrupt Instructions:

Interrupt instructions in assembly language are used to invoke interrupt handlers or service
routines. Here's a breakdown of some commonly used interrupt instructions:

● INT (Interrupt): This instruction is used to call an interrupt handler. The operand
specifies the interrupt number which corresponds to an entry in the Interrupt Vector

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 Table (IVT). For example, INT 0x10 in x86 assembly might be used to call BIOS video
services. The CPU uses this number to find the address of the interrupt handler in the IVT
and then transfers control to it.
● INTO (Interrupt on Overflow): This instruction checks the Overflow Flag (OF) in
the flag register. If OF is set, it triggers an interrupt with number 4 (in x86 systems),
which is typically associated with an overflow exception. This is useful for error handling
in arithmetic operations where an overflow might lead to unexpected results.
● INT n: Similar to INT, where 'n' is an immediate value representing the interrupt
number. This directly specifies which interrupt handler should be executed. For instance,
INT 0x80 was famously used in Linux for system calls.
● IRET (Interrupt Return): This instruction is used to return from an interrupt handler
back to the interrupted code. It restores the CPU's state from the stack, including flags,
registers, and the program counter, ensuring that the program continues from where it
was interrupted. The instruction is crucial for maintaining the integrity of the program
flow after an interrupt.

An assembly code example demonstrating these instructions could look like this:

assembly
; Example of using INT for a system call in x86
mov eax, 1 ; System call number for exit
mov ebx, 0 ; Exit status
int 0x80 ; Call kernel to exit

; Example of INTO
add ax, bx ; Perform addition
into ; If overflow, interrupt 4 is triggered

; Example of IRET in an interrupt handler

pushf ; Save flags
push cs ; Save code segment
pushf ; Save flags again for IRET
; Interrupt handling code here
iret ; Return from interrupt

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This example shows how these instructions facilitate communication between the CPU and the
operating system or hardware, allowing for efficient handling of various system events.

4. Real Mode vs. Protected Mode:

Real Mode and Protected Mode are two operational states of x86 processors that significantly
affect how interrupts are handled:

● Real Mode: This was the original mode of operation for the 8086 and early x86
processors. In Real Mode, the CPU operates with a simple, flat memory model where
addresses are 20-bit, allowing access to 1MB of memory. Interrupts in Real Mode are
managed through the Interrupt Vector Table (IVT), which is located at the beginning of
memory (addresses 0x0000 to 0x03FF). Here, each interrupt vector is a 4-byte pointer
consisting of a segment and offset. When an interrupt occurs, the CPU directly jumps to
the address specified by this vector. The limitations include no memory protection,
meaning one program can easily corrupt another's memory, and limited address space.
Also, there's no concept of privilege levels, so any interrupt can potentially disrupt the
system's stability.
● Protected Mode: Introduced with the 80286, Protected Mode offers a more
sophisticated environment with virtual memory, paging, and segmentation, allowing for
much larger address spaces (up to 4GB with 32-bit addressing). Interrupt handling in
Protected Mode uses the Interrupt Descriptor Table (IDT) instead of the IVT. The IDT
can contain various types of descriptors, including interrupt gates, trap gates, and task
gates, which provide different levels of privilege and protection. Here, interrupts can be
prioritized, and there's support for hardware task switching. Protected Mode addresses
many of Real Mode's limitations by introducing memory protection, where each program
runs in its own protected space, reducing the risk of one program affecting another.
Additionally, it supports virtual memory, allowing the system to use disk space as an
extension of RAM, which is not available in Real Mode. However, this complexity also
means that setting up interrupts requires more overhead, including setting up the IDT and
handling different privilege levels, which can be more challenging for developers.

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5. Interrupt Flag Bits:

The Interrupt Flag (IF) is a crucial bit within the flag register of the x86 architecture, which
controls the CPU's ability to respond to maskable hardware interrupts. Here's how it works:

● When the IF bit is set to 1, the CPU is in a state where it can accept maskable interrupts.
This means that if a hardware device generates an interrupt signal, the CPU will
acknowledge it, save the current state, and jump to the appropriate interrupt handler as
specified by the Interrupt Vector Table or Interrupt Descriptor Table, depending on the
mode (Real or Protected). This state is essential for normal operation as it allows the CPU
to respond to events like keyboard presses, disk I/O completion, or timer ticks without
needing to constantly check these devices.
● Conversely, when the IF bit is cleared to 0, the CPU becomes interrupt-disabled for
maskable interrupts. This state is used when the system needs to perform critical
operations where an interrupt might cause data corruption or timing issues. For instance,
during certain phases of operating system boot or while executing atomic operations in
multi-threaded environments, disabling interrupts ensures that the CPU completes these
operations without interruption.

The state of the IF bit directly affects interrupt processing. If an interrupt occurs when IF is 0, the
CPU will not respond to it until IF is set back to 1. However, non-maskable interrupts (NMI) can
still occur regardless of the IF state, as they are designed for critical, system-level events that
must be handled immediately, like hardware failures or emergency system conditions.

In software, the IF bit can be manipulated using instructions like STI (Set Interrupt Flag) to
enable interrupts and CLI (Clear Interrupt Flag) to disable them. This control is vital in ensuring
that interrupts do not interfere with critical sections of code or when precise timing is necessary.

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6. Interrupt Vector Table:

The Interrupt Vector Table (IVT) is a fundamental component in the architecture of x86
processors, particularly when operating in Real Mode. It serves as a jump table that directs the
CPU to the correct interrupt handler when an interrupt occurs. Here's a detailed explanation:

● Structure: In Real Mode, the IVT is located at the very beginning of the system
memory, from address 0x0000 to 0x03FF. This table consists of 256 entries, each 4 bytes
long, making up a total of 1KB. Each entry corresponds to an interrupt number from 0 to
255. Each entry is a far pointer, which includes a 2-byte segment address and a 2-byte
offset within that segment, pointing to the start of the interrupt service routine (ISR) for
that interrupt.
● Function: When an interrupt occurs, the CPU automatically multiplies the interrupt
number by 4 to find the correct entry in the IVT. It then loads the segment and offset
from this entry into the CS (Code Segment) and IP (Instruction Pointer) registers,
respectively, causing an immediate jump to the specified ISR. This process ensures that
the CPU handles the interrupt efficiently without needing to search for the handler's
location during runtime.
● Usage: The IVT is used for both hardware and software interrupts. For example,
hardware interrupts like those from the keyboard or timer are mapped to specific interrupt
numbers, while software interrupts, often used for system calls, have their own set of
numbers. In Real Mode, the simplicity of the IVT allows for quick setup and handling but
lacks the advanced features of Protected Mode like memory protection and privilege
levels.
● Example: If interrupt number 0x13 (typically for disk services in BIOS) is triggered, the
CPU would look at the entry at address 0x13 * 4 = 0x4C in the IVT to find where to
jump to handle this interrupt.

In Protected Mode, this concept evolves into the Interrupt Descriptor Table (IDT), which
provides more sophisticated handling with descriptor entries that include additional information
like privilege levels and gate types for better security and system management.

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7. Steps in Interrupt Processing:

Interrupt processing involves a series of well-defined steps that ensure the CPU handles
interrupts efficiently and returns to the original task seamlessly. Here's a detailed breakdown:

● 1. Interrupt Occurs: An interrupt signal is generated by a hardware device or through a

software interrupt instruction. This could be from pressing a key, a timer expiring, or a
program invoking a system call.
● 2. CPU Acknowledges: Upon receiving the interrupt signal, the CPU finishes the
current instruction it was executing. This ensures that the state of the CPU is consistent
before it begins handling the interrupt.
● 3. Save CPU State: The CPU saves its current state, which includes the contents of
various registers like the program counter (EIP/RIP), flags, and general-purpose registers.
This is typically done by pushing these values onto the stack, ensuring that the
interrupted task can be resumed later.
● 4. Fetch Handler Address: Depending on whether the system is in Real Mode or
Protected Mode, the CPU fetches the address of the interrupt handler from either the
Interrupt Vector Table (IVT) or the Interrupt Descriptor Table (IDT). In Real Mode, it
uses the interrupt number to calculate the address in the IVT. In Protected Mode, it looks
up the IDT entry which might involve more complex operations due to privilege checks
and descriptor types.
● 5. Execute Handler: The CPU jumps to the address of the interrupt handler and begins
executing the interrupt service routine (ISR). This routine deals with the event that caused
the interrupt, like reading a keystroke or handling a timer event.
● 6. Acknowledge Interrupt: If it's a hardware interrupt, the CPU might send an
acknowledgment signal back to the interrupting device to inform it that the interrupt has
been received and is being processed.
● 7. Restore and Return: After the ISR completes its task, the CPU uses the IRET
(Interrupt Return) instruction to restore the saved state from the stack. This includes
popping the saved registers, flags, and program counter back into their respective places,
effectively resuming the execution of the program from where it was interrupted.
● 8. Resume Execution: The CPU continues executing the previously interrupted
program or task as if the interrupt never occurred, maintaining the illusion of
simultaneous processing of multiple events.

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This structured approach ensures that interrupts are handled promptly and efficiently, allowing
for responsive system behavior without losing the context of the original task.

8. Handling Hardware Interrupts:

Handling hardware interrupts involves a coordinated effort between hardware devices, the
interrupt controller, and the CPU. Here’s how this process typically unfolds:

● Interrupt Generation: A hardware device like a keyboard, mouse, or hard drive

generates an interrupt when it needs the CPU's attention, typically due to an event like
data availability or completion of an operation. This is done by sending an electrical
signal on the interrupt line.
● Interrupt Controller: Modern systems use an interrupt controller, like the
Programmable Interrupt Controller (PIC) or Advanced Programmable Interrupt
Controller (APIC), to manage hardware interrupts. The controller receives the interrupt
signal, determines its priority, and if necessary, sends it to the CPU. For instance, in a
system with multiple devices, the controller ensures that critical interrupts like those from
the system timer or critical I/O operations are prioritized over less urgent ones.
● CPU Recognition: Upon receiving the interrupt signal from the controller, the CPU
acknowledges it by sending an acknowledgment signal back through the controller to the
device, signaling that the interrupt is being processed. The CPU then saves its current
state, including the program counter, registers, and flags, to the stack.
● Interrupt Vectoring: The CPU uses the interrupt number provided by the controller
to locate the appropriate interrupt handler in the Interrupt Vector Table (IVT) in Real
Mode or the Interrupt Descriptor Table (IDT) in Protected Mode. This address points
toOops, something broke. Talk to me later?

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References:

1. Geeks for Geeks - [What is an Interrupt](https://www.geeksforgeeks.org/what-is-an-interrupt/)

2. Geeks for Geeks - [Types of interrupts](https://www.geeksforgeeks.org/types-of-interrupts/)
3. Geeks for Geeks - [Interrupt in microcontroller](https://www.geeksforgeeks.org/interrupt-in-
microcontroller/)
4. Study Tonight - [Real Mode versus Protected Mode](https://studytonight.com/operating-
system/real-mode-and-protected-mode.php)
5. Michael J. Spinks et al. - "Microprocessors: Principles and Applications" (No link available)
6. A. Silberschatz et al. - "Operating System Concepts," Wiley (No link available)
7. J. F. Kurose and K. W. Ross - "Computer Networking: A Top-Down Approach," Pearson (No
link available)
8. IBM Technical Library - [Assembly Language
Programming](https://www.ibm.com/docs/en/assembly-language-programming)
9. embedded.com - [microKERNEL Software
Architecture](https://www.microkernelsoftwarearchitecture.com/language/numerous-cpu-micro-
code-semantic-features-improvements-in-memory-management)

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