CMOS VLSI Design

Prof. (Dr.) Purvang Dalal

Department of Electronics and Communication

Faculty of Technology,
Dharmsinh Desai University, Nadiad.

[email protected] (9426033978)
 Prof. (Dr.) Purvang Dalal

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2 TEXTBOOK, REFERENCE BOOKS

Introduction to VLSI Circuits and Systems.

Uyemura, John P .

Introduction to VLSI Design

ED Fabricius
McGraw-Hill, 1990 ISBN 0-07-19948-5
Basic VLSI Design
D. A. Pucknell, K Eshraghian
Prentice Hall, 1994 ISBN 0-13-079153-9
Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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3 SYLLABUS ( PART 1 ) SECTION I

1st PHASE
Chapter 1 : Introduction – (Concepts .. Rest Self Study )
Chapter 2 : Logic Design with MOSFET
Chapter 3 : Physical Structure of CMOS IC.

2nd PHASE
Chapter 8 : Designing High Speed CMOS Logic Networks
Chapter 9 : Advanced Techniques in CMOS Logic Circuits

3rd PHASE
Chapter 14: System Level Physical Design
Chapter 16: Reliability and Testing of VLSI Circuits
Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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4 LEARNING OUTCOMES

Understand the principles

of the Design and Implementation of standard CMOS integrated circuits
Assess performance
of a digital CMOS circuit
taking into account the effects of real circuit parameters
Encourage / Motivate for research
in Advanced Technology.

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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5 LABORATORY

Quartus II Simulation and Synthesis Package

Coding style
Impact of coding on Hardware

Optimization Problems and Solutions

Digital Design Project

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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6 WHY VLSI

Integration reduces manufacturing cost

Integration improves the design
Almost no manual assembly

Lower parasitic - - > higher speed

Lower power consumption
Physically smaller

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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VLSI APPLICATIONS

VLSI is an implementation technology for electronic circuitry

Analogue or Digital

It is concerned with forming a pattern of interconnected switches

and gates on the surface of a crystal of semiconductor

Microprocessors/Microcontrollers
Memory - DRAM / SRAM
Special Purpose Processors - ASICS (CD players, DSP appl)
Optical Switches

Made highly sophisticated control systems mass-producible

Therefore cheap Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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8 MOORE’S LAW

Gordon Moore: co-founder of Intel

Exponential improvement in technology is a natural trend

VLSI transistor densities

Predicted that the number of transistors per chip would grow
exponentially (double every 18 months)

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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9 THE COST OF FABRICATION

Current cost $2 - 3 billion

Typical fab line occupies 1 city block, a few hundred employees

Most profitable period is first 18 months to 2 years

For large volume IC’s packaging and testing is largest cost

For low volume IC’s, design costs may swamp manufacturing costs
Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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10 STEPS IN VLSI DESIGN
Designer Tasks Tools

Define Overall Chip

Text Editor
Architect C/RTL Model C Compiler
Initial Floorplan

Behavioral Simulation RTL Simulator

Logic Logic Simulation Synthesis Tools
Designer Timing Analyzer
Synthesis
Datapath Schematics Power Estimator

Cell Libraries
Circuit Circuit Schematics Schematic Editor
Designer Circuit Simulation Circuit Simulator
Router
Megacell Blocks

Layout and Floorplan

Physical Place and Route Place/Route Tools
Designer Physical Design
Parasitics Extraction and Evaluation
Dharmsinh Desai University, Nadiad
DRC/LVS/ERC Tools
 Prof. (Dr.) Purvang Dalal

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DESIGN HIERARCHY

System Specifications
(function/speed/size)

Abstract Model
Verilog/VHDL/C/C++
Model – Extensive
Logic Synthesis Simulations
Basic primitive gates/units

Circuit Design
Transistor / Voltage Sources

Physical Design
Silicon Logic Design Verification

Dharmsinh Desai University, Nadiad

Manufacturing / Finished VLSI Chip
 Prof. (Dr.) Purvang Dalal

LOGIC OPTIMIZATION
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• Transistor count reduction AREA

• Circuit count reduction POWER
• Gate count (fanout) reduction DELAY
(Speed)

Area, power and delay reduction improves design

Not possible to reduce all at a time.
Important Design Parameter : Power Delay Product

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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TYPES OF IC

Full Custom

Entire circuit is custom designed for the project.

Tedious and time consuming process – impractical

ASIC - Application Specific Integrated Circuit

System design in term of state diagrams/functions/logic diagrams

Characteristics like speed, size etc. are set by architectural design and can not be
controlled at later stage.

Semi-Custom

Group of primitive cells

Basic function implementation
Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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14

Building Basic Logic Gates using CMOS

Building Complex Logic Gates using CMOS
Logic Interpretation
TG / 2:1 MUX based logic implementation
 Prof. (Dr.) Purvang Dalal

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15
& BOOLEAN OPERATIONS
Assert High Switch Assert Low Switch

y=A.x
y=A.x

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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16
& BOOLEAN OPERATIONS

What if two assert low

switches are connected in
parallel ?

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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17 MOSFET AS SWITCH

Advantages of MOSFET over BJT … prepare a note

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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18 nMOS TRANSISTOR

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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19
nMOS OPERATION

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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20 pMOS TRANSISTOR

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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MOSFET AS SWITCH Supply Voltage and Logic Definitions

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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MOSFET SWITCHING CHARACTERISTICS
Similar to that of ideal Switches

An nMOS behaves like an assert-high switch

An pMOS behaves like an assert-low switch

Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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23 nFET THRESHOLD VOLTAGE
Different from ideal Switch --- FET has switching loss

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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24 pFET THRESHOLD VOLTAGE
polarity is different as holes are the carriers

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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25 nFET PASS CHARACTERISTICS

strong '0'

weak '1'

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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26 pFET PASS CHARACTERISTICS

strong '1'

weak '0'

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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27 CMOS PAIR

X
VDD

0
5V 2:1
0V Vout = 0V MUX = ~X. 5V + X. 0V
0V 1

GND
Make nFET ON for driving 0V (strong ‘0’)
GND Make pFET ON for driving 5V (strong ‘1’)
X
5V Vout = 5V
0
(1) 2:1 = ~X. (1) + X. (0)
GND (0) MUX = ~X
1
INVERTER
nFET & pFET behave in a complementary manner;
Dharmsinh Desai University, Nadiad
in terms of TURN ON input and logic output
 Prof. (Dr.) Purvang Dalal

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CMOS INVERTER

Input (i..e Control Input to Gate) and output are in electrical isolation.
Output is driven by Constant Voltage Source (Strong)
Dharmsinh Desai University, Nadiad
Output strength is irrelevant to the Strength of input (i..e Control Input to
 Prof. (Dr.) Purvang Dalal

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29 BASIC LOGIC USING CMOS

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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TECHNIQUES - CMOS LOGIC IMPLEMENTATION

Use of Boolean Equation

Use of Truth Table

HIGH Output , Charging of output Capacitor , VDD

HIGH output (strong) - PUN - pFET(s)
Atleast one path between VDD & Cout should be ON
Steady State - PDN must be OFF - No Discharging

LOW Output , Discharging of output Capacitor , GND

LOW output (strong) - PDN - nFET(s)
Atleast one path between GND & Cout should be ON
Steady State - PUN must be OFF - No Charging

Use of complementary nMOS/pMOS pair for each input

 Prof. (Dr.) Purvang Dalal

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31 CMOS NOR2 Use of Boolean Equation May not be easy to reduce Eq.

x
x
x
y
g
y y
g
g

g = [x + y]' = ~[x + y] x y

g(HIGH) = g(1) = ~x . ~y
g
Assert LOW Switche(s) [2 nos ] in series

g(LOW) = g(0) = x+y x y

Assert HIGH switche(s) [2 nos] in Desai

Dharmsinh parallel
University, Nadiad
 Prof. (Dr.) Purvang Dalal

Use of Truth Table g = [x + y]' = ~[x + y]

CMOS NOR2
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x
g x
y
x
y
y
x y g(x, y) 0 1
x g y
0 0 1 0 1 0 g
0 1 0
1 0 0 1 0 0 g
1 1 0 x y

x y

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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33 DO IT YOURSELF

Draw CMOS Schematic for out = ~(a . b)

out(1) = ~a + ~b out(0) = a . b
(1) NAND2

(2) XOR2

(3) 2:1 MUX

(4) AOI22

(5) OAI32

(6) AO31

(7) AND2 Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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34 AOI22

Vdd AOI22 = Y = ~ [A.B + C.D] '

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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35 AND2

g=x.y

g(HIGH) = g(1) = x . y
- 2 pFETs in series
- pFET is assert LOW swith, input to the gate is inverted x

g(LOW) = g(0) = x.y =x+y y

- 2 pFETs in series g
- remember nFET is assert HIGH swith so use direct input
x y

How many FETs ?

Can we reduce the number of FETs ?

Design AND3 , AND4 ... count FETs.

Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

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OR3 Alternate Design

Out = A + B + C
OR3 = NOR3 + INV

NOR3 INV OR3

Total FETs
= CMOS pair for each input + Inverted for each inverted input requirement
= ( No of inputs in logic * 2 ) + ( No of inverted inputs * 2 )
= 3 * 2 + 3 * 2 = 12 ----------------------------------------------------------------------->>> 8
 Prof. (Dr.) Purvang Dalal

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37 GENERAL COMMENTS

CMOS transistors are complementary.

It is easy to implement logic having INVERTED output. (i.e. AOI & OAI)

For non-inverted logic, first implement inverted logic and

then use INV (2T) so as to get non-inverted output.

i.e. ONLY 2T in addition; irrespective of number of inputs.

Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

XOR2, XNOR2, 2:1MUX

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

XOR2, XNOR2, 2:1MUX

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

XOR2, XNOR2, 2:1MUX

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 Prof. (Dr.) Purvang Dalal

XOR2, XNOR2, 2:1MUX

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F = ~ [ s.a0 + (~s).a1 ] = (~s).(~a0) + s.(~a1) = ~[F2:1MUX]

[F2:1MUX]  ~[F] using 10T + 2T (INV) = Total 12T design
 Prof. (Dr.) Purvang Dalal

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~s
ao

s
a1

In any case ,
the output MUST be
either Strong '1' or Strong '0‘

So a switch MUST have

strong ‘1’ and strong ‘0’
Pass characteristics
 Prof. (Dr.) Purvang Dalal

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2 Pass Transistors + 2 for X to ~X

Total 4T CMOS Logic

Bi-directional Switch B = f(A,X)

When ON Control input state

Both FETs are ON Determined as per the gate input of nFET
 Prof. (Dr.) Purvang Dalal

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A0
A0
~S F = A0.S’ + A1.S F
A1
A1
S
S
6T Design
4T for TG with 2T for Common Control Input
 Prof. (Dr.) Purvang Dalal

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F = B(~A) + (~B).A

8T Design
4T for TG
2T for Common Control Input
2T for input
 Prof. (Dr.) Purvang Dalal

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 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS
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Stick diagrams are a means of capturing topography & layer information using simple diagrams.
Stick diagrams convey layer information through color codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.

It shows relative placement of components.

Goes one step closer to the layout – We will follow the Layout not Schematics
Helps plan the layout and routing

Does not show Layout can be very time consuming

Exact placement of components / We will show as it is based on layout
Transistor sizes – Wire lengths, wire widths, tub boundaries
Any other low level details such as parasitic
Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS - NOTATIONS

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS - EXAMPLE

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS – SOME RULES

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• When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.

• When two or more „sticks‟ of different type cross or touch each other there
is no electrical contact. (If electrical contact is needed we have to show the
connection explicitly)

• When a poly crosses diffusion it represents a transistor. If a contact is

shown then it is not a transistor

• In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.

All PMOS must lie on one side of the line and all NMOS will have to be on
the other side. Dharmsinh Desai University, Nadiad
 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS
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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

EULER GRAPH
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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

FINDING GATE ORDERING - EULERIAN PATH

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

EULER GRAPH
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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

EULERIAN PATH – OPTIMUM GATE ORDERING

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS – EULERIAN PATH

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

EULER GRAPH
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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS – EULER GRAPH

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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

STICK DIAGRAMS
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Dharmsinh Desai University, Nadiad

 Prof. (Dr.) Purvang Dalal

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Dharmsinh Desai University, Nadiad