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CH.1 8086 16 bit Microprocessor.

Chapter 1 Marks 14
8086 16 bit Microprocessor
1.1 INTRODUCTION TO MICROPROCESSOR:

OVERVIEW OF A SIMPLE MICRO COMPUTER:

The major parts are the central processing unit or CPU, memory, and the input and output circuitry or I/O.

Connecting these parts together are three sets of parallel lines called buses. The three buses are the
address bus, thedata bus, and the control bus.

Block diagram of simple computer or microcomputer.

i) MEMORY: The memory section usually consists of a mixture of RAM and ROM. It may also have magnetic
floppy disks, magnetic hard disks, or laser optical disks. Memory has two purposes. The first purpose is to
store the binary codes for the sequence of instructions you want the computer to carry out. When you
write a computer program, what you are really doing is just writing a sequential list of instructions for the
computer. The second purpose of the memory is to store the binary-coded data with which the computer is
going to be working.

ii) INPUT/OUTPUT: The input/output or I/O section allows the computer to take in data from the outside
world or send data to the outside world. These allow the user and the computer to communicate with each
other. The actual physical devices used to interface the computer buses to external systems are often called
ports.

iii) CPU: The central processing unit or CPU controls the operation of the computer. It fetches binary-coded
instruction of the computer. It fetches binary-coded instructions from memory, decodes the instructions
into a series of simple actions, and carries out these actions. The CPU contains an arithmetic logic unit, or
ALU. Which can perform add, subtract, OR, AND, invert, or exclusive-OR operations on binary words when
instructed to do so. The CPU also contains an address counter which is used to hold the address of the next
instruction or data to be fetched from memory, general-purpose registers which are used for temporary
storage of binary data, and circuitry which generates the control bus signals.

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CH.1 8086 16 bit Microprocessor.

iv) ADDRESS BUS: The address bus consists of 16, 20, 24, or more parallel signal lines. On these lines the
CPU sends out the address of the memory location that is to be written to or read from. The number of
address lines determines the number of memory locations that the CPU can address. If the CPU has N
address lines then it can directly address 2N memory locations.

v) DATA BUS: The data bus consists of 8, 16, 32 or more parallel signal lines. As indicated by the double-
ended arrows on the data bus line, the data bus lines are bi-directional. This means that the CPU can read
data in on these lines from memory or from a port as well as send data out on these lines to memory
location or to a port. Many devices in a system will have their outputs connected to the data bus, but the
outputs of only one device at a time will be enabled.

vi) CONTROL BUS: The control bus consists of 4-10 parallel signal lines. The CPU sends out signals on the
control bus to enable the outputs of addressed memory devices or port devices. Typical control bus signals
are memory read, memory write, I/O read, and I/O writer. To read a byte of data from a memory location,
for example, the CPU sends out the address of the desired byte on the address bus and then sends out a
memory read signal on the control bus.

What is a Microprocessor?
• The word comes from the combination micro and processor.

– Processor means a device that processes numbers, specifically binary numbers, 0’s and 1’s.

– Micro is a new addition.

– In the late 1960’s, processors were built using discrete elements.

– These devices performed the required operation, but were too large and too slow.

– In the early 1970’s the microchip was invented. All of the components that made up the processor were
now placed on a single piece of silicon. The size became several thousand times smaller and the speed
became several hundred times faster.

– The “Micro” Processor was born.

Definition of Microprocessor:

• Microprocessor is a multipurpose, programmable device that accepts digital data as input,

processes it according to instructions stored in its memory, and provides results as output.

or

• A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device

that reads binary instructions from a storage device called memory accepts binary data as input and
processes data according to instructions, and provides result as output.

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CH.1 8086 16 bit Microprocessor.

MICROCONTROLLER:

• A microcontroller (sometimes abbreviated μC, uC or MCU) is a small computer on a single

integrated circuit containing a processor core, memory, and programmable input/output
peripherals.

or

• CPUs with integrated memory or peripheral interfaces History fo Microprocessors:

8086 Microprocessor features:

1. It is 16-bit microprocessor

2. It has a 16-bit data bus, so it can read data from or write data to memory and ports either 16-bit or 8-bit
at a time.

3. It has 20 bit address bus and can access up to 220 memory locations (1 MB).

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CH.1 8086 16 bit Microprocessor.

4. It can support up to 64K I/O ports

5. It provides 14, 16-bit registers

6. It has multiplexed address and data bus AD0-AD15 & A16-A19

7. It requires single phase clock with 33% duty cycle to provide internal timing.

8. Prefetches up to 6 instruction bytes from memory and queues them in order to speed up the processing.

9. 8086 supports 2 modes of operation

a. Minimum mode

b. Maximum mode

Pin Descriptions

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let us now
discuss in detail the pin configuration of a 8086 Microprocessor.
8086 Pin Diagram
Here is the pin diagram of 8086 microprocessor −

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CH.1 8086 16 bit Microprocessor.

Let us now discuss the signals in detail –

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its frequency is
different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries higher
order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address and
later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data
bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
RD (Read)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is an
active high signal. When it is high, it indicates that the device is ready to transfer data. When it is low, it
indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to immediately terminate
its present activity. This signal is active high for the first 4 clock cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock cycle of each
instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an
interrupt request to the microprocessor.
TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the processor has to wait
for IDLE state, else the execution continues.
MN/MX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to
operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives this
signal, it acknowledges the interrupt.

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CH.1 8086 16 bit Microprocessor.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the processor
begins any operation. This signal indicates the availability of a valid address on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver
is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data flow
through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output
device depending on the status of M/IO signal .
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD
signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the address/data buses.
It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of
instruction queue. Their conditions are shown in the following table −
QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0 , S 1 , S 2
These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to
generate memory & I/O control signals. These are available at pin 26, 27, and 28. Following is the table
showing their status −
S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

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CH.1 8086 16 bit Microprocessor.

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus. It
is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release the system
bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT 0 has a higher priority than
RQ/GT1.

GND
Ground for the internal circuit.

Architecture of 8086 microprocessor:

As shown in the below figure, the 8086 CPU is divided into two independent functional parts

1. Bus Interface Unit(BIU)

2. Execution Unit(EU)

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CH.1 8086 16 bit Microprocessor.

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Register organization:

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CH.1 8086 16 bit Microprocessor.

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CH.1 8086 16 bit Microprocessor.

Segment Register
Types of segment registers are follows:-
1. Code segment(CS) : The CS holds the base address for the code segment. All programs are store in
the code segment and accesed via. The IP
2. Data Segment(DS) : DS contains most of data used by program. Data are accessed in the data
Segment by an offset address or content of other register that holds the offset address.DS holds the
base address for the data segment.
3. Stack Segment(SS) : SS defined the area of memory used for the stack. SS holds the base address for
stack segment.
4. Extra Segment register: ES is a additional data segment that is used by some of the string to hold the
destination data.Es holds the base address for the extra segment.
Special purpose register (16 bit)
1. Stack Pointer : Points to stack top, stack is in stack segment, use during instruction like PUSH,
POP,Call etc.
It holds offset address of top of stack.
2. Base Pointer : BP can hold offset address of any location in the stack segment It is used to access
random locations of the stack.
Index register
3. Source index : It hold offset address in the Data segment During string operations.
4. Destination index:- It holds offset address in extra segment during string operations
8086 flag register and its functions:

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CH.1 8086 16 bit Microprocessor.

The description of each status flag bit is as follows:

SF- Sign Flag: After the execution of arithmetic or logical operations, if the MSB of the result is 1, the sign bit is
set. Sign bit 1 indicates the result is negative; otherwise it is positive.(When it is 0 then it is positive, when it is 1 then it is
negative)

ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous
instruction is zero.

PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or borrow in case of
subtraction.

AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.

OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-
bit signed operation and more than 15-bits in size in case of 16-bit sign operations, and then the overflow
will be set.

The description of each control flag bit is as follows:

TF- Trap Flag: If this flag is set, the processor enters the single step execution mode. The processor
executes the current instruction and the control is transferred to the Trap interrupt service routine.

IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by the CPU, otherwise
they are ignored.

D- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto
decrementing mode.

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CH.1 8086 16 bit Microprocessor.

Concept of pipelining
Pipelining in the 8086 microprocessor is a technique that breaks down instruction processing into stages,
allowing multiple instructions to be worked on simultaneously. This improves performance by increasing
the overall instruction throughput.

1. The process of fetching the next instruction when the present instruction is being executed is called
as pipeling.

2. Pipelining has becomes possible due to the use of queue.

3. BIU fills in the queue until the entire queue is full.

4. BIU restart filling in the queue when at least two locations of queue are vacant.

How it works

• The 8086 microprocessor has two functional units: the Bus Interface Unit (BIU) and the Execution
Unit (EU).

• The BIU fetches instructions from memory and stores them in a queue.

• The EU receives instructions from the queue, decodes them, and executes them.

• The BIU and EU operate in parallel, allowing the next instructions to be fetched while the EU is
decoding and executing the previous instructions.

Benefits

• Pipelining allows for parallel instruction fetching and execution.

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CH.1 8086 16 bit Microprocessor.

• It improves overall instruction throughput.

• The execution unit always reads the next instruction byte from the queue in BIU. This is faster than
sending out an address to the memory and waiting for the next instruction byte to come.

• More efficient use of processor.

• Quicker time of execution of large number of instruction.

• In short pipelining eliminates the waiting time of EU and speeds up the processing. – The 8086 BIU
will not initiate a fetch unless and until there are two empty bytes in its queue. 8086 BIU normally
obtains two instruction bytes per fetch.

Memory segmentation
Segmentation is the process in which the main memory of the computer is logically divided into different
segments and each segment has its own base address. It is basically used to enhance the speed of
execution of the computer system, so that the processor is able to fetch and execute the data from the
memory easily and fast.
Need of memory segmentation
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment
Registers.

• Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored.

• Data segment register (DS): points to the data segment of the memory where the data is stored.

• Extra Segment Register (ES): also refers to a segment in the memory which is another data segment
in the memory.

• Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB
memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment
is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous
memory locations. It is an independent, separately addressable unit. Starting address will always be
changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only with
four 64KB segments within the whole 1MB memory.

Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an
8086.

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Physical Memory address generation

Segment register carry 16 bit data, which is also known as base address, BIU attaches 0 as LSB of the base
address. So now this address becomes 20 bit address. Any base/ pointer or index register carry 16 bit offset.
Offeset address is added into 20-bit base address which finally forms 20 bit physical address of memory
location.

Ex 1 :Assume DS= 2632H, SI=4567H

DS : 26320H…….0 added by BIU

+ SI : 4567H

------------------------------------

2A887H

Ex 2 : if the data segment starts at location 1000 H and data reference contains
the address 29 H where is the actual data?

Segment: 0001 0000 0000 0000 0000 (shifting 4 bits) = 10000 H

Offset: 0000 0000 0010 1001 = 0029 H

Physical Address: 0001 0000 0000 0010 1001 = 10029 H

We have seen that how 20-bit physical address is generated within the code segment. In the similar way the
20-bit physical address is generated in the other segments. However, it is important to note that each
segment requires particular segment register and offset register to generate 20-bit physical address as
shown in table below:

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CH.1 8086 16 bit Microprocessor.

Logical address and physical address: There are three type of addresses :-

physical address The physical address is the 20- bit address that actually put on the address pins of the
8086 microprocessor and decoded by the memory interfacing circuitry. The address can have a range of
00000 H to FFFFF H . this is actual physical location in RAM or ROM within the 1 M byte memory range.

offset address The offset address is a location within 64K-byte segment range . therefore, an offset address
can range from 0000 H to FFFF H.

logical address. The logical address consists of a segment value and an offset address. Logical address is
specified as segment: offset

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