COMP

302 Digital Design and Computer Architecture

LEC
Sequential Logic Design
6 Textbook chapter 3

Fall 2024 Dr. Amr Hefny Cairo University

Introduction
• Outputs of sequential logic depend on current
and prior input values – it has memory.
• Some definitions:
– State: all the information about a circuit necessary
to explain its future behavior
– Latches and flip-flops: state elements that store
one bit of state
– Synchronous sequential circuits: combinational
logic followed by a bank of flip-flops

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <2>
Sequential Circuits
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store
information

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <3>
State Elements
• The state of a circuit influences its future
behavior
• State elements store state
– Bistable circuit
– SR Latch
– D Latch
– D Flip-flop

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <4>
Bistable Circuit
• Fundamental building block of other state
elements
• Two outputs: Q, Q
• No inputs
I1 Q
Q Q
I2 I1

I2 Q

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <5>
Bistable Circuit Analysis
• Consider the two possible cases:
0
I1 Q
– Q = 0: 1

then Q = 0, Q = 1 (consistent) 0 1
I2 Q

– Q = 1: I1
1
Q
0
then Q = 1, Q = 0 (consistent)
1 0
I2 Q

• Stores 1 bit of state in the state variable, Q (or Q)

• But there are no inputs to control the state

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <6>
SR (Set/Reset) Latch
• SR Latch R
N1 Q

N2 Q
S
• Consider the four possible cases:
– S = 1, R = 0
– S = 0, R = 1
– S = 0, R = 0
– S = 1, R = 1

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <7>
SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
then Q = 1 and Q = 0 0

1
0
0
1 N2 Q
S

1
R 0
– S = 0, R = 1: N1 Q
1
X Y NOR
then Q = 0 and Q = 1 0 0 1
0
1
0 N2 Q 0 1 0
S
1 0 0
1 1 0

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <8>
SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
then Q = 1 and Q = 0 0

Set the output 10

1 N2
0
Q
S

1
R 0
– S = 0, R = 1: N1 Q
1
X Y NOR
then Q = 0 and Q = 1 0 0 1
0
1
Reset the output 0 N2 Q 0 1 0
S
1 0 0
1 1 0

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SR Latch Analysis
– S = 0, R = 0: Qprev = 0 Qprev = 1

then Q = Qprev R
0
0 R
0 1
N1 Q N1 Q

0 N2 Q 0 N2 Q
S S

– S = 1, R = 1:
1
then Q = 0, Q = 0 R 0
N1 Q
X Y NOR
0
0 0 1
0 0 1 0
0
1 N2 Q 1 0 0
S
1 1 0

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <10>
SR Latch Analysis
– S = 0, R = 0: Qprev = 0 Qprev = 1

then Q = Qprev R
0
0 R
0 1
N1 Q N1 Q
Memory!

0 N2 Q 0 N2 Q
S S

– S = 1, R = 1:
1
then Q = 0, Q = 0 R 0
N1 Q
X Y NOR
0
Invalid State 0 0 1
Q ≠ NOT Q 0 0 1 0
0
1 N2 Q 1 0 0
S
1 1 0

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Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <12>
SR Latch Symbol
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R
inputs
– Set: Make the output 1 SR Latch
Symbol
(S = 1, R = 0, Q = 1)
– Reset: Make the output 0 R Q
(S = 0, R = 1, Q = 0)
S Q
• Must do something to avoid
invalid state (when S = R = 1)
Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <13>
Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <14>
D Latch
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function
– When CLK = 1, D Latch
D passes through to Q (transparent) Symbol
– When CLK = 0,
Q holds its previous value (opaque) CLK
• Avoids invalid case when D Q
Q ≠ NOT Q Q

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <15>
D Latch Internal Circuit
CLK R CLK
D R Q Q

S
D Q
S Q Q
D
Q

CLK D D S R Q Q
0 X
1 0
1 1

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <16>
D Latch Internal Circuit
CLK R CLK
D R Q Q

S
D Q
S Q Q
D
Q

CLK D D S R Q Q
0 X X 0 0 Qprev Qprev
1 0 1 0 1 0 1
1 1 0 1 0 1 0

Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 3 <17>
The latch timing problem

Using Clk as enable for controlled Synchronous

Operation is not Possible for D-Latch
𝑄
𝐶𝑙𝑘 𝐷

𝐷
𝑄′
𝑄 𝐶𝑙𝑘

𝑄𝑏 𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝑄𝑐 As Long as Clk=1 the Latch output asynchronously

follows input Data D
18
Flip-flops

• A flip-flop is a one-bit memory cell, similar to latches

• A flip-flop solves the issue of latch transparency
•Latches are level sensitive memory elements (active as
long as 𝐶𝑙𝑘 = 1)
•Flip-flops are edge-triggered or edge-sensitive
memory elements (active only at transitions; i.e.
either 0 → 1 or 1 → 0)

19
20
Response of Latches vs. Flip-flops

Latch

Flip-flop

Flip-flop
Level-sensitive vs. Edge-triggered storage elements

D-Latch

𝐷 𝑄𝑎

𝐶𝑙𝑘 𝑄𝑎′
+ve Edge FF
𝐶𝑙𝑘 𝑄𝑏
𝐷 𝑄𝑏′
𝑄𝑎 -ve Edge FF

𝑄𝑏 𝑄𝑐
𝑄𝑐 𝑄𝑐′

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚 𝐶𝑖𝑟𝑐𝑢𝑖𝑡

22
Level-sensitive vs. Edge-triggered storage elements

D-Latch

𝐷 𝑄𝑎

𝐶𝑙𝑘 𝑄𝑎′
+ve Edge FF
𝐶𝑙𝑘 𝑄𝑏
𝐷 𝑄𝑏′
𝑄𝑎 -ve Edge FF

𝑄𝑏 𝑄𝑐
𝑄𝑐 𝑄𝑐′

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚 𝐶𝑖𝑟𝑐𝑢𝑖𝑡

23
Master-slave 𝐷 ff using latches

𝐶𝑙𝑘
𝐷
𝑌
𝑄
𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚
Negative Edge D-FF

𝐷 𝑄

𝐶𝑙𝑘 𝐶𝑖𝑟𝑐𝑢𝑖𝑡
2
4
Master-slave 𝐷 ff using latches

𝐶𝑙𝑘
𝐷
𝑌
𝑄
𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚
Negative Edge D-FF
𝐷 𝑄

𝐶𝑙𝑘 𝐶𝑖𝑟𝑐𝑢𝑖𝑡
2
5
Master-slave 𝐷 ff using latches

𝐶𝑙𝑘
𝐷

𝑌
𝑄
𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚
Negative Edge D-FF
𝐷 𝑄

𝐶𝑙𝑘 𝐶𝑖𝑟𝑐𝑢𝑖𝑡
2
6
Registers: Multi-bit Flip-Flop
CLK

D0 D Q Q0

CLK
D1 D Q Q1
4 4
D3:0 Q3:0
D2 D Q Q2

D3 D Q Q3

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