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Branch : CSE & IT Hinglish

WEEKLY TEST – 02
Computer Organization
and Architecture

Maximum Marks 15
Q.1 to 5 Carry ONE Mark Each
[MCQ] (a) Indexed Address modes (AMS)
1. In which address mode, the effective address of the (b) Relative /PC-relative AMS
operand is generated by adding a constant value to the (c) Based/Based register AMS
content of a register? (d) Indirect Addressing modes (AMS )
(a) Absolute mode
(b) Indirect mode [MSQ]
(c) Immediate mode 4. Which of the following cannot be a valid instruction
(d) Index mode for an accumulator based computer system?
X, Y = Addresses, r1, r2 = Registers.
[MCQ] (a) Load X
2. (b) Push Y
Consider 4 byte long jump instruction stored in the
(c) Add Y
memory with a starting address of (200)10. Address
(d) POP X
filed of an instruction contain (–24), base register
contain 400. Calculate the branch address when the
[NAT]
instruction is designed using PC relative addressing
5. A 16 bit instruction is present in memory location
mode?
(a) 180 (b) 80 starting at 250. The instruction is divided into two
(c) 204 (d) 24 fields opcode and address of 8 bit each, where address
field contains the value 232. What will be the effective
address using direct addressing mode.
Consider the memory is byte addressable.
[MSQ]
3. Which of the following address modes is/are the
transfer of control addressing modes (AMS).

Q.6 to 10 Carry TWO Mark Each

[NAT] Immediate 20
6. Register 20
Consider 500 MHZ clock frequency processor uses
different operand accessing mode below. Direct 20
Indirect 20
Operand Accessing Modes Frequencies % 10
Register Indirect
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Indexed 10 [MSQ]
9. In a computer, a memory unit is of size 256 KW,
Also consider 4 cycles consumed for memory
references 2 cycles consumed for ALU operation, 0 where W stands for word. Word size is 32 bits and
cycle consumed when the data is present in register and instruction size is one word. Instruction sports 3 types
instruction itself. Calculate the average execution time of addressing modes (direct, indirect and registers
up to one decimal place to fetch the operand? AMs)
The instruction has four parts:
[MCQ] Addressing mode, operation code, register code, and
7. Which of the following statement(s) is true. address part. An addressing mode part is used to
(a) Indexed addressing mode is used for branch specify one of the 64 registers.
instruction. Which of following given statements is/are true?
(b) If current running or branch instruction memory (a) Addressing mode part takes 2 bits.
address is 456 and the PC-relative address field is (b) Register code takes 6 bits.
44. The current running instruction branch to 500 (c) Address part takes 18 bits.
after its execution. (d) opcode part takes 6 bits.
(c) Indirect addressing mode and base register
addressing modes permits relocation without any [NAT]
change in code. 10. Only instructions with zero, one and two addresses are
(d) For an indirect addressing mode, the address field supported by some CPUs, The size of an op-code field
in the instruction is the address of the effective is of 8 bits, the instruction size is of 16 bits whereas the
address of the actual operand. size of an address is 4 bits what is the maximum
number of two address instructions?
[NAT]
8. A CPU has 19 registers and uses 10 addressing modes.
RAM is 8K × 32 and the instruction is of size 32 bits.
What is the maximum size of the op-code field (in bits)
if the instruction has a register operand and a memory
address operand?
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Answer Key
1. (d) 7. (d)
2. (a) 8. (10 to 10)
3. (b,c) 9. (a, b, c, d)
4. (b, d) 10. (256 to 256)
5. (232)
6. (6.8 to 6.8)
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Hints and Solutions

1. (d) Transfer of control flow AMS
In Index addressing mode, the content of a given Index
register gets added to an instructions address part so as (i) Relative/PC-relative AMS
to obtain effective address. (ii) Based /Based register AMS
2. (a) 4. (b, d)
By default memory is byte addressable. In single accumulator CPU organization, the first ALU
operand is always stored into the accumulator and the
second operand is present either in registers or in the
memory.
Hence, Push B and POP are not a valid accumulator
based instructions.

5. (232 to 232)
In direct addressing mode, the value at the address field
is considered as the actual address of data.

250 opcode
251 232
252

Effective address = 232

6. (Range 6.8 to 6.8)

1
Cycle time =
Frequency

1
= = .002× 10–6
500 M HZ
3. (b,c)
Addressing modes = 2 nsec.

(i) Sequential control flow AMS Immediate → 0 cycle

(ii) Transfer of control flow AMS
Register → 0 cycle
Sequential control flow AMS
Direct → 1 memory Reference (MR) → 4 cycles
S
(i) Implied AM
(ii) Immediate AMS Indirect → 2 MR → 4 ×2 → 8 cycles

(iii) Direct AMS Register Indirect → 1MR→ 4 cycles

(iv) Indirect AMS Indexed → IMR + IALU = 4+2 = cycles

(v) Indexed AMS Average execution time = [0.2 × 0 + 0.2×0+0.2×4 +

0.2 ×8 + 0.1 × 4 + 0.1 ×6] × 2nsec.
(vi) Auto Indexed AMS
= [0.8 + 1.6 + 0.4 + 0.6] ×2nsec.
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= 3.4 × 2 nsec. 9. (a, b, c, d)

Memory unit = 256 KW
= 6.8 n sec.
= 218 W
7. (d)
For example. 1 word = 32 bits = 4B
Add A, @500  A ← A + m [m[500]] Addressing mode = 2 bits for direct, indirect and
registers.

500 625 Register code =  log 2 64  = 6 bits

⁝
625 400 Address lines in memory = 18 bits
Since 500 gives effective address (EA) of 400,
Operation mode (op-code) = 32 – (1 + 6 + 18)
Hence, option (d) is true.
= 32 – 25

8. (10 to 10) Opcode = 7 bits

Number of registers = 19

Number of bits for register field =  log 2 19  10. (256 to 256)

The given data,
=5
The CPU supports instruction size = 16 bits
Addressing modes = 10
Op-code field = 8 bits
Number of bits for a addressing mode =  log 2 10 
Address size = 4 bits
=4 ← 16 bits →
Op-code Add2 Add1
RAM size = 8k × 32
We have two operands
= 213 × 25
so it requires the 2 × 4 bits = 8 bits
Address lines required = 13
And remaining 16 – 8 bits can be used for two address
Instruction size = 32 bits instructions

Addressing Opcode Registers Memory Maximum number of two address instructions

Mode Field address field
= 28 = 256
← 4 bits → ← x bits → ← 5 bits → ← 13 bits →
4 + x + 5 + 13 = 32
x = 32 – 22
= 10

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