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The document outlines the examination format for the Digital Design and Computer Organization course, including modules and questions for the third semester B.E./B.Tech. degree examination scheduled for Dec.2023/Jan.2024. It specifies the requirement to answer five full questions, with details on topics such as Karnaugh maps, Verilog coding, latches, multiplexers, computer operations, addressing modes, interrupts, and bus arbitration. Each question is associated with marks and Bloom's taxonomy levels, indicating the depth of understanding required.

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39 views2 pages

Last QP

The document outlines the examination format for the Digital Design and Computer Organization course, including modules and questions for the third semester B.E./B.Tech. degree examination scheduled for Dec.2023/Jan.2024. It specifies the requirement to answer five full questions, with details on topics such as Karnaugh maps, Verilog coding, latches, multiplexers, computer operations, addressing modes, interrupts, and bus arbitration. Each question is associated with marks and Bloom's taxonomy levels, indicating the depth of understanding required.

Uploaded by

poorvisarvade0
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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GBGS SCHENME

USN BCS302

Third Semester B.E./B.Tech. Degree Examination, Dec.2023/Jan.2024


Digital Design and Computer organization
Time: 3 hrs. Max. Marks: 100
Note: 1. Answer any FIVE fullquestions, choasing ONE full question from etch
etch module.
2. M: Marks, L: Bloom's level,C: Courseoutcomes.
Module M L
Q.1 a Obtain a minimum product of suas With a Karnaugh map. 10 L3 CO1
F(w, x, y, z) =x'z'+ wyz + w'yzxy.
b. Find the minimum sum of products for each function u_ing a Karnaugh 10| L3 CO1
map
i) Fi(a, b,c) = Mpt M M_+ M6
ii) Fa(d, e, f) = Jih(0y1,2, 4)
ii) F:(r, s, t)#r's+r's
OR
Q.2 a,Identify the prime implicants and esseptial prime implicants of the 10 | L3 CO1
following functions:
i) AB, C, D) =(1,3,4, 5, 0, 11,12, 13, 14, 15)
ii)W, X,Y, Z) =EX0, 1,2,512,8, 10, 15).
b. Write the verilog code for the given expression using dataflow, and 5 L2 CO1
behavioral model where
Y= (AB + A'B) (CBtAD) (ABC+ AC).
Write the verilog code and time diaganm for the givencirouit with 5 L2 CO1
propagation dlay yhere the AND, ORgate has a delay of 30ns.and 10ns.

Fig.Q.2(c)
Module -2
Q.3 What is Latch? With neat diagram, explain S-R latch using NOR gate. 10 L3 CO2
Derive chaçactefistics equation.
20 b.(What is priority encoder? Design 4:2 priority encoder with necessary 10 L3 CO2
diagrams.
OR
Q.4 a. Design and explain four bit adder with carry look ahead. 10|L3 CO2

b. What is multiplexer? Design 9:1 mux using 2:1 mux. 10 L3 CO2

lof 2
BCS302
Module-3
Q.5 a. Explain four types of operation performed by computer with an cxample. 10 L2 CO3

Show how below expression will be executed in one aress, two address 10 L1 CO3
zero address and three address processor in an accumul¥tor organization
X=(A * B) +(C* D).
OR
Q.6 What is addressing mode? Explain different ypes ofaddressing mode with 10 L2 CO3
an examples.
h. With a neat diagram, explain basic operational concepts of a computtr. 10 L2 CO3

Module 4
Q.7 Explain the following with gespeet to interrupts with diagram. 10 L2 CO3
i) Vector interrupt
ii) Interrupt nesting
ii) Simultaneous requeat.
b. Explain Direct Memory Access with a neat diagrám. 10 L2 CO3

OR
Q.8 What is Busarbitration? Explain differept týpes of bus arbitration. 10 L2 CO3

b. Discuss dífferent types of mapping fuictions of coaches.als) 10 L CO3

Module-5
Q.9 Draw and explain the siñgle-bus organization of the data path inside 10 L2 CO4
processor.

b. List out the actions peeded to execute the instuction ADD (R3), RI write 10 L2 C04
and explain the sequenceof control steps forthe execution ofthe same.
OR
Q.10 Analyze how does exxecution ofa complete instruction Carry out. 10 L4 C04
02-04-2
b Whatis pipeline? Explainthe performance of pipeline with an example. 10 L4 CO4

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