K.S.

SCHOOL OF ENGINEERING AND MANAGEMENT, BENGALURU-560109

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
SESSION: 2021-2022 (EVEN SEMESTER)
Module-2 : Q & A

Q1 Q. Develop an assembly language program to add first 10 digits using loop, and write comments.
Soln:

Q2 List and explain Arithmetic instructions with examples.

• The arithmetic instructions implement addition and subtraction of 32-bit signed and
unsigned values.

•
Q3 Q. List and Illustrate the different Compare instructions of ARM with examples.
• The comparison instructions are used to compare or test a register with a 32-bit value.
• They update the cpsr flag bits according to the result, but do not affect other registers.
• After the bits have been set, the information can then be used to change program flow
by using conditional execution.
• S suffix is not necessary for comparison instructions to update the flags.
Comparison Instructions

The CMP is effectively a subtract instruction with the result discarded; similarly the TST
instruction is a logical AND operation, and TEQ is a logical exclusive OR operation.
• For each, the results are discarded but the condition bits are updated in the cpsr.
It is important to understand that comparison instructions only modify the
conditional flags of the cpsr and do not affect the registers being compared.
Q4. Q. With a neat diagram and shift instructions, illustrate the working of Barrel shifter.
Data processing instructions are processed within the arithmetic logic unit (ALU). A unique and powerful
feature of the ARM processor is the ability to shift the 32-bit binary
pattern in one of the source registers left or right by a specific number of positions before it enters the ALU. Pre-
processing or shift occurs within the cycle time of the instruction. This shift increases the power and flexibility
of many data processing operations.This is particularly useful for loading constants into a register and achieving
fast
multiplies or division by a power of 2. There are data processing instructions that do not use the barrel shift, for
example, the MUL (multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add) instructions.

Figure shows the data flow between the ALU and the barrel shifter.
 Register Rn enters the ALU without any pre- processing of registers.
 We apply a logical shift left (LSL) to register Rm before moving it to the destination register. This is
the same as applying the standard C language shift operator « to the register.

Q5. Develop an algorithm and assembly language program to find the factorial of N.
Q6 List and illustrate the different multiply instructions of ARM with examples.
Soln:
The multiply instructions multiply the contents of a pair of registers and, depending upon the instruction,
accumulate the results in with another register. The long multiplies accumulate onto a pair of registers
representing a 64-bit value. The final result is
placed in a destination register or a pair of registers.

The number of cycles taken to execute a multiply instruction depends on the processor implementation. For
some implementations the cycle timing also depends on the value in Rs. The following are examples:
a. PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1*r2
POST r0 = 0x00000004
r1 = 0x00000002
r2 = 0x00000002
b. PRE r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
UMULL r0, r1, r2, r3 ; [r1,r0] = r2*r3
POST r0 = 0xe0000004 ; = RdLo
r1 = 0x00000001 ; = RdHi
 • The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a 64- bit result.
• If the result is too large to fit in a single 32-bit register, then the result is placed in two registers labeled
RdLo and RdHi. RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds the higher 32 bits of
the 64-bit result.

Q7 Illustrate the Profiler and Cycle Counter with examples.

Soln:
The first stage of any optimization process is to identify the critical routines
and measure their current performance.
» A profiler is a tool that measures the proportion of time or processing cycles spent in each subroutine.
» You use a profiler to identify the most critical routines.
» A cycle counter measures the number of cycles taken by a specific routine.
» You can measure your success by using a cycle counter to benchmark a given subroutine before and
after an optimization.
» The ARM simulator used by the ADS1.1 debugger is called the ARMulator and provides profiling and
cycle counting features.
» The ARMulator profiler works by sampling the program counter pc at regular intervals. The profiler identifies
the function the pc points to and updates a hit counter for each function it encounters.

Q8 Illustrate the single-register transfer load-store instructions and addressing modes with examples.
Soln: Single-Register Transfer: These instructions are used for moving a single
data item in and out of a register. The data types supported are
- Signed And Unsigned Words (32-bit).
 - Halfwords (16-bit).

- Bytes.
A few load-store single-register transfer instructions are shown below:

Single-Register Load-Store Addressing Modes: The ARM instruction set provides different modes
for addressing memory. These modes incorporate one of the indexing methods:
• Preindex With Writeback
• Preindex
• Postindex

• Each instruction shows the result of the index method with the same pre-condition.
 • The addressing modes available with a particular load or store instruction depend on the
instruction class.

Q9 Illustrate the multiple-register load-store addressing modes with examples.

Soln: Load-store multiple instructions can transfer multiple registers between memory and the
processor in a single instruction. The transfer occurs from a base address register Rn pointing into
memory.

• Multiple-register transfer instructions are more efficient than single-register transfers for
moving blocks of data around memory and saving and restoring context and stacks.
• Load-store multiple instructions can increase interrupt latency. ARM implementations
do not usually accept interrupt instructions while they are executing.
• For example, on an ARM7 a load multiple instruction takes 2 + Nt cycles, where N is
the number of registers to load, t is the number of cycles required for each sequential
access to memory.
• If an interrupt has been raised, then it has no effect until the load-store multiple
instruction is complete. Compilers, such as armcc, provide a switch to control the
maximum number of registers being transferred on a load-store, which limits the
maximum interrupt latency.

In table 8.9 N is the number of registers in the list of registers. Any subset of the current bank of
registers can be transferred to memory or fetched from memory. The base register Rn determines the
source or destination address for a load-store multiple instruction. This register can be optionally
updated following the transfer. This occurs when register Rn is followed by the ‘!’ character, similar to
the single register load-store using pre-index with writeback.
Q1 Examine the working of the any 2 of the following instructions with suitable examples:–
0 A. Swap instruction
B. Software interrupt instruction
C. Program status register instruction
D. Coprocessor instructions
Soln:
A.Swap instruction: The swap instruction is a special case of a load-store instruction. It swaps the contents of
memory with the contents of a register.
This instruction is an atomic operation—it reads and writes a location in the same bus operation, preventing any
other instruction from reading or writing to that location until it completes.
• This instruction is mainly useful for implementing semaphores and mutual exclusion in an operating
system. It allows both a byte and a word swap.

B. B. Software interrupt instruction: Software interrupt instruction (SWI) causes a software interrupt
exception, which provides a mechanism for applications to call operating system routines.
• When the processor executes an SWI instruction, it sets the program counter pc to the offset 0x8 in the
vector table. The instruction also forces the processor mode to SVC, which allows an operating system
routine to be called in a privileged mode.
• Each SWI instruction has an associated SWI number, which is used to represent a particular function
call or feature

C. Program status register instruction: The ARM instruction set provides two instructions to
directly control a program status register (psr).
• The MRS instruction transfers the contents of either the cpsr or spsr into a register; in
the reverse direction.
• The MSR instruction transfers the contents of a register into the cpsr or spsr.
• Together these instructions are used to read and write the cpsr and spsr.
• The syntax has a label called fields. This can be any combination of control (c),
extension (x), status (s), and flags (f ).
• These fields relate to particular byte regions in a psr, as shown in Figure 3.9.
 D. Coprocessor instructions
• Coprocessor instructions are used to extend the instruction set.
• A coprocessor can either provide additional computation capability or be used to
control the memory subsystem including caches and memory management.
• The coprocessor instructions include data processing, register transfer, and memory
transfer instructions.

• In the syntax of the coprocessor instructions, the cp field represents the coprocessor
number between p0 and p15.
• The opcode fields describe the operation to take place on the coprocessor.
• The Cn, Cm, and Cd fields describe registers within the coprocessor.
• The coprocessor operations and registers depend on the specific coprocessor you are
using. Coprocessor 15 (CP15) is reserved for system control purposes, such as memory
management, write buffer control, cache control, and identification registers.

Q1 List the stack operation addressing modes and Illustrate stack operation instruction of ARM
1 processors with examples.
Soln:
• The ARM architecture uses the load-store multiple instructions to carry out stack operations.
• The pop operation (removing data from stack) uses a load multiple instruction; similarly, the
 push operation (placing data onto the stack) uses a store multiple instruction.

• When you use a full stack (F), the stack pointer sp points to an address that is the last used or
full location (i.e., sp points to the last item on the stack).
• In contrast, if you use an empty stack (E) the sp points to an address that is the first unused or
empty location (i.e., it points after the last item on the stack).

When handling a checked stack 3 attributes have to be preserved, i.e. the stack base, the stack
pointer, and the stack limit. Stack base is the starting address of the stack in memory. Stack
pointer initially points to the stack base; as data is pushed onto the stack, the stack pointer
descends memory and continuously points to the top of stack. If the stack pointer passes the stack
limit, then a stack overflow error occurs.

Q1 Q. List and explain the Branch Instructions

2
• A branch instruction changes the flow of execution or is used to call a routine. This type
of instruction allows programs to have subroutines, if-then-else structures, and loops.

• The change of execution flow forces the program counter pc to point to a new address.
The ARMv5E instruction set includes four different branch instructions.
• The address label is stored in the instruction as a signed pc-relative offset and must be
within approximately 32 MB of the branch instruction.

• T refers to the Thumb bit in the cpsr. When instructions set T, the ARM switches to
Thumb state.

• Branches are used to change execution flow. Most assemblers hide the details of a
branch instruction encoding by using labels.

• In the above example, forward and backward are the labels.

• The branch labels are placed at the beginning of the line and are used to mark an address
that can be used later by the assembler to calculate the branch offset.

The branch exchange (BX) instruction uses an absolute address stored in register Rm. It
is mainly used to branch to and from the Thumb code. The T bit of cpsr is updated by
the LSB of the branch register. Similarly, the BLX instruction updates the T bit of the
cpsr with LSB and also sets the link register with the return address.