MICROPROCESSOR & MICROCONTROLLER ISBN: 978-93-5996-719-6

Microprocessor & Microcontroller

(8085, 8086 & 8051) Microprocessor & Microcontroller
BEC-502 (8085, 8086 & 8051)
BEC-502
ABOUT THE AUTHORS
Dr. Arun Kumar G is working as Professor & HOD, Department of
Electronics & Communication Engineering, JSS Academy of Technical
Education, NOIDA, UP. He has completed Diploma in E&C Engineering
V SEMESTER - ECE
from Bapuji Polytechnic, Davanagere, B.E. degree in E&C Engineering
(VTU) from STJIT, Ranebennur, Karnataka, M. Tech. in Digital
Communications & Networking from Govt. UBDTCE, Davanagere,
Karnataka, and Ph.D. in E&C Engineering from VTU, Belagavi in 2016. He As per the syllabus of
has a teaching experience of more than 16 years. Dr. A.P.J. Abdul Kalam Technical University, Uttar Pradesh.
Mr. Ganesha H. S. is working as an assistant professor in the Department of
Electronics and Communication Engineering at the JSS Academy of Technical
Education, NOIDA, Uttar Pradesh. He has completed a B.E. degree in E&C
Engineering (VTU) from APS College of Engineering, Bengaluru, Karnataka.
M.Tech. in Digital Electronics and Communications from the NMAM Institute
of Technology, NITTE, Karnataka, and a pursuing Ph.D. in E&C Engineering
from Amity University, Noida, Uttar Pradesh. He has teaching experience
spanning more than 10 years.

Dr Gayatri Sakya is working as Associate Professor in Department of

Electronics & Communication Engineering, JSS Academy of Technical
Education, NOIDA, UP. She has completed BE in Electronics Engineering from
Motilal Nehru NIT Allahabad Uttar Pradesh and ME (Embedded Systems)
from SGSITS Indore, Madhya Pradesh and Ph.D. in E&C Engineering from
GBU Grater Noida in 2018. She has a teaching experience of more than 20
years.

Dr. Chandra Shankar is currently serving as an Associate Professor in the

Department of Electronics and Communication Engineering at JSS Academy
of Technical Education, located in Noida, Uttar Pradesh, India. He earned his
B. Tech. degree in Electronics and Communication from UPTU Lucknow,
followed by an M. Tech. degree from PTU Jalandhar. In 2018, he successfully
completed his Ph.D. at JAYPEE Institute of Information Technology in Noida,
India. Dr. Chandra Shankar boasts an impressive teaching career spanning
over 16 years.

ISBN:978-93-5996-719-6 Dr. ARUN KUMAR. G

Mr. GANESHA H S
Dr. GAYATRI SAKYA
PRICE: Rs. 200/- Dr. CHANDRA SHANKAR
 MICROPROCESSOR & MICROCONTROLLER
(8085, 8086 & 8051)
BEC-502

VSEMESTER
Electronics & Communication Engineering

As per the syllabus of

Dr. A.P.J. Abdul Kalam Technical University, UP.

Dr. ARUN KUMAR. G

Professor & HOD
Dept. of Electronics & Communication Engineering
JSS Academy of Technical Education, NOIDA, UP.

Mr. GANESHA H S
Assistant Professor & Assistant Registrar
Dept. of Electronics & Communication Engineering
JSS University, NOIDA, UP.

Dr. GAYATRI SAKYA

Associate Professor & HOD, Assistant Registrar
Dept. of Electronics & Communication Engineering
JSS University, NOIDA, UP.

Dr. CHANDRA SHANKAR

Associate Professor
Dept. of Electronics & Communication Engineering
JSS Academy of Technical Education, NOIDA, UP.
 Microprocessor & Microcontroller
(8085, 8086 & 8051)
BEC-502

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Pages : x + 245
Price : Rs. 200/-
ISBN : 978-93-5996-719-6
 Dedicated to
our
Beloved
Family, Friends
&
Teachers
 PREFACE

This book is written as a textbook on Microprocessor & Microcontroller for the fifth-
semester engineering students, following the syllabus of Dr. A.P.J. Abdul Kalam
Technical University, Uttar Pradesh. The aim is to help students grasp the
fundamental concepts of Communication Engineering at a basic level. The book
strives to introduce students and engineers to Communication Engineering using
easily understandable explanations, incorporating recent information, and drawing
comparisons between theories and real-world phenomena. The text employs plain
and lucid language to elucidate the subject's core concepts.

The book covers all major topics of Microprocessor & Microcontroller, accompanied
by numerous illustrations, sketches, and diagrams designed to provide essential
technical information in a simple manner, facilitating easy comprehension by
students. The book also includes exercises at the end of chapters to assess
understanding.

All five units are thoroughly addressed both theoretically and through problem-
solving. A significant number of examination problems are solved to reinforce
theoretical concepts. The book's orientation towards examinations is evident in the
inclusion of solutions to examination question papers. This book will be valuable not
only to students in engineering and polytechnic colleges but also to teachers. We
welcome and highly appreciate suggestions for improving this book.

Special gratitude is extended to His Holiness Jagadguru Sri Shivarathri Deshikendra

Mahaswamiji, President of JSS Mahavidyapeetha Mysuru. Sincere thanks go to the
management of JSS Mahavidyapeetha Mysuru. We acknowledge the assistance
provided by the personnel at JSS Academy of Technical Education, Noida, Uttar
Pradesh, for their unwavering support in producing this book. Lastly, our family
members deserve thanks for their infinite patience and understanding, allowing us
to dedicate time to writing this book. Finally, we are indebted to all individuals who
have directly or indirectly aided us in preparing this manuscript by offering valuable
suggestions and moral support, thus contributing to the realization of this book.

Dr. ARUN KUMAR. G

Mr. GANESHA H S
Dr. GAYATRI SAKYA
Dr. CHANDRA SHANKAR
 MICROPROCESSOR & MICROCONTROLLER - (BEC-501)

SYLLABUS
UNIT 1: Introduction to Microprocessor:
Introduction to Microprocessor: Microprocessor architecture and its operations,
Memory, Input & output devices, The 8085 MPU- architecture, Pins and signals,
Timing Diagrams, Logic devices for interfacing, Memory interfacing, Interfacing
output displays, Interfacing input devices, Memory mapped I/O.

UNIT 2: Basic Programming concepts

Flow chart symbols, Data Transfer operations, Arithmetic operations, Logic
Operations, Branch operation, writing assembly language programs,
Programming techniques: looping, counting and indexing. Additional data
transfer and 16-bit arithmetic instruction, Logic operation: rotate, compare,
counter and time delays, 8085 Interrupts.

UNIT 3: 16-bit Microprocessors (8086) & Peripheral Devices

16-bit Microprocessors (8086): Architecture, Pin Description, Physical address,
segmentation, memory organization, Addressing modes. Peripheral Devices:
8237 DMA Controller, 8255 programmable peripheral interface,
8253/8254programmable timer/counter, 8259 programmable interrupt
controller, 8251 USART and RS232C.

UNIT 4: 8051 Microcontroller Basics

Inside the Computer, Microcontrollers and Embedded Processors, Block Diagram
of 8051, PSW and Flag Bits, 8051 Register Banks and Stack, Internal Memory
Organization of 8051, IO Port Usage in 8051, Types of Special Function Registers
and their uses in 8051, Pins Of 8051. Memory Address Decoding, 8031/51
Interfacing with External ROM And RAM. 8051 Addressing Modes.

UNIT 5: Assembly programming and instruction of 8051

Assembly programming and instruction of 8051: Introduction to 8051 assembly
programming, Assembling and running an 8051 program, Data types and
Assembler directives, Arithmetic, logic instructions and programs, Jump, loop
and call instructions, IO port programming. Programming 8051 Timers. Serial
Port Programming, Interrupts Programming, Interfacing: LCD & Keyboard
Interfacing, ADC, DAC & Sensor Interfacing, External Memory Interface, Stepper
Motor and Waveform generation.

TEXT BOOK

1. Ramesh Gaonkar, “Microprocessor Architecture, Programming, and Applications with the

8085”, 6th Edition, Penram International Publication (India) Pvt. Ltd.,2013.

2. D. V. Hall: Microprocessors Interfacing, TMH 3rd Edition.

3. Mazidi Ali Muhammad, Mazidi Gillispie Janice, and McKinlay Rolin D., “The 8051
Microcontroller and Embedded Systems using Assembly and C”, Pearson, 2nd Edition,2006.
 CONTENTS

UNIT-1: Introduction to Microprocessor

1.1 Introduction to Microprocessor 1
1.1.1 Microcomputer 1
1.1.2 Microprocessor 2
1.1.3 Operations performed by Microprocessor 2
1.1.4 8085 Microprocessor Bus organization 3
1.2 Features of 8085 Microprocessor 4
1.2.1 8085 Microprocessor architecture 5
1.2.2 Pin Diagram of 8085 Microprocessor 10
1.3 Timing Diagram 14
1.3.1 Machine cycles of 8085 14
1.3.2 Timing Diagram of 8085 Instructions 18
1.4 Memory Interfacing 22
1.4.1 Typical EPROM and Static RAM 22
1.4.2 Decoder 23
1.4.3 Address Decoding 25
1.5 Interfacing I/O Devices 31
UNIT-2: Basic Programming concepts
(Annexure-1: 8085 Programming) )

2.1 Flow Chart Symbols 36

2.2 Addressing Modes 37
2.3 Instruction & Instruction Format 38
2.3.1 Data Transfer Instructions 41
2.3.2 Arithmetic Group 44
2.3.3 Logical Group 52
2.3.4 Branch Control Group 58
2.3.5 STACK, I/O and MACHINE CONTROL GROUP 68
UNIT-3: 16-bit Microprocessor and Peripheral devices
3.1 Introduction to 16-bit Microprocessor 8086 72
3.1.1 8086 Internal Architecture 72
3.1.2 Pin Description of 8086 Microprocessor 76
3.1.3 Memory Segmentation and Physical Address 80
3.1.4 Instruction format of 8086 83
3.1.5 Addressing Modes of 8086 84
3.1.6 Evolution of microprocessors 85
3.2 Peripheral devices 87
3.2.1 Direct Memory Access Controller 8237 87
3.2.2 The 8237 DMA Controller 87

i
 3.2.3 DMA Signals 89
3.2.4 Interfacing 8237a DMA Controller with the 8085 90
3.2.5 Programming The 8237 91
3.2.6 DMA Operation 91
3.3 8255 PROGRAMMABLE PERIPHERAL INTERFACE 92
3.3.1 8255 modes of operation 93
3.3.2 PIN DIAGRAM OF 8255 94
3.3.3 8253/8254 PROGRAMMABLE INTERVAL TIMER (PIT) 96
3.3.4 OPERATION OF 8253 98
3.4 PIN DIAGRAM OF 8253/54 103
3.4.1 Applications of 8253/8254 104
3.4.2 3.4.2 DIFFERENCE BETWEEN 8253 AND 8254 105
3.5 8259 PROGRAMMABLE INTERRUPT CONTROLLER 106
3.5.1 Pin Diagram of 8259 108
3.6 8251 USART & RS 232C 109
3.7 3.7 RS232C 111
3.7.1 Electrical Specifications 111
3.7.2 Working of Rs 232c 112
UNIT-4: 8051 MICROCONTROLLER BASICS
4.1 INTRODUCTION TO MICROPROCESSOR & MICROCONTROLLERS:
114
MICROPROCESSOR
4.1.1 Microcontroller 114
4.1.2 Difference between Microprocessor & Microcontroller 115
4.1.3 RISC and CISC processors 116
4.1.4 Difference between RISC and CISC processors 116
4.1.5 Selection Of Microcontrollers 116
4.1.6 Embedded Microcontrollers 117
4.2 8051 ARCHITECTURES 117
4.2.1 STACK (8-bit) 119
4.2.2 Applications of Microcontrollers 120
4.2.3 Special Function Register (Sfr) 122
4.2.4 Features Of 8051 Microcontroller 122
4.3 MEMORY ORGANIZATION 123
4.3.1 Register banks or General-purpose RAM 124
4.3.2 Bit addressable RAM 124
4.3.3 External RAM 125
4.4 I/O PORTS FUNCTIONS 127
4.4.1 PORT 0 (Pins 32-39) 127
4.4.2 PORT 1 (Pins 1-8) 129
4.4.3 PORT 2 (Pins 21-28) 129
4.4.4 PORT 3 (Pins 10-17) 129

ii
4.5 8051 PIN DIAGRAM 130
4.6 EXTERNAL MEMORY (ROM & RAM) INTERFACING 131
4.6.1 Interfacing External Data 131
4.6.2 Interfacing External Rom 20
4.7 8051 ADDRESSING MODES 141
4.8 SPECIAL FUNCTION REGISTERS (SFR’s) 143
UNIT-5: Assembly programming and instruction of 8051
(Annexure-2: 8051 Instruction Set)
5.1 PROGRAMMING 8051 TIMERS 149
5.2 Timer Resistors 149
5.2.1 TIMER 0 Register 149
5.2.2 TIMER 1 Register 150
5.3 TMOD (Timer Mode) register 150
5.3.1 FOR TIMER 1 150
5.3.2 FOR TIMER 0 151
5.4 TCON Register (Timer Control Register) 153
5.5 TIMER MODES 154
5.5.1 TIMER IN MODE 1 154
5.5.2 TIMER IN MODE 2 156
5.6 COUNTER MODE 157
5.6.1 COUNTER 0 IN MODE 1 157
5.6.2 COUNTER 1 IN MODE 1 158
5.6.3 COUNTER 0 IN MODE 2 158
5.6.4 COUNTER 1 IN MODE 2 159
5.7 MAXIMUM COUNT VALUE 160
5.8 SERIAL COMMUNICATION 163
5.8.1 Serial communication 163
5.8.2 Parallel communication 163
5.8.3 DATA TRANSFER RATES 164
5.8.4 BAUD RATE IN THE 8051 164
5.8.5 SCON (serial control) register 165
5.8.6 SBUF register 166
5.8.7 PCON Register 166
5.9 Programming the 8051 to transfer data serially 167
5.10 PROGRAMMING THE 8051 TO RECEIVE DATA SERIALLY 168
5.10.1 SCON register configuration 169
5.10.2 TMOD REGISTER CONFIGURATION 169
5.11 INTERRUPTS 171
5.11.1 INTERRUPT & POLLING METHODS 172
5.11.2 STEPS IN EXECUTING AN INTERRUPT 172
5.11.3 DIFFERENT TYPES OF INTERRUPT 173
iii
 5.11.4 IE AND IP REGISTERS 173
5.11.5 Interrupt Priority 174
5.11.6 ENABLING OR DISABLING OF INTERRUPTS 177
5.12 STACK 178
5.13 SUBROUTINE 181
5.14 ADC0804 (ANALOG TO DIGITAL CONVERTER) 182
5.15 LCD INTERFACING 185
5.15.1 LCD Commands 186
5.15.2 LCD Timing for READ 187
5.15.3 LCD Timing for WRITE 187
5.16 Stepper motor 191
5.16.1 Configuration 192
5.16.2 Stepper motor controller circuit advantages 193
5.16.3 Stepper Motor Applications 193
5.16.4 Stepper motor controller 194
Annexure-1: 8085 Programming 204
Annexure-2: 8051 Instruction Set 216

iv
Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

UNIT
Introduction to Microprocessor

SYLLABUS
Introduction to Microprocessor: Microprocessor architecture and its operations, Memory, Input
& output devices, the 8085 MPU- architecture, Pins and signals, Timing Diagrams, Logic devices for
interfacing, Memory interfacing, Interfacing output displays, Interfacing input devices, Memory
mapped I/O.

1.1 Introduction to Microprocessor:

The 8085 Microprocessor is an 8-bit microprocessor with an 80-instruction set, capable of
interfacing with various peripherals and memory. It was introduced by Intel in 1976 and played
a significant role in the early development of personal computers and embedded systems. It
succeeded the 8080 microprocessor and was one of the earliest microprocessors widely used in
various applications. The 8085 typically operates at a clock speed of 3 MHz, although some
variations and implementations may have different clock speeds. It can access up to 64KB of
memory, making it suitable for a variety of applications. Memory interfacing is a crucial aspect of
working with the 8085.

The 8085 microprocessor is typically programmed using assembly language, which provides low-
level control over its operations. Programmers write code in assembly language and then
assemble it into machine code for execution. It has historical significance in the world of
computing and served as a stepping stone for the development of more advanced
microprocessors and microcontrollers.

1.1.1 Microcomputer:

Figure 1.1: Microcomputer

Microcomputer system consists of four components:
1. Microprocessor (The microprocessor is the heart of microcomputer.)
2. Memory

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

3. Input and
4. Output
The microcomputer is a programmable digital device, designed with registers, flip-flops and
timing elements. It is designed for general-purpose computing tasks and can be used for various
applications.

1.1.2. Microprocessor:
A microprocessor is a specific component within a microcomputer, and it serves as the central
processing unit (CPU) of the system.

Fig. 1.2: Block diagram of Microprocessor.

 The microprocessor mainly contains (CPU)

i. The Arithmetic & Logic unit (ALU)
ii. The control unit and
iii. General-purpose registers.
It does not have built-in RAM, ROM, I/O ports etc. on the chip.
 The microprocessors are commonly referred to as general-purpose microprocessor.
Examples:
Intel: 8086, 80286, 80386, 80486, Pentium etc.
Motorola: 68000, 68010, 68020, 68030 etc.

1.1.3. Operations performed by Microprocessor:

The Operations performed by Microprocessor are
1. Microprocessor-initiated operations
2. Internal operations
3. Peripheral operations or externally initiated operations

1. Microprocessor initiated operations:

The Microprocessor unit (MPU) performs primarily four operations:
i. Memory Read: Read data or Instructions from memory.
ii. Memory write: Writes data or instructions into memory.
iii. I/O Read: Accept data from input devices.
iv. I/O write: Sends data to output devices.

2. Internal operations or 8085 Microprocessor internal data operation:

The internal data operations in 8085 microprocessor are
 Store 8-bit data.
 Perform arithmetic and logical operations.
 Test for conditions.
 Sequence the execution of instructions.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

 Store data temporarily during the execution in the defined R/W memory locations called
the stack.

3. Peripherals or Externally Initiated operations:

The external devices or signals can initiate the following operations using the 8085
Microprocessor Pins: Reset, Interrupt, Ready and Hold.

Reset IN: When the reset pin is activated by an external key, all the internal operations are
suspended and the program counter is cleared i.e. PC = 0000 H. Now, the program execution
will begin from the address 0000 H.

Interrupt: The microprocessor can be interrupted from the execution of instructions and
asked to execute some other instructions called an Interrupt Service Routine (ISR). The
microprocessor resumes it operation after completing the Interrupt service routine.

Ready: It is used by the microprocessor to sense whether a peripheral is ready to transfer data
or not.
If Ready = 1, the peripheral is ready.
If Ready = 0, the microprocessor waits till it goes high.

Hold: When the HOLD pin is activated by an external signal, the microprocessor relinquishes
control of buses and allows the external peripheral to use them. For example: The HOLD signal
is used in Direct Memory Access (DMA) data transfer.

1.1.4. 8085 Microprocessor Bus organization:

Figure 1.3: The 8085-bus structure

The 8085 microprocessor performs operation using three sets of communication lines called
buses:

1 The Address : The 8085 microprocessor uses a 16-bit address bus to access
bus memory locations. This provides a maximum addressable memory
space of 64 KB (kilobytes). This address bus is used for memory
addressing, allowing the microprocessor to fetch. The 8085 MPU
with its 16-bit address lines is capable of addressing 216 = 65.536
memory location (64 Kb) instructions and data from memory and
to write data to memory.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

2 The data bus : The 8085 microprocessor has an 8-bit bi-directional data bus. Data
bus can transfer data in 8-bit chunks or one byte between the
microprocessor and memory, input/output (I/O) devices, and
other components.
3 The control bus :  The control bus is comprised of various single lines that carry
synchronization signals. The control bus is not a group of lines
like Address bus or data bus, but individual lines that provide a
pulse to indicate an MPU operation.
 The control bus in the Intel 8085 microprocessor is a set of
signals that are used to control various operations within the
microprocessor. These control signals coordinate actions such
as memory read and write operations, input/output (I/O)
operations, and the sequencing of instructions.

Figure 1.4: Memory Read operation

 To communicate with a memory, for example, to read an instruction from a memory

location, the MPU unit places the 16-bit address on the address bus s shown in figure 1.
The address on the bus is decoded by an external logic circuit.
 The MPU unit sends a pulse called Memory Read as the control signal. The pulse activates
the memory chip, and the contents of the memory location i.e. 8-bit data are placed on the
data bus and brought inside the microprocessor.

1.2. Features of 8085 Microprocessor:

The features of 8085 Microprocessor are:
 8-bit general purpose µp
 Capable of addressing 64 k of memory
 It has 40 pins
 Requires +5 v power supply
 Can operate with 3 MHz clock
 The clock cycle is 200 ns
 It has 80 basic instructions

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1.2.1. 8085 Microprocessor architecture:

Figure 1.5: 8085 Microprocessor internal architecture

Figure 1.5 shows the 8085 Microprocessor internal architecture.

The various units of a microprocessor are listed below

 Arithmetic and logic Unit
 Accumulator
 General purpose register
 Program counter
 Stack pointer
 Temporary Register
 Status Register (Flags)
 Timing and Control Unit
 Instruction Register and Decoder
 Register array
 Address bus and Data bus

Arithmetic & Logic Unit (ALU):

The ALU unit performs the arithmetic and logical operations like addition, subtraction, Logical
AND, Logical OR, Complement, Increment, Decrement clear etc.

Accumulator
 Accumulator is an 8-bit register which can hold 8-bit data.
 Accumulator is a special register used for temporary data storage and manipulation
during arithmetic and logical operations.
 It also stores the result of the operation carried out by the Arithmetic and Logic unit.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

General purpose register:

Figure 1.6: shows the General-Purpose register

General Purpose Registers

 Apart from accumulator 8085 consists of six special registers called General Purpose
Registers.
 These general-purpose registers are used to hold data like any other registers.
 The general-purpose registers in 8085 processors are B, C, D, E, H & L and each register
can hold 8-bit data.
 These registers can also be used to work in pairs to hold 16-bit data such as B-C, D-E and
H-L to store 16-bit data.
 The H-L pair works as a memory pointer.
 A memory pointer holds the address of a particular memory location and can store 16-bit
address as they work in pair.

Program Counter (PC):

 The Program Counter is a 16-bit register which points to the address of the next
instruction to be executed.
 It automatically increments after fetching each instruction byte.
 When the 8085 microprocessor is reset, the default value of PC is 0000H, indicating the
beginning of the program memory.

STACK:
The stack is a region of memory used for storing data temporarily during program execution.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Stack Pointer (SP):

 The Stack pointer is also a 16-bit register which is used as a memory pointer.
 The stack is a section of RAM used by the CPU to store information temporarily. This
information could be data or an address.
 The register used to access the stack is called the stack pointer (SP) register.
 The last memory location of the occupied portion of the stack is called stack top.
 The storing of a CPU register in the stack is called a PUSH, and loading the contents of the
stack back into a CPU register is called a POP.

Temporary register:
Temporary register is an 8-bit register. This register acts as a temporary memory during the
arithmetic and logical operations. This temporary register can only be accessed by the
microprocessor and it is completely inaccessible to programmers.

Status Register (Flags) or Program Status Word (PSW)

Flags are a set of five flip-flops and are associated with arithmetic and logic operations. These
flags can hold a 1-bit value, either a logic 1 or 0, based on certain conditions that arise during
arithmetic and logic operations.

D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘

Figure 1.7: 8085 microprocessor Flags

The five bits indicate the five-status flag and three bits are undefined. The combinations of these
8-bits are called Program Status Word (PSW). The 5 flags bits are Carry (CY), Zero (Z), Sign (S),
Parity (P) and Auxiliary Carry (AC)

CARRY (CY):
 After performing arithmetic & logic operation if there is a carryout from the MSB (D 7 i.e.
7th bit) then CY = 1, otherwise CY = 0.
 If there is a borrow from subtraction or comparison, the carry flag CY=1; otherwise CY=0.

PARITY FLAG (P):

After performing arithmetic & logic operation if the result in the accumulator has an even
number of 1’s then P=1; otherwise P=0. (i.e. if the result in the accumulator has an odd number
of 1’s then P= 0.)

AUXILIARY CARRY FLAG (AC):

After performing arithmetic & logic operation if a carry is generated from D3 to D4 bit then AC
= 1, otherwise AC = 0.
(This flag is used only internally for BCD operations and is not available for the
programmer).

ZERO FLAG:
After performing arithmetic & logic operation if the result in the accumulator is zero, then Z=1
and if the result in the accumulator is non-zero then Z=0.

SIGN FLAG:
After performing arithmetic & logic operation if the most significant bit (MSB) of the result in
accumulator is 1 i.e. MSB=1, then S=1; otherwise S=0. (if MSB=1, then S=1 & if MSB=0, then S=0).

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

TIMING AND CONTROL UNIT

The Timing and Control Unit plays a crucial role in synchronizing all microprocessor operations
with the clock and generating essential control signals required for communication between the
microprocessor and peripherals. The 𝐑𝐃̅̅̅̅ and 𝐖𝐑
̅̅̅̅̅ signals serve as sync pulses that indicate the
availability of data on the data bus.

INSTRUCTION REGISTER AND DECODER

The instruction register and the decoder are part of the ALU. When an instruction is fetched from
memory, it is loaded in the instruction register. The decoder decodes the instruction and
establishes the sequence of events to follow. The instruction register is not programmable
and cannot be accessed through any instruction.

REGISTER ARRAY
Two additional registers, called temporary registers 𝐖 and 𝐙, are included in the register array
and they are used internally by 8085 microprocessor. These registers are not available to the
programmer. These registers are used to hold 8-bit data during the execution of some
instructions.

ADDRESS BUS AND DATA BUS:

ADDRESS BUS:
 The address bus is a set of physical lines that carry the memory address information. It
specifies the location in memory or a peripheral device where data needs to be read from
or written to.
 In 8085 microprocessor address bus is 16-bit A0 to A15.
 The lower address lines are multiplexed address and data lines i.e. AD0 to AD7 and
higher address line are A8 to A15.
 The address bus is unidirectional. The width of the address bus determines the range of
memory addresses that can be accessed, allowing access to 64 KB of memory locations
(i.e. 216 = 64 KB).

DATA BUS:
 The data bus is set of physical lines that carry the actual data being transferred between
the microprocessor and memory or peripheral devices.
 In 8085 microprocessor data bus is 8-bit bidirectional allowing it to transfer 8-bits of
data at a time.

NUMERICAL ON FLAGs

1. Determine the flag bits in the 8085 microprocessor after adding 80H and 60H.
SOLUTION:
CY D7 D6 D5 D4 D3 D2 D1 D0

80 0 1 0 0 0 0 0 0 0

+ 60 + 0 1 1 0 0 0 0 0

E0 1 1 1 0 0 0 0 0

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Carry Flag (CY) : There's no carry, so CY = 0.

Parity Flag (P) : E0H has 3 set bits, which is odd, so P = 0.
Auxiliary Carry : There's no carry from D3 to D4 bit, so AC = 0.
Flag (AC) OR
Theirs is no carry from the low nibble (4 bits) to the high nibble, so
AC = 0.
Zero Flag (Z) : The result (E0H) is not zero, so Z = 0.
Sign Flag (S) : The leftmost bit (Most Significant Bit - MSB) is 1, it indicates a
negative number i.e. result is E0H. so S = 1.

So, after adding 80H and 60H, the flag values are:
D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘
1 0 0 0 0

2. Determine the flag bits in the 8085 microprocessor after adding CB H and E9 H.
SOLUTION:
CY D7 D 6 D5 D4 D3 D2 D1 D0

1 1 1 1 1

CB 1 1 0 0 1 0 1 1

+ E9 + 1 1 1 0 1 0 0 1

1B4 1 1 0 1 1 0 1 0 0

Carry Flag (CY) : There's carry, so CY = 1.

Parity Flag (P) : B4 H has 4 set bits, which is even, so P = 1.
Auxiliary Carry : There's carry from D3 to D4 bit, so AC = 1.
Flag (AC) OR
Theirs is carry from the low nibble (4 bits) to the high nibble, so AC
= 1.
Zero Flag (Z) : The result (B4 H) is not zero, so Z = 0.
Sign Flag (S) : The leftmost bit (Most Significant Bit - MSB) is 1, it indicates a
negative number i.e. result is E0H. so S = 1.

So, after adding CB H and E9 H, the flag values are:

D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘
1 0 1 1 1

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1.2.2. PIN DIAGRAM OF 8085 MICROPROCESSOR:

Figure 1.8 (a): Pin diagram of 8085 Figure 1.8 (b): Functional Pin diagram

The pins of 8085 microprocessor are as below:

Pin
Pin Name Description
No.
 Crystal (or either RC network or LC network) is connected
at these two pins to set the frequency of internal clock
generator.
1-2 X 1 & X2
 The frequency is internally divided by two. The 8085
microprocessor operates at a frequency of 3MHz, so a 6MHz
crystal is connected externally.
It indicates that the MPU is being reset. The signal can be used to
3 RESETOUT
reset other devices.
The 8085 has two pins for serial Communication: Serial Input Data
(SID) & Serial Output Data (SOD).

SOD (Serial Output Data):

SOD is the serial output data pin. It is used for transmitting data
4& Serial I/O Ports serially from the microprocessor to external devices or peripherals.
5 SOD & SID Data is sent bit by bit through this pin in a sequential manner.

SID (Serial Input Data):

SID is the serial input data pin. It is used for receiving serial data
from external devices or peripherals and transferring it to the
microprocessor. Data is received bit by bit through this pin.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

In the 8085 microprocessor, interrupts are mechanisms used to

temporarily pause the normal program execution and handle
specific events or requests from external devices. The 8085
microprocessor has five interrupt signals that can be used to
interrupt program execution. These interrupt signals are:

TRAP or TRAP Interrupt:

 TRAP is a non-maskable interrupt (NMI) that is generated by
an external device, such as a power failure or a hardware
malfunction.
 When TRAP is triggered, the microprocessor jumps to a
specific memory location address 0024 to execute a
predefined routine.
 The TRAP interrupt has the highest priority and cannot be
disabled.

RST 7.5:
 The RST 7.5 interrupt is a maskable interrupt that is
generated by a software instruction. RST 7.5 can be enabled
or disabled by the microprocessor.
 When RST 7.5 is triggered, the microprocessor jumps to a
specific memory location address 002C to execute a
predefined routine.
 It has the second highest priority.
(INTERRUPTS)
RST 6.5:
TRAP  The RST 6.5 interrupt is a maskable interrupt that is
RST 7.5 generated by a software instruction. RST 6.5 can be enabled
6-11 or disabled by the microprocessor.
RST 6.5
RST 5.5  When RST 6.5 is triggered, the microprocessor jumps to a
INTR specific memory location address 0034 to execute a
̅̅̅̅̅̅̅
𝐈𝐍𝐓𝐀 predefined routine.
 It has the third highest priority.

RST 5.5:
 The RST 5.5 interrupt is a maskable interrupt that is
generated by a software instruction. RST 5.5 can be enabled
or disabled by the microprocessor.
 When RST 5.5 is triggered, the microprocessor jumps to a
specific memory location address 003C to execute a
predefined routine.
 It has the fourth highest priority.

INTR (Interrupt Request):

 INTR is a maskable interrupt request generated by external
devices, such as a keyboard or a mouse.
 INTR is enabled or disabled by software.
 It has the lowest priority and can be disabled.
INTA (Interrupt Acknowledge):
 INTA is not an interrupt.
 It is an interrupt acknowledgement sent by the
microprocessor after INTR is received.

 When the microprocessor acknowledges the interrupt, it

proceeds to execute the corresponding interrupt service
routine.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

SUMMARY OF INTERRUPTS
Address
Maskable or Non-
Interrupt Priority order or
Maskable
Location
1 (Highest Non-maskable
TRAP 0024
priority) (NMI)
RST 7.5 2 Maskable 003C
RST 6.5 3 Maskable 0034
RST 5.5 4 Maskable 002C
5 (Lowest No
INTR Maskable
priority) specific
AD0 to AD7:
 AD0 to AD7 are multiplexed address and data lines that form
the lower byte of the 16-bit Address/Data bus. AD0 – AD7 are
8-bit bi-directional and serve as both A0 – A7 and D0 – D7
simultaneously.
12-  They are used to send both address and data between the
AD0-AD7
19 microprocessor and memory or peripheral devices
 During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts
of the execution, they carry the 8 data bits.

20 GND or VSS Ground

A8 to A15:
 A8-A15 are a set of eight unidirectional lines that form the
21-
A8-A15 upper part of the 16-bit Address bus.
28
 They are used to transmit the most significant bits of the
memory address during memory read and write operations.

ALE (Address Latch Enable):

 When ALE = 1, AD0 to AD7 serve as address lines (A0-A7),
allowing the microprocessor to use them for addressing
30 ALE
memory locations.
 When ALE = 0, AD0 to AD7 serve as data lines (D0-D7),
enabling the microprocessor to send or receive data.
 ̅̅̅̅̅ is an active low signal used to initiate the write
𝐖𝐑
operation when interfacing with memory or peripheral
31 ̅̅̅̅̅
𝐖𝐑 devices.
 When 𝐖𝐑 ̅̅̅̅̅ = 0, It indicates that the data on the data bus are
to be written into a selected memory or I/O location.
 ̅̅̅̅ is an active low signal used to initiate the read operation
𝐑𝐃
̅̅̅̅ when interfacing with memory or peripheral devices.
32 𝐑𝐃
 When ̅̅̅̅𝐑𝐃 = 0, it indicates that the selected I/O or memory
device is to be read and data are available on the data bus.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

These are the status signals sent by microprocessor to distinguish

the various types of operations as mentioned below.
S1 S0 Operations
29 &
S0 & S1 0 0 HALT (No operation)
33
0 1 WRITE
1 0 READ
1 1 FETCH
 I0/ 𝐌
̅ is a status signal used to differentiate whether the
address is for I/O or memory operations.
̅  When I0/ 𝐌 ̅ = 1, the address on the address bus is for I/O
34 I0/ 𝐌
devices.
 When I0/ 𝐌 ̅ = 0, the address on the address bus is for the
memory.
 READY signal is used by the microprocessor to sense whether a
peripheral is ready to transfer data or not.
35 READY
 If READY = 1, the peripheral is ready
 If READY = 0, the microprocessor waits till it goes high.

 When ̅̅̅̅̅̅̅̅̅
𝐑𝐄𝐒𝐄𝐓 ̅̅̅𝐈𝐍 = 𝟎, the microprocessor enters a reset state.
36 ̅̅̅̅̅̅̅̅̅ 𝐈𝐍
𝐑𝐄𝐒𝐄𝐓 ̅̅̅  During this state, all registers and flags are cleared, and the
program counter (PC=00) is typically set to its initial value.
 CLK OUT in the 8085 microprocessor is an output signal that
37 CLK (OUT) carries the microprocessor's clock frequency. This signal can be
used as the system clock for other devices.
HLDA (Hold Acknowledge):
 HLDA is a signal used to acknowledge a HOLD request.
38 HLDA  It indicates that the HOLD request has been received.
 The microprocessor takes over the buses after the removal of
the HOLD request when HLDA goes low.
HOLD (Hold Request):
 It indicates that another device is requesting the use of the
address and data bus.
 After receiving a HOLD request, the microprocessor
39 HOLD
relinquishes (hands over) the use of the buses as soon as the
current machine cycle is completed.
 The microprocessor regains the buses after the removal of the
HOLD signal.
40 VCC +5V DC supply

Note:
In the 8085 microprocessor, "HOLD" and "HLDA" (Hold Acknowledge) are control
signals used to manage external requests for control of the system bus.

Status signals and the status of data bus

̅
I0/ 𝐌 S1 S0 Data Bus Status (Output)

0 0 0 Halt

0 0 1 Memory WRITE

0 1 0 Memory READ

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1 0 1 IO WRITE

1 1 0 IO READ

0 1 1 Op code fetch

1 1 1 Interrupt acknowledge

1.3. Timing Diagram

Timing Diagram is a graphical representation. Timing diagram of 8085 instructions represents

the execution time taken by each instruction in a graphical format. The execution time is
represented in T-states.
The time required to access the memory or input/output devices is called machine cycle. A
portion of an operation carried out in one system clock period is called as T-state.
One T-state is equal to the time period of the internal clock signal of the processor. The T-state
starts at the falling edge of a clock.

1.3.1. Machine cycles of 8085:

The 8085 microprocessor has 5 basic machine cycles. They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)

Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085
processor executes an instruction, it will execute some of the machine cycles in a specific order.

Instruction Cycle:
The time required to execute an instruction is called instruction cycle.

Figure 1.9: Number of Clock Signals in Instruction Cycle

Status of Various Signals for different Operations of 8085 is shown in table below.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Opcode Fetch Machine Cycle Of 8085

 Each instruction of the processor has one-byte opcode.
 The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory
and the remaining T-states are used for internal operations by the processor.

Figure 1.10: Opcode fetch

Memory Read Machine Cycle Of 8085

 The memory read machine cycle is executed by the processor to read a data byte
from memory. The processor takes 3T states to execute this cycle.
 The instructions which have more than one-byte word size will use the machine
cycle after the opcode fetch machine cycle.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.11: Memory Read

Memory Write Machine Cycle Of 8085

 The memory write machine cycle is executed by the processor to write a data byte in
memory. The processor takes 3T states to execute this cycle.
 The instructions which have more than one-byte word size will use the machine cycle
after the opcode fetch machine cycle.

Figure 1.12: Memory Write

I/O Read Machine Cycle Of 8085

 The I/O Read machine cycle is executed by the processor to Read a data byte from the I/O
port or from a peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.13: I/O Read

I/O Write Machine Cycle Of 8085

 The I/O write machine cycle is executed by the processor to write a data byte in
the I/O port or to a peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.

Figure 1.14: I/O Write

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1.3.2. Timing Diagram of 8085 Instructions

Timing Diagram for MVI B, 43H
 Fetching the opcode 06H from the memory 2000H. (Opcode fetch machine cycle)
 Read (move) the data 43H from memory 2001H. (memory read).

Address Mnemonics Opcode

2000H MVI B,43H 06H
2001H 43H

Figure 1.15: Timing Diagram for MVI B, 43H

Timing Diagram for STA 526AH

 STA means Store Accumulator -The contents of the accumulator are stored in the
specified address (526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH (see fig). – OF machine cycle.
 Then the lower order memory address is read(6A). – Memory Read Machine Cycle
 Read the higher order memory address (52) – Memory Read Machine Cycle.
 The combinations of both the addresses are considered and the content from
accumulator is written in 526A. – Memory Write Machine Cycle
 Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.
Address Mnemonics Opcode
41FFH STA 526A 32H
4200H 6AH
4201H 52H

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.16: Timing Diagram for STA 526AH

T states of all Instructions of 8085

Op-
Instruction Operand Bytes MC T Detail
code

Add immediate to
ACI 24 ACI 8-bit data 2 2 7
Accumulator with Carry

ADC B Reg., Add register to

ADC 1,1 1,2 4,7
ADC M Mem. accumulator with carry

ADD B Reg., Add register to

ADD 1,1 1,2 4,7
ADD M Mem. Accumulator

Add immediate to
ADI 24 ADI 8-bit, data 2 2 7
accumulator

Reg., Logical AND with

ANA ANA 1,1 1,2 4,7
mem. Accumulator

AND immediate with

ANI ANI 8-bit, data 2 2 7
accumulator

16-bit Unconditional
CALL CALL 3 5 18
address Subroutine call

Complement
CMA CMA None 1 1 4
Accumulator

CMC CMC None 1 1 4 Complement Carry

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Reg., Compare with

CMP CMP 1,1 1,2 4,7
Mem. accumulator

Compare Immediate
CPI CPI 8-bit 2 2 7
with accumulator

Decimal Adjust
DAA DAA None 1 1 4
Accumulator

Add register pair to H

DAD DAD Reg. Pair 1 3 10
and L registers

Reg., 4,1
DCR DCR 1,1 1,3 Decrement source by 1
Mem. 0

Decrement register pair

DCX DCX Reg. Pair 1 1 6
by 1

DI DI None 1 1 4 Disable Interrupts

EI EI None 1 1 4 Enable Interrupts

5
2 or
or
HLT HLT None 1 mor Halt and enter wait state
mo
e
re

Input data to
8-bit port
IN IN 2 3 10 accumulator from a port
address
with 8-bit address

Reg., 4,1 Increment contents of

INR INR 1,1 1,3
Mem. 0 register/Memory by 1

Increment register pair

INX INX Reg. Pair 1 1 6
by 1

JMP JMP 16-bit 3 3 10 Jump unconditionally

16-bit
LDA LDA 3 4 13 Load accumulator direct
address

B/D reg. Load accumulator

LDAX LDAX 1 2 7
Pair indirect

16-bit Load H and L registers

LHLD LHLD 3 5 16
address direct

Reg. Pair,
Load Register Pair
LXI LXI 16-bit 3 3 10
Immediate
data

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

MOV Rd, Rs
1 4 Move-copy from source
MOV MOV M, Rs 1
2 7 to destination
MOV Rd, M

Reg., Data
2 2 7
MVI MVI Mem., Move immediate 8 bit
2 3 10
Data

NOP NOP None 1 1 4 No Operation

Reg., Logically OR with

ORA ORA 1,1 1,2 4,7
Mem. Accumulator

ORI ORI 8-bit data 2 2 7 Logically OR Immediate

Output Data from

8-bit port
OUT OUT 2 3 10 Accumulator to a port
address
with 8 bit address

Load program counter

PCHL PCHL None 1 1 6
with HL contents

POP OFF Stack to

POP POP Reg. pair 1 3 10
register pair

Push register pair into

PUSH PUSH Reg. pair 1 3 12
stack

Rotate accumulator left

RAL RAL None 1 1 4
through carry

Rotate accumulator right

RAR RAR None 1 1 4
through carry

RLC RLC None 1 1 4 Rotate Accumulator Left

Rotate Accumulator
RRC RRC None 1 1 4
Right

Return from subroutine

RET RET None 1 3 10
unconditionally

RIM RIM None 1 1 4 Read Interrupt Mask

Subtract source and

Reg.,
SBB SBB 1,1 1,2 4,7 borrow from
Mem.
accumulator

Subtract immediate with

SBI SBI 8-bit data 2 2 7
borrow

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

16-bit Store H and L registers

SHLD SHLD 3 5 16
address direct

SIM SIM None 1 1 4 Set Interrupt Mask

6
(in
808
5), Copy H and L registers to
SPHL SPHL None 1 1
5(i the Stack pointer (SP)
n
808
0)

STA STA 16 bits 3 4 13 Store Accumulator Direct

B/D reg. Store Accumulator

STAX STAX 1 2 7
pair Indirect

STC STC None 1 1 4 Set Carry

Subtract register or
Reg.,
SUB SUB 1,1 1,2 4,7 memory from
Mem.
Accumulator

Subtract immediate from

SUI SUI 8-bit data 2 2 7
accumulator

Exchange H and L with D

XCHG XCHG None 1 1 4
and E

Reg., Exclusive OR with

XRA XRA 1,1 1,2 4,7
Mem. accumulator

Exclusive OR immediate
XRI XRI 8-bit data 2 2 7
with accumulator

Exchange H and L with

XTHL XTHL None 1 5 16
top of stack

1.4. Memory Interfacing

The memory is made up of semiconductor material used to store the programs and data. Three
types of memory are,
 Process memory
 Primary or main memory
 Secondary memory

1.4.1 Typical EPROM and Static RAM

 A typical semiconductor memory IC will have ‘n’ address pins, ‘m’ data pins (or output
pins).

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

 Having two power supply pins (one for connecting required supply voltage (V and the
other for connecting ground).
 The control signals needed for static RAM are chip select (chip enable), read control
(output enable) and write control (write enable).
 The control signals needed for read operation in EPROM are chip select (chip enable) and
read control (output enable).

Figure 1.17: Typical EPROM and Static RAM

1.4.2. Decoder

It is used to select the memory chip of processor during the execution of a program. No of IC's
used for decoder is,
 2-4 decoder (74LS139)
 3-8 decoder (74LS138)

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.18: Block diagram and Truth table of 2-4 decoder

Figure 1.19: Block diagram and Truth table of 3-8 decoder

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Memory Interfacing

The following are the steps involved in interfacing memory with 8085 processor.
1. First decide the size of memory requires to be interfaced. Depending on this we can say how
many address lines are required for it. For example, if you want to interface 4KB (212) memory
it requires 12 address lines. Remaining address lines can be used in address decoding.
2. Depending on the size of memory required and given address range, construct address
decoding circuitry. This address decoding circuitry can be implemented with NAND gates and/or
decoders or using PAL (when board size is a constraint).
3. Connect data bus of memory to processor data bus.
4. Generate the control signals required for memory using IO/M’, WR’, RD’ signals of 8085
processor.

1.4.3. Address Decoding

 The result of ‘address decoding’ is the identification of a register for a given address.
 A large part of the address bus is usually connected directly to the address inputs of the
memory chip.
 This portion is decoded internally within the chip.
 What concerns us is the other part that must be decoded externally to select the chip.
 This can be done either using logic gates or a decoder.

Example

Interface 4KB memory to 8085 with starting address A000H.

1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has 16
address lines. Hence four of address lines are used for address decoding
2. Given that starting address for memory is A000H. So, for 4KB memory ending address becomes
A000H+0FFFH (4KB) = AFFFH.

A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 are used
for generating chip select signal for memory chip.
Address decoding circuit using 3X8 decoder

Figure 1.20: Address decoding circuit using 3X8 decoder

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to 74X138
chip as inputs. When these lines are 010 output should be ‘0’. This is provided at O2 pin of 74X138
chip.

Address decoding circuit using only NAND gates:

Figure 1.21: Address decoding circuit using NAND gates

A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So, the circuit for this is as shown
above.

Types of address decoding

There are two types of address decoding mechanism, based on address lines used for generating
chip select signal.
1. Absolute decoding
2. Partial decoding

Absolute decoding

All the higher order lines of microprocessor, left after using the required signals for memory are
completely used for generating chip select signal as shown in above example. This type of
decoding is called absolute decoding.

Partial decoding

Only some of the address lines of microprocessor left after using the required signals for memory
are used for generating chip select signal. Because of this multiple address ranges will be formed.
If total memory space is not required for the system then, this type of address decoding can be
used. The advantage of this technique is fewer components are required for memory interfacing
because of this board size reduces and in turn cost reduces.

Example 1
Connect 512 bytes of memory to 8085
1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directly connect
to address bus of memory.
2. In the remaining A9-A15 for example only A15-A12 are used for generating chip select signal.
A11-A9 are don’t care signals.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Because of the don’t care signals the address range can be

0000 to 01FF
0200 to 03FF
0400 to 05FF
0600 to 07FF
0800 to 09FF
0A00 to 0BFF
0C00 to 0DFF
0E00 to 0FFF

Address decoding circuit

Figure 1.22: Address decoding

Example 2

Consider a system in which 32kb memory space is implemented using four numbers of 8kb
memory. Interface the EPROM and RAM with 8085 processor.
The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the
remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address
lines A0- A12 of the processor are connected to 13 address pins of all the memory. The address
lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chips select signals.
These four chips select signals can be used to select one of the four memory IC at any one time.
The address line A15 is used as enable for decoder. The simplified schematic memory
organization is shown.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.23: Interfacing 16KB EPROM and 16KB RAM with 8085

The address allotted to each memory IC is shown in following table.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Example 3
Interface EPROM of 16 K using 8K X 8 chips and a RAM of 8K using 4K X 8 chips to the system
lines of 8085 using a 3X8 decoder.
 Required EPROM size: 16Kb
 Available EPROM size: 8Kb
 Number of EPROM Chips: 16Kb/8Kb = 2
 Address lines in 8Kb Chip: 8Kb= 8×1kb = 23×210 = 213
 Number of address lines in 8K×8 = 13 (A0 to A12)
 A13, A14 and A15 are used for chip select logic using decoder
 Number of data Lines = 8 (D0 to D7)
 Required RAM size: 8Kb
 Available RAM size: 4Kb
 Number of RAM Chips: 8Kb/4Kb =2
 Address lines in 4Kb Chip: 4Kb= 4×1kb = 22×210 = 212
 Number of address lines in 4K×8 = 12 (A0 to A11)
 Number of data Lines = 8 (D0 to D7)

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.24: Interfacing diagram and Table

Example 4
Design a system for 8085 such that it contains 4KB of EPROM and 2KB of RAM using two 2KB of
EPROM and two 1KB of RAM. Draw the complete interfacing diagram.
 Required EPROM size: 4Kb
 Available EPROM size: 2Kb
 Number of EPROM Chips: 2
 Address lines in 2Kb chip: 2Kb= 2×1kb = 2×210 = 211
 Number of address lines in 2K×8 = 11 (A0 to A10)
 A11, A12 and A13 are used for chip select logic using decoder
 A14, A15 are connected to the two active low enable pins of decoder
 Number of data Lines = 8 (D0 to D7)
 Required RAM size: 2Kb
 Available RAM size: 1Kb
 Number of RAM Chips: 2Kb/1Kb =2
 Address lines in 1Kb chip: 1Kb= 1×1kb = 210
 Number of address lines in 1K×8 = 10 (A0 to A9)
 Number of data Lines = 8 (D0 to D7)

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.25: Interfacing diagram and Table

1.5. Interfacing I/O Devices

 Using I/O devices data can be transferred between the microprocessor and the outside
world.
 This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O.
 The other method is serial I/O where one bit is transferred at a time using the SID and
SOD pins on the Microprocessor.
 There are two ways to interface 8085 with I/O devices in parallel data transfer mode:
 Memory Mapped I/O
 I/O Mapped I/O

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Memory mapped I/O

I/O devices are interfaced using address from memory space. That means I/O device address are
part of addresses given to memory locations.8085 uses 16-bit address to memory interfacing. So,
any address between 0000H-FFFFH can be given to each peripheral. But the addresses given to
peripheral can’t be used for memory. Memory control signals are used as read and write control
signals for peripherals. And all the operations that can be performed on memory can also be
performed on peripherals. No need of using I/O instructions such as IN, OUT.

I/O mapped I/O

In this method separate address space is given to I/O devices. Each I/O device is given an 8-bit
address. Hence maximum 256 devices can be interfaced to the processor. The address range for
the I/O devices is 00H-FFH. I/O control signals are used to perform read, write operations. For
reading data from I/O device or writing data to I/O device IN, OUT instructions need to be used.
Arithmetic and logical operations can’t be performed directly on I/O devices as in memory
mapped I/O. I/O devices can be interfaced, by using buffers for simple I/O i.e., by using address
decoding circuit to enable buffer. For handshake I/O or to interface more peripherals ICs like
8255 peripheral programmable interface (PPI) can be used.

I/O mapped I/O vs. Memory Mapped I/O

Sl.
Memory Mapped I/O IO mapped I/O
No.
1 I/O is treated as memory. I/O is treated I/O.
2 16-bit addressing. 8- bit addressing.
3 More Decoder Hardware. Less Decoder Hardware.
4 Can address 216=64k locations. Can address 28=256 locations.
5 Less memory is available. Whole memory address space is available.
6 Memory Instructions are used. Special Instructions are used like IN, OUT.
7 Memory control signals are used. Special control signals are used.
Arithmetic and logic operations can be Arithmetic and logic operations cannot be
8
performed on data. performed on data.
9 Data transfer b/w register and I/O. Data transfer b/w accumulator and I/O.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Interfacing of Input and Output Devices

I/O Device Selection:

As mentioned earlier, the 8085 gives 8 bit I/O address. This means it can select one of the 256 I/O
ports. To select an appropriate, I/O device, it is necessary to do following things.
1. Decode the address to generate unique signal corresponding to the device address
on the bus.
2. When device address signal and control signal (IOR or IOW) both are low,
generate device select signal.
3. Use device select signal to activate the Input Output Interfacing Techniques.

Figure 1.26: Absolute decoding circuit for I/O Devices

Interfacing Input Device:

The microprocessor 8085 accepts 8-bit data from the input device such as keyboard, sensors,
transducers etc. Figure below shows the circuit diagram to Input Output Interfacing Techniques
(buffer) which is used to read the status of 8 switches. The address for this input device is 80H as
device select signal goes low when address is 80H.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.27: Circuit diagram to interface input port

When the switch is in the released position, the status of line is high otherwise status is low. With
this information microprocessor can check a particular key is pressed or not.

The following program checks whether the switch 2 is pressed or not.

Program:
IN 80H ; Read status of all the switches
ANI 02H ; Mask bit positions for other switches
JZ NEXT ; if program control is transferred to label NEXT, then switch 2 is pressed
otherwise not

Interfacing Output Device:

The microprocessor 8085 sends 8-bit data to the output device such as 7 segment displays, LEDs,
printer etc. Figure below shows the circuit diagram to interface output port (latch) which is used
to send the signal for glowing the LEDs. LED will glow when output pin status is low. The IC
74LS138 and 3 input OR gate is used to generate device select signal. The latch enable signal is
active high. So, NOR gate is used to generate latch enable signal, which goes high when Y 1 and
IOW both are low.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Figure 1.28: Circuit diagram to interface output port

The following program glows the LEDs L1, L3 and L6

L8 L7 L6 L5 L4 L3 L2 L1
1 1 0 1 1 0 1 0 = DAH

The code (data) DAH must be sent on the latch to glow LEDs L1, L3 and L6.
Program:
MVI A, DAH ; Loads the data in the accumulator.
OUT 81H ; sends the data on the latch.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

UNIT
Basic Programming concepts

SYLLABUS
Basic Programming concepts: Flow chart symbols, Data Transfer operations, Arithmetic
operations, Logic Operations, Branch operation, Writing assembly language programs,
Programming techniques: looping, counting and indexing. Additional data transfer and 16-bit
arithmetic instruction, Logic operation: rotate, compare, counter and time delays, 8085 Interrupts.

2.1. FLOW CHART SYMBOLS

SYMBOL SHAPE MEANING
An oval shape indicates the beginning or
OVAL SHAPE
end of a program.

Arrow indicates the direction of the

ARROW
program execution.

RECTANGLE A rectangle represents a process.

A parallelogram represents input or

PARALLELOGRAM
output.

A diamond indicates a decision or

DIAMOND
branching point.

DOUBLE SIDED Represents a predefined process such as

RECTANGE a subroutine.

CIRCLE WITH AN Represents continuation (an entry or

ARROW exit) to a different page.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
2.2. ADDRESSING MODES:
The CPU can access data in various ways. The data could be in a memory or in register or it may
be an immediate value (CONSTANT). The various ways of accessing these data are called
addressing mode.

There are 5 addressing modes in 8085

1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Implied Addressing Mode

1. IMMEDIATE ADDRESSING MODE:

 In immediate addressing mode the 8-bit or 16-bit data (operand) is specified within
the instruction itself.
 The immediate addressing instructions are either 2 bytes or 3 bytes long.
 In 2-byte instruction, the first byte is OPCODE, and the second byte is the 8-bit data.
 In 3-byte instruction, the first byte is OPCODE, second and third bytes are 16-bit data.
 The instruction containing the letter “I” indicate immediate addressing mode.
Examples:
Instruction Comment
MVI A, 42 H ; Move 42 H in register A
ADI 05 H ; Add 05 H to the content of the accumulator.
LXI H, C300 H ; This instruction transfers 16-bit immediate data C300 to HL register
pair. Lower order data (00 H) to L register and high order data
(C3 H) to H register.

2. REGISTER ADDRESSING MODE:

 In register addressing mode, the source and destination operands are in the
general-purpose registers.
 The register addressing instructions are generally of 1 byte i.e. OPCODE only.
 The OPCODE specifies the operation and registers to be used to perform the operation.
Examples:
Instruction Comment
MOV A, B ; Move the content of register B to register A
ADD B ; This instruction adds the content of the B register and A register, the
data is present in both B and A registers. The result is stored in the
accumulator.
PCHL ; This instruction will transfer the content of register pair HL to the PC
(Program Counter).

3. DIRECT ADDRESSING MODE:

 In direct addressing mode, the 16-bit address of the data (operand) is given within
the instruction itself.
 The instruction in the direct addressing mode is 3-byte instructions. The first byte is
OPCODE, the second lower order address mode, and the third is the higher-order address
mode.
 For I/O instruction that uses direct addressing mode is 2-byte as the address if I/O is one
byte.
Examples:
Instruction Comment
LDA C300 H ; Load accumulator directly from the memory location. In this
instruction, the contents of the C300 H memory location are
transferred to the accumulator.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
STA 2500 H ; Store accumulator directly to memory location. In this instruction,
the content of the accumulator is stored at memory location 2500 H.
IN 02 H ; Read data from the PORT B. (Here 02 H is the address of PORT C).

4. REGISTER INDIRECT ADDRESSING MODE:

 In register indirect addressing mode, the address of the data (operand) is specified
by a register pair (i.e. the memory address where the operand is located is specified
by the content of a register pair).

Example 1:
Instruction Comment
LXI H, 3500 H ; Load the H-L pair with 3500 H
MOV A, M ; Move the content of the memory location, whose address is in H-L
pair i.e. 3500 H, to the accumulator
HLT ; Halt

Example 2:
Instruction Comment
LXI H, 3500 H ; Load the H-L pair with 3500 H
ADD A, M ; Add the content of the memory location, whose address is in H-L pair
i.e. 3500 H, to the content of the accumulator
HLT ; Halt

Example 3:
Instruction Comment
LDAX B ; The BC register pair is used as an address and the content of the
memory location specified by the BC pair is copied to the
accumulator.

5. IMPLIED ADDRESSING MODE:

 The implied mode of addressing does not require any data (operand) or memory
address.
 The data is specified within Instruction (OPCODE) itself.
 Generally, the implied addressing mode instruction is a 1-byte instruction.
 The data is supposed to be present generally in the accumulator.

Examples:
Instruction Comment
CMA ; Complement Accumulator. The CMA instruction complements (flips)
all the bits in the accumulator. It changes 0s to 1s and 1s to 0s.
RAL ; Rotate Accumulator Left through Carry. The RAL instruction rotates
the bits in the accumulator to the left through the carry flag. The carry
flag is shifted into the least significant bit (LSB), and the LSB is shifted
into the carry flag.
NOP : This instruction does nothing and is used for creating delays in a
program.

2.3. INSTRUCTION & INSTRUCTION FORMAT:

INSTRUCTION
 An instruction is a command to the microprocessor to perform a specific operation.
 Each Instruction has two parts
i. OPCODE (operation code): Operation or Task to be performed.
ii. OPERAND: The data to be operated

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
INSTRUCTION FORMAT:
OPCODE OPERAND1, OPERAND 2
 Each instruction has two parts: one is task to be performed, called the operation code
(opcode), and the second is the data to be operated on, called the operand. It may
have more than operand.
 The operand (or data) can be specified in various ways. It may include 8-bit or 16-bit
data, an internal register, a memory location, or 8-bit or 16-bit address. In some
instructions, the operand is implicit.

INSTRUCTION WORD SIZE IN 8085:

The 8085-instruction set is classified into three groups based on the size of the instruction
 One-word or 1-byte instructions
 Two-word or 2-byte instructions
 Three-word or 3-byte instructions
Examples:
1 Byte Instruction 2 Byte Instruction 3 Byte Instruction
NOP LDA 2050H LHLD 3050H
HLT MVI A, 3CH STA 4090H
DI INR D LXI H, 3050H

CLASSIFICATION OF INSTRUCTIONs:
These instructions can be classified into five different groups:
1. Data Transfer Group
2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. I/O and Machine Control Group

1. DATA TRANSFER GROUP INSTRUCTIONS:

 These operations simply COPY the data from the source to the destination.
 The data in the source is not changed.
 Data transfer instructions do not affect the flags.
(Examples: MOV, MVI, LDA, STA etc.)
Example:
 The "MOV" (move) instruction is a common data transfer instruction. It transfers data
from one location to another, such as from memory to a register or between registers.
Note:
They transfer:
 Data between registers.
 Data Byte to a register or memory location.
 Data between a memory location and a register.
 Data between an I\O Device and the accumulator.

2. ARITHMETIC GROUP INSTRUCTIONS:

Instructions in this group perform various mathematical operations, including addition,
subtraction, multiplication, and division. They manipulate numerical data and perform
arithmetic calculations.
Example:
 The "ADD B" instruction adds the contents of B register with Accumulator and the result
is stored in the accumulator.

3. LOGICAL GROUP INSTRUCTIONS:

Logical group instructions perform logical operations on data stored in the accumulator (A) and
sometimes other registers. These instructions are used to perform logical AND, OR, XOR,
complement (NOT), and rotate operations.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Example:
 The "AND" instruction performs a bitwise AND operation on two operands, setting the
result to 1 in each bit position where both operands have a 1.

4. BRANCH GROUP INSTRUCTIONS:

Instructions in this group control program flow by allowing conditional or unconditional
branching. They determine the sequence in which instructions are executed based on certain
conditions or jump to specific locations in the program.
Example:
 The "JUMP IF ZERO" instruction checks if a specific condition (e.g., the result of a previous
calculation is zero) is met. If true, it branches to a specified address; otherwise, it
continues to the next instruction.

5. I/O MACHINE GROUP INSTRUCTIONS:

These instructions manage input and output operations, as well as control various machine-level
functions. They are responsible for interacting with external devices and controlling the
computer's hardware.
Example:
 Input/output instructions may include commands to read data from a keyboard or write
data to a display.
 Machine control instructions can include commands to reset the computer or put it in a
specific power-saving mode.

SYMBOLS & ABBREVIATIONS

A Accumulator
A, B, C, D, E, H, L 8-bit register
H-L Register Pair H-L
B-C Register Pair B-C
D-E Register Pair D-E
PSW Program Status Word (Flags)
M Memory whose address is in H-L pair
H 2000 H indicates the hexadecimal number (It is not a register).
16-bit Program counter, PCH is the higher order 8-bit and PCL is the lower
PC
order 8-bits of register PC.
C Carry flag
addr 16-bit address of the memory location
data 8-bit data available in the instruction.
data 16 16-bit data available in the instruction.
Rs Source register
Rd Destination register
Register Pair
B represents B-C pair; B is higher order register & C is lower order
register.
D represents D-E pair; D is higher order register & E is lower order
rp register.
H represents H-L pair; H is higher order register & L is lower order
register.
SP represents 16-bit stack pointer; SPH is higher order 8-bits & SPL is
lower order 8-bits of register SP.
rh The higher order register of a register pair
rl The lower order register of a register pair
() The content of a register identified within the bracket.
The content of the memory location whose address is in the register pair
(( ))
identified within brackets.
Exchange contents

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
^ or . (dot) AND operation
ᵛ OR Operation
⊕ EXCLUSIVE OR Operation
H at the end of an instruction, it indicates that the number is in
H
hexadecimal (base-16) notation.

2.3.1. DATA TRANSFER INSTRUCTIONS

Note: XX is unknown value

affected

Bytes
Flags
Syntax Operation Description Example

MOV A, B
Move or copy the content of source
Move or copy
register B to destination register A.
the content of
source register

None
MOV Rd, Rs (Rd)  (Rs) Before Execution: 1
Rs to
Let A = XX H & B = 04 H
destination
After Execution:
register Rd.
A = 04 H & B = 04 H

MOV M, B
Move or copy Move or copy the content of source
the content of register B to destination memory
source register location pointed by register M
Rs to (H-L).

None
MOV M, Rs (M)  (Rs) destination Before Execution: 1
memory Let M (H-L) = 3000 H &
location pointed B = 04 H
by register M 3000 H = XX
(H-L). After Execution:
3000 H = 04 H & B = 04 H
MOV B, M
Move or copy the content of the
Move or copy memory location pointed by
the content of register M (H-L) to destination
the memory register B.
location pointed Before Execution:
None

MOV Rd, M (Rd)  (M) by register pair Let M (H-L) = 3000 H & 1
M 3000 H = 55 H
(H-L) to B = XX
destination
register Rd. After Execution:
B= 55H & 3000 H = 55 H

MVI A, 55 H
Move 8-bit immediate data 55 H to
Move 8-bit
the destination register A
immediate data
None

MVI Rd, 8-bit (A)  8-bit data to the 2

Before Execution:
destination
Let A = XX H & B = 04 H
register
After Execution:
A = 04 H & B = 04 H

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
MVI M, 55 H
Move 8-bit immediate data 55 H to
Move 8-bit the memory location pointed by
immediate data register M (H-L)
to the memory
location pointed Before Execution:

None
MVI M, data M  8-bit data 1
by register M Let M (H-L) = 3000 H
(H-L) 3000 H = XX
55 H is 8-bit data

After Execution:
3000 H = 55 H

affected

Bytes
Flags
Syntax Operation Description Example

The contents of
a memory
LDA 3000 H
location,
The contents of a memory location,
specified by a
3000 H, is copied to the accumulator
16-bit address
LDA 16-bit in the operand,
Before Execution:
address is copied to the
Let M (H-L) = 3000 H
A  (16-bit accumulator.

None
3000 H = 55 H 3
(Load address) or
A = XX
Accumulator Load the
Directly) content (8-bit
After Execution:
data) of the
A = 55
specified
3000 H = 55 H
memory
location into
accumulator.
LDAX B
Load the accumulator (A) with the
contents of the memory location
Load the pointed to by the register pair B-C
accumulator (A)
with the Before Execution:
contents of the Let B (B-C) = 3000 H None
LDAX rp A  (rp) 1
memory B=30 H & C=00 H
location pointed 3000 H = 55 H
to by the A = XX
register pair
After Execution:
A = 55
3000 H = 55 H
LXI H, 3000 H
Loads the HL register pair with the
16-bit hexadecimal value 3000H.
LXI rp, 16-bit
data Loads 16-bit Before Execution:
data in the Let H (H-L) = XXXX
(rp)  16-bit
None

Load Register specified H=XX H & L=XX H 3

data
Pair register pair
Immediate (B or D or H) After Execution:
H-L = 3000 H
H = 30 H (the high byte of 3000H)
L = 00 H (the low byte of 3000H)

LHLD 16-bit Load the LHLD 3000 H

address (L)  (16-bit content of the Load the content of the memory
address) memory location 3000 H into register L and
None

3
Load HL pair location into the content of the next memory
to the content (H)  (16-bit register L and location 3001 H is loaded into
of the address address + 1 i.e. the content of register H

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
next memory the next
location) memory Before Execution:
location is Let 3000 H = 11 H
loaded into 3001 H = 22 H
register H L = XX & H = XX i.e. HL = XXXX

After Execution:
3000 H = 11 H
3001 H = 22 H
L = 11 H & H = 22 H
i.e. HL = 2211 H

affected

Bytes
Flags
Syntax Operation Description Example

SHLD 3000 H
Stores the contents of the HL
register pair into the memory
Stores the locations
contents of the i.e. content of L register in 3000 H
HL register pair and the content of H register in
into the 3001 H.
memory
SHLD 16-bit locations Before Execution:

None
(address)  (L)
3
address (address+ 1)  (H) i.e. content of L Let 3000 H = XX
register in 3001 H = XX
address and the L = 11 & H = 22 i.e. HL = 2211 H
content of H
register in After Execution:
address +1. 3000 H = 11 H
3001 H = 22 H
HL = 2211 H

STA 3000 H
The content of the accumulator is
STA 16-bit stored in the memory location
The content of
address 3000 H.
the accumulator
Before Execution:
is stored in the
Let 3000 H = XX
None
(address)  (A) memory 3
Store A = 55 H
location
accumulator
specified in the
content to After Execution:
instruction.
direct address 3000 H = 55 H
A = 55 H

Store the STAX B

contents of the Store the contents of the
accumulator (A) accumulator (A) in the memory
in the memory location whose address is in the
location whose register pair B-C
STAX rp
address is in the
register pair Before Execution:
None

Store ((rp))  (a) 1

Let B=30 H & C= 00 H
accumulator
The "rp" can be i.e. BC = 3000 H
indirect
one of the A = 55 H
following 3000 H = XX
register pairs:
BC & DE After Execution:
3000 H = 55 H
The contents of XCHG
XCHG (H) (D) H-L pair are The contents of H-L pair are
None

exchanged with exchanged with the contents of 1

Exchange the (L) (E) the contents of D-E pair.
content of H
D-E pair. Before Execution:

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
and L with D Let H = 11 H & L = 22 H
and E pair i.e. H-L = 1122 H

Let D = 33 H & E = 44 H
i.e. D-E = 3344 H &

After Execution:
H = 33 H & L = 44 H
i.e. H-L = 3344 H
D = 11 H & E = 22 H
i.e. D-E = 1122 H

2.3.2. ARITHMETIC GROUP

affected
Bytes
Flags
Syntax Operation Description Example

ADD B
Before Execution:
Let A = 9A H
B = 89 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0

Execution:
The contents of
9A H= 1001 1010
register are
89 H= 1000 1001
added to the

All Flags
23 H= 0010 0011
A  (A) + contents of
ADD R 1
(Reg) accumulator.
After Execution:
The result is
A = 23 H
stored in
B = 89 H
accumulator.
Flag: S=0, Z=0, AC=1, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADD M

Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0

Memory
24FF H 75 H
The contents of
2500 H 08 H
memory are
2501 H 21 H
added to the
All Flags

2502 H 13 H
A  (A)+ contents of
ADD M 1
(Memory) accumulator.
The result is Execution:
stored in 20 H= 0010 0000
accumulator. 08 H= 0000 1000
28 H= 0010 1000

After Execution:
A = 28 H
HL = 2500 H

Flag: S=0, Z=0, AC=0, P=1, and CY=0

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

ADI B2 H
Before Execution:
Let A = C4 H
Immediate Data = B2 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0

The 8-bit Execution:

immediate data is C4 H= 1100 0100
added to the B2 H= 1011 0010

All Flags
A  (A)+ 8-bit contents of 76 H= 0111 0110
ADI 8-bit 2
Data accumulator.
The result is
stored in After Execution:
accumulator. A = 76 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADC B
Before Execution:
Let A = 9A H
B = 89 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

The contents of Execution:

register and 9A H= 1001 1010
Carry Flag (CY) 89 H= 1000 1001
All Flags

are added to the CY 1

A  (A)+
ADC R contents of 24 H= 0010 0100
1

(Reg)+(CY)
accumulator.
The result is
stored in After Execution:
accumulator. A = 24 H
B = 89 H
Flag: S=0, Z=0, AC=1, P=1, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADC M
The contents of Before Execution:
memory and Let A = 20 H
Carry Flag (CY) HL = 2500 H
All Flags

A  (A)+ are added to the Flag: S=0, Z=0, AC=0, P=0, and CY=1
ADC M (Memory)+(CY contents of
1

) accumulator. Memory
The result is 24FF H 75 H
stored in 2500 H 08 H
accumulator. 2501 H 21 H
2502 H 13 H

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Execution:
20 H= 0010 0000
08 H= 0000 1000
CY 1
29 H= 0010 1001

After Execution:
A = 29 H
HL = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

ACI B2 H

Before Execution:
Let A = C4 H
Immediate Data = B2 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

The 8-bit Execution:

immediate data C4 H= 1100 0100
and the Carry B2 H= 1011 0010
Flag (CY) are CY 1

All Flags
A  (A)+ 8- added to the 77 H= 0111 0111
ACI 8-bit

2
bits Data+(CY) contents of
accumulator.
The result is After Execution:
stored in A = 77 H
accumulator.
Flag: S=0, Z=0, AC=0, P=1, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

DAD B

Before Execution:
The 16-bit
Let HL = 2233 H
contents of the
BC = 1122 H
register pair are
Flag: CY=1
Carry Flag

added to the
HL  (Reg.
DAD Rp contents of H-L
1

Pair) +(HL) Execution:

pair.
2233 H
The result is
1122 H
stored in H-L
3355 H
pair.
After Execution:
HL = 3355 H
BC = 1122 H

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Flag: CY=0

Note: NO flags are affected except

carry flag.

SUB B
Before Execution:
Let A = 9A H
B = 89 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0
The contents of
Execution:
the register are
9A H= 1001 1010
subtracted from

All Flags
89 H= 1000 1001
the contents of
SUB R A  (A)- (R) 11 H= 0001 0001

1
the accumulator.
The result is
After Execution:
stored in
A = 11 H
accumulator.
B = 89 H
Flag: S=0, Z=0, AC=0, P=1, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

SUB M
Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

The contents of Execution:

the memory 20 H= 0010 0000
location are 08 H= 0000 1000
All Flags

subtracted from 18 H= 0001 1000

SUB M A  (A)- (M) the contents of
1

the accumulator.
The result is After Execution:
stored in A = 18 H
accumulator. HL = 2500 H

Flag: S=0, Z=0, AC=1, P=1, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

SUI 13 H
All Flags

The 8-bit
A  (A)- 8 bits Before Execution:
SUI 8-bit immediate data is
2

Data Let A = 05 H
subtracted from
Immediate data= 13 H

Page | 47
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
the contents of Flag: S=0, Z=0, AC=0, P=0, and CY=0
the accumulator.
The result is Execution:
stored in 05 H= 0000 0101
accumulator. 13 H= 0001 0011
F2 H= 1111 0010

After Execution:
A = F2 H

Flag: S=1, Z=0, AC=0, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

SBB B
Before Execution:
Let A = 25 H
B = 13 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1
The contents of
the register and Execution:
Borrow Flag (i.e. 25 H= 0010 0101
CY) are 13 H= 0001 0011

All Flags
A  (A)- (R)- subtracted from CY 1
SBB R

1
(CY) the contents of 11 H= 0001 0001
the accumulator.
The result is After Execution:
stored in A = 11 H
accumulator.
Flag: S=0, Z=0, AC=0, P=1, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

SBB M
Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H 75 H
2500 H 08 H
The contents of 2501 H 21 H
the memory 2502 H 13 H
location and
Borrow Flag (i.e. Execution:
All Flags

CY) are 20 H= 0010 0000

A  (A)- (M)-
SBB M subtracted from 08 H= 0000 1000
1

(CY)
the contents of CY 1
the accumulator. 17 H= 0001 0111
The result is
stored in
accumulator. After Execution:
A = 17 H
HL = 2500 H

Flag: S=0, Z=0, AC=1, P=1, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H

Page | 48
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

SBI 13 H
Before Execution:
Let A = 18 H
Immediate data= 13 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1
The 8-bit
immediate data Execution:
and the Borrow 18 H= 0001 1000
Flag (i.e. CY) is 13 H= 0001 0011

All Flags
A  (A)- 8 bits subtracted from CY 1
SBI 8-bits

2
data -(CY) the contents of F2 H= 0000 0100
the accumulator.
The result is After Execution:
stored in A = 04 H
accumulator.
Flag: S=0, Z=0, AC=0, P=0, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

INR E
Before Execution:
Let E = 1C H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

All flags, except Cy flag

Execution:
The contents of 1C H= 0001 1100
register are + 1
incremented by 1. 1D H= 0001 1101
INR R R  (R)+ 1

1
The result is
stored in the After Execution:
same place. E= 1D H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
INR M
Before Execution:
Let HL = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

All flags, except Cy flag

The contents of Memory

memory location 24FF H XX H
are incremented 2500 H 1C H
INR M M  (M)+ 1 by 1. 2501 H XX H
1

The result is 2502 H XX H

stored in the
same place. Execution:
1C H= 0001 1100
+ 1
1D H= 0001 1101

After Execution:
HL= 2500 H

Page | 49
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Memory
24FF H XX H
2500 H 1D H
2501 H XX H
2502 H XX H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
INX B
Before Execution:
Let BC = 2050 H

Execution:
The contents of 2050 H= 0010 0000 0101 0000
the designated + 1
register pair are 2051 H= 0010 0000 0101 0001

None
INX Rp Rp  (Rp)+ 1 incremented by 1

1
and their result is After Execution:
stored at the BC= 2051 H
same place.
Flag: S=0, Z=0, AC=0, P=1, and CY=NO
CHANGE

Note: Flag bits are not at all affected

by the execution of this instruction.
DCR B
Before Execution:
Let B = 1C H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

All flags, except Cy flag

Execution:
The contents of
1C H= 0001 1100
the designated
- 1
register are
1B H= 0001 1011
DCR R R  (R)- 1 decremented by 1
1
and their result is
After Execution:
stored at the
B= 1B H
same place.
Flag: S=0, Z=0, AC=0, P=1, and CY=NO
CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
DCR M
Before Execution:
Let HL = 2500 H
All flags, except Cy flag

The contents of Flag: S=0, Z=0, AC=0, P=0, and CY=1

the designated
memory are Memory
DCR M M  (M)- 1 decremented by 1
1

24FF H XX H
and their result is
2500 H 1C H
stored at the
2501 H XX H
same place.
2502 H XX H

Execution:
1C H= 0001 1100

Page | 50
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
- 1
1B H= 0001 1011

After Execution:
HL= 2500 H

Memory
24FF H XX H
2500 H 1B H
2501 H XX H
2502 H XX H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
DCX B
Before Execution:
Let BC = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

The contents of Execution:

the designated 2500 H= 0010 0101 0000 0000
register pair are - 1

None
DCX Rp Rp  (Rp)- 1 decremented by 1 24FF H= 0010 0100 1111 1111

1
and their result is
stored at the After Execution:
same place. HL= 24FF H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: Flags are not at all affected by

the execution of this instruction
Description:
The contents of the accumulator are changed from a binary
value to two 4-bit binary-coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary flag (internally) to
perform the binary-to-BCD conversion; the conversion
procedure is described below.
Instruction DAA converts the binary contents of the
accumulator as follows:
1 If the value of the low-order four bits
(𝐷3 − 𝐷0 ) in the accumulator is greater than 9 or if AC flag
is set, the instruction adds 6(06) to the low-order four bits.
DAA 2 If the value of the high-order four bits
A (BCD Value) (𝐷7 − 𝐷4 ) in the accumulator is greater than 9 or if the
(Decimal Carry flag is set, the instruction adds 6(60) to the high-
ALL

 A(Binary
1

adjust order four bits.

Value)
accumulator
) Example:
ADD decimal number 13 to the accumulator, which
contains 38
In In
Decimal Hex
3 8 38
+ 1 3 + 13
5 1 4B H

Page | 51
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
D7 D6 D5 D4 D3 D2 D1 D0
1 1

A 3 8 = 0 0 1 1 1 0 0 0
+ 1 3 = 0 0 0 1 0 0 1 1
4 B = 0 1 0 0 1 0 1 1
Result in Accumulator is 4B H and not an BCD.

The result, initially 4BH, is not in BCD format. After applying

the DAA instruction, the value of the lower-order four bits is
greater than 9, we add 6H to those bits to ensure the result is
in proper BCD format

D7

D6

D5

D4

D3

D2

D1

D0
1 1 1

A 4 B = 0 1 0 0 1 0 1 1
+ 0 6 = 0 0 0 0 0 1 1 0
A 5 1 = 0 1 0 1 0 0 0 1
Result in Accumulator is BCD 51.

2.3.3. LOGICAL GROUP

affected
Bytes
Flags
Syntax Operation Description Example

(A)  (A) ^ ANA B

(r) Performs a logical AND operation between
ANA r
the contents of A and the B register, and the
performs a
Note: result is stored back in accumulator A.
bitwise AND
AND symbol
operation
^ Before Execution:
between the ALL
A = 55 H
ANA r binary values in
B = 65 H
the accumulator (Z,
AND (A) and the S,
Where "r" After Execution: 1
register specified P,
can be any of A = 41 H
with register (r) & CY
the following B = 65 H
accumulator the result is &
registers:
stored back in AC)
B, C, D, E, H,
the
L or M
accumulator.
(Indirect
addressing
using the HL
pair)
Perform a ANA M
logical AND
operation Before Execution:
between the A = 55 H
contents of the M = HL = 3000 H ALL
ANA M accumulator (A) 3000 = 65 H
and the data (Z,
(A) (A)
AND stored in the After Execution: S,
^ (M) 1
memory memory A = 41 H P,
with location pointed 3000 = 65 H CY
accumulator to by the HL &
register pair & AC)
the result is
stored back in
the
accumulator.

Page | 52
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Perform a ANI 3C H
logical AND ALL
ANI 8-bit data operation Before Execution:
between the A = A7 H (Z,
(A) (A) ^
AND accumulator (A) data  3C H S,
(data) 1
immediate and an 8-bit P,
data with data value & the After Execution: CY
accumulator result is stored A = 24 H &
back in the AC)
accumulator.
(A) (A) ORA B
v (r) Performs a logical OR operation between the
contents of A and the B register, and the
ORA r
Note: result is stored back in accumulator A.
performs a
OR symbol
bitwise OR
ᴠ Before Execution:
operation ALL
A = 55 H
between the
ORA r B = 65 H
binary values in (Z,
the accumulator S,
OR register Where "r" After Execution: 1
(A) and the P,
with can be any of A = 75 H
specified CY
accumulator the following B = 65 H
register (r) & &
registers:
the result is AC)
B, C, D, E, H,
stored back in
L or M
the
(Indirect
accumulator.
addressing
using the HL
pair)

affected
Bytes
Flags
Syntax Operation Description Example

Perform a ORA M
logical OR
operation Before Execution:
between the A = 55 H
contents of the M = HL = 3000 H ALL
accumulator (A) 3000 = 65 H
ORA M
and the data (Z,
(A) (A)
stored in the After Execution: S,
OR memory v (M) 1
memory A = 75 H P,
with
location pointed 3000 = 65 H CY
accumulator
to by the HL &
register pair & AC)
the result is
stored back in
the
accumulator.
Perform a ORI 65 H
logical OR ALL
ORI 8-bit data operation Before Execution:
between the A = 55 H (Z,
(A) (A) v
OR accumulator (A) data  65 H S,
(data) 1
immediate and an 8-bit P,
data with data value & the After Execution: CY
accumulator result is stored A = 75 H &
back in the AC)
accumulator.
XRA r (A) (A) ⊕ XRA r XRA B ALL
(r) performs a Performs a logical EX-OR operation between
EX-OR bitwise EX-OR the contents of A and the B register, and the (Z,
1
register Note: operation result is stored back in accumulator A. S,
with EX-OR symbol between the P,
accumulator ⊕ binary values in Before Execution: CY

Page | 53
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
the accumulator A = 55 H &
(A) and the B = 65 H AC)
specified
Where "r" register (r) & After Execution:
can be any of the result is A = 30 H
the following stored back in B = 65 H
registers: the
B, C, D, E, accumulator.
H, L or M
(Indirect
addressing
using the
HL pair)
XRA M XRA M
perform a
bitwise XOR Before Execution:
(exclusive OR) A = 55 H
operation M = HL = 3000 H
(A) (A) ⊕ between the 3000 = 65 H
(M) contents of the ALL
XRA M accumulator (A) After Execution:
Note: and the data A = 30 H (Z,
EX-OR EX-OR symbol stored in the 3000 = 65 H S,
1
memory ⊕ memory P,
with location pointed CY
accumulator to by the HL &
register pair AC)
(indirect
addressing) &
the result is
stored back in
the
accumulator.
XRI 8-bit data XRI 65 H
perform a
logical XOR Before Execution:
(exclusive OR) A = 55 H ALL
(A) (A) ⊕ 8- operation
bit data between the After Execution: (Z,
contents of the A = 30 H S,
XRI 8-bit data 1
Note: accumulator (A) P,
EX-OR symbol and an 8-bit CY
⊕ immediate data &
value & the AC)
result is stored
back in the
accumulator.
CMA CMA
(Complement
Accumulator) Before Execution:
instruction is A = 0F H
used to perform
ALL
a bitwise After Execution:
CMA complement A = F0 H
(Z,
̅) (bitwise NOT)
(A)  (𝑨 S,
Complement operation on the 1
P,
the contents of the
CY
accumulator accumulator (A).
&
This means that
AC)
all the bits in the
accumulator are
inverted: 0s
become 1s, and
1s become 0s.

Page | 54
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CMC is used to CMC
complement Before Execution:
CMC (toggle) the CY = 0 (one bit)
state of the
(CY) 
Complement Carry Flag (CY) After Execution:
(̅̅̅̅
𝑪𝒀) CY 1
the carry bit in the status CY = 1 (one bit)
(CY) register.

Other flags are

not affected
CMP r CMP B
used to compare Before Execution:
the contents of A = 55 H
the accumulator B = 56 H
(A) with the
contents of a After Execution:
specified A = 55 H
register (r) B = 56 H
without ALL
actually Zero Flag (Z): Set if A = B
CMP r
changing the Sign Flag (S): Set if the result is negative (A < (Z,
(A) - (r) contents of the B). S,
Compare 1
accumulator. It Carry Flag (CY): Set if a borrow occurred P,
register with
sets the flags in during subtraction (A < B). CY
accumulator
the status Parity Flag (P): Set if the number of set bits &
register based in the result is even. AC)
on the result of Auxiliary Carry Flag (AC): Set if a borrow
the occurred from bit 4 to bit 3 during
comparison. subtraction.

The contents of
the A & r
remain
unchanged.
CMP M
Before Execution:
CMP M M (HL) = 3000 H
instruction is A = 55 H
used to compare 3000 H = 56 H
the contents of
the accumulator After Execution:
(A) with the A = 55 H ALL
data stored in 3000 = 56 H
CMP M
the memory (Z,
(A) - (M) location pointed S,
Compare 1
to by the HL Zero Flag (Z): Set if A = M P,
memory with
register pair Sign Flag (S): Set if the result is negative (A < CY
accumulator
(indirect M). &
addressing). Carry Flag (CY): Set if a borrow occurred AC)
during subtraction (A < M).
The contents of Parity Flag (P): Set if the number of set bits
the A & M in the result is even.
remain Auxiliary Carry Flag (AC): Set if a borrow
unchanged. occurred from bit 4 to bit 3 during
subtraction.

CPI 8-bit data CPI 56 H

ALL
Compare the Before Execution:
(Z,
contents of the (A) = 55 H
(A) - 8-bit S,
CPI 8-bit data accumulator (A) 8-bit data = 56 H 1
data P,
with an 8-bit
CY
immediate data After Execution:
&
value (8-bit A = 55 H
AC)
constant). It 3000 = 56 H

Page | 55
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
performs a CY = 1 (one Bit)
subtraction
between the Zero Flag (Z): Set if A = 8-bit data value.
accumulator and Sign Flag (S): Set if the result is negative (A <
the immediate data).
data value Carry Flag (CY): Set if a borrow occurred
without altering during subtraction (A < data).
the contents of Parity Flag (P): Set if the number of set bits
the accumulator. in the result is even.
Auxiliary Carry Flag (AC): Set if a borrow
occurred from bit 4 to bit 3 during
subtraction.

The contents of the accumulator and the Carry flag will be

updated as follows:

 Each binary bit of the accumulator is rotated left by one

position.
 Bit A7 (MSB) is placed in the position of A0 as well as in the
Carry flag.
 CY is modified according to bit A7.

Before Execution:
A = 55 H
CY = X ALL
RLC (CY)  A7
A7  A6 (Z,
Rotate A0  A7 S, 1
accumulator P,
left CY
&
AC)

After Execution:
A = AA H
CY = 0

The contents of the accumulator and the Carry flag will be

updated as follows:
ALL
RRC  Each binary bit of the accumulator is rotated right by one
(Z,
(CY)  A0 position.
S,
Rotate A7  A0  Bit A0 (LSB) is placed in the position of A7 as well as in the 1
P,
accumulator A6  A7 Carry flag.
CY
right  CY is modified according to bit A0.
&
AC)
Before Execution:
A = 55 H
CY = X

Page | 56
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

After Execution:
A = AA H
CY = 1

The contents of the accumulator and the Carry flag will be

updated as follows:
 Each binary bit of the accumulator is rotated left by one
position through the Carry flag.
 Bit A7 is placed in the Carry flag, and the Carry flag is placed
in the least significant position A0.
 CY is modified according to bit A7.
Before Execution:
A = 55 H
CY = 1 ALL
RAL
(Z,
CY  A7
S,
Rotate the A0  CY 1
P,
accumulator A1  A0
CY
left through
&
carry
After Execution: AC)
A = AB H
CY = 0

The contents of the accumulator and the Carry flag will be

updated as follows:
 Each binary bit of the accumulator is rotated right by one
position through the Carry flag.
 Bit A0 is placed in the Carry flag, and the Carry flag is placed
in the most significant position A7.
RAR ALL
 CY is modified according to bit A0.
Before Execution:
(Z,
CY  A0 A = 55 H
Rotate the S,
A7  CY CY = 0 1
accumulator P,
A0  A1
right through CY
carry &
AC)

After Execution:
A = 21 H
CY = 1

Page | 57
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

2.3.4. BRANCH CONTROL GROUP

Jump (Unconditional and Conditional)

affected

Bytes
Flags
Syntax Operation Description Example

JMP 2050
Before Execution:
2041 X
2042 JMP 2050
2045 X
. X
Transfers the 204F X
program 2050 X
Jumps to the sequence to 2051 X
JMP 16-Bit

None
address the described 3
Address
memory After Execution:
address. 2041 X
2042 JMP 2050
2045 X
. X
204F X
2050 X
2051 X

JC 2050
Before Execution:
2041 X
2042 JC 2050
2045 X
. X
204F X
If condition is
true address 2050 X
PC (Program 2051 X
JC 16-Bit Jump, if carry
None

Counter) 3
Address flag is set. After Execution:
If condition is
false PC  PC+3 2041 X If If
True False
2042 JC 2050
2045 X
. X
204F X
2050 X
2051 X
JNC 2050
If condition is Before Execution:
true address 2041 X
PC (Program Jump, if carry 2042 JNC 2050
JNC 16-Bit
None

Counter) flag is not set 2045 X 3

Address
If condition is (reset). . X
false PC  PC+3 204F X
2050 X
2051 X

Page | 58
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
After Execution:
2041 X If If
True False
2042 JNC 2050
2045 X
. X
204F X
2050 X
2051 X
JZ 2050
Before Execution:
2041 X
2042 JZ 2050
2045 X
. X
If condition is 204F X
true address 2050 X
PC (Program 2051 X
JZ 16-Bit Jump, if zero

None
Counter) 3
Address flag is set. After Execution:
If condition is
false PC  PC+3 2041 X If If
True False
2042 JZ 2050
2045 X
. X
204F X
2050 X
2051 X
JNZ 2050
Before Execution:
2041 X
2042 JNZ 2050
2045 X
. X
204F X
2050 X
2051 X

After Execution:
2041 X If If
True False
2042 JNZ 2050
If condition is
2045 X
JNZ 16-Bit true address
Jump, if zero . X
Address PC (Program
None

flag is not set 204F X 3

Counter)
(reset). 2050 X
If condition is
false PC  PC+3 2051 X

Page | 59
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
JP 2050
Before Execution:
2041 X
2042 JP 2050
2045 X
. X
If condition is 204F X
true address 2050 X
PC (Program Jump, if 2051 X
JP 16-Bit Counter) positive i.e. 3

None
Address If condition is sign flag is After Execution:
false PC  PC+3 reset. 2041 X If If
True False
2042 JP 2050
2045 X
. X
204F X
2050 X
2051 X

JM 2050
Before Execution:
2041 X
2042 JM 2050
2045 X
. X
204F X
If condition is
true address 2050 X
Jump, if 2051 X
PC (Program
JM 16-Bit minus i.e.

None
Counter) 3
Address sign flag is After Execution:
If condition is
set. 2041 X If If
false PC  PC+3
True False
2042 JM 2050
2045 X
. X
204F X
2050 X
2051 X
JPE 2050
Before Execution:
2041 X
2042 JPE 2050
2045 X
. X
204F X
If condition is 2050 X
true address 2051 X
Jump, if
PC (Program
JPE 16-Bit parity even
None

Counter) After Execution: 3

Address i.e. parity flag
If condition is 2041 X If If
is set.
false PC  PC+3 True False
2042 JPE 2050
2045 X
. X
204F X
2050 X
2051 X

Page | 60
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
JPO 2050
Before Execution:
2041 X
2042 JPO 2050
2045 X
. X
204F X
If condition is 2050 X
true address 2051 X
Jump, if
PC (Program
JPO 16-Bit parity odd i.e.

None
Counter) After Execution: 3
Address parity flag is
If condition is 2041 X If If
reset.
false PC  PC+3 True False
2042 JPO 2050
2045 X
. X
204F X
2050 X
2051 X

CALL (Unconditional and Conditional)

affected

Bytes
Flags
Syntax Operation Description Example

CALL 3050
Before Execution:
2041 X
2042 CALL
3050
2045 X
. X
Program 204F X
sequence Jumps 2050 X
This 2051 X
to the
instruction is SP=2573 H
subroutine
used to PC=2042 H
address
branch to the After Execution:
CALL 16-Bit subroutine
None

PC (Higher 2041 X Subroutine 3

Address whose 16-bit 2042 CALL 3050
byte) (SP-1)
address is 3050
PC (Lower
provided in 2045 X
byte) (SP-2)
the
(SP-2) SP . X
instruction.
16 Bit 204F X
AddressPC 2050 X
2051 X

SP-1=2572H=45H
SP-2=2571H=20H
SP=2571 H
PC=3050 H

Page | 61
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CC 3050
Before Execution:
2041 X
2042 CC 3050
2045 X
. X
If CY=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call 2042 CC
CC 16-Bit

None
byte) (SP-2) subroutine if 3050 3050 3
Address (SP-2) SP carry status
2045 X (If True
16 Bit CY=1 CY=1)
. X
AddressPC 204F X
If CY=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program CY=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
CY=0 SP=2573 H

CNC 3050
Before Execution:
2041 X
2042 CNC 3050
2045 X
. X
204F X
If CY=0,
2050 X
Program
2051 X
sequence Jumps
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call 2042 CNC
CNC 16-Bit 3050 3050
None

byte) (SP-2) subroutine if 3

Address (SP-2) SP carry status 2045 X (If True
16 Bit CY=0 . X CY=0)
AddressPC 204F X
If CY=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program CY=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
CY=1 SP=2573 H

Page | 62
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CZ 3050
Before Execution:
2041 X
2042 CZ 3050
2045 X
. X
If flag Z=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call 2042 CZ
CZ 16-Bit

None
byte) (SP-2) subroutine if 3050 3050 3
Address (SP-2) SP zero status 2045 X (If True
16 Bit flag Z=1 . X Z=1)
AddressPC 204F X
If flag Z=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program Z=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
Z=0 SP=2573 H

CNZ 3050
Before Execution:
2041 X
2042 CNZ 3050
2045 X
. X
If flag Z=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call
2042 CNZ
CNZ 16-Bit
None

byte) (SP-2) subroutine if

3050 3050 3
Address (SP-2) SP Zero status
2045 X (If True
16 Bit flag Z=0
. X Z=0)
AddressPC 204F X
If flag Z=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program Z=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
Z=1 SP=2573 H

Page | 63
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CP 3050
Before Execution:
2041 X
2042 CP 3050
2045 X
. X
204F X
If flag S=0,
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call 2042 CP
CP 16-Bit

None
byte) (SP-2) subroutine if 3050 3050 3
Address (SP-2) SP sign status 2045 X (If True
16 Bit flag S=0 . X S=0)
AddressPC 204F X
If flag S=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program S=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
S=1 SP=2573 H

CM 3050
Before Execution:
2041 X
2042 CM 3050
2045 X
. X
If flag S=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call
2042 CM
CM 16-Bit
None

byte) (SP-2) subroutine if 3

3050 3050
Address (SP-2) SP sign status
2045 X (If True
16 Bit flag S=1
. X S=1)
AddressPC 204F X
If flag S=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program S=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
S=0 SP=2573 H

Page | 64
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CPE 3050
Before Execution:
2041 X
2042 CPE 3050
2045 X
. X
If flag P=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call
2042 CPE
CPE 16-Bit

None
byte) (SP-2) subroutine if 3
3050 3050
Address (SP-2) SP parity status
2045 X (If True
16 Bit flag P=1
. X P=1)
AddressPC 204F X
If flag P=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program P=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
P=0 SP=2573 H

CP0 3050
Before Execution:
2041 X
2042 CPO 3050
2045 X
. X
If flag P=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte) (SP-1) Subroutine
PC (Lower Call
2042 CPO
CPO 16-Bit
None

byte) (SP-2) subroutine if 3

3050 3050
Address (SP-2) SP parity status
2045 X (If True
16 Bit flag P=0
. X P=0)
AddressPC 204F X
If flag P=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program P=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
P=1 SP=2573 H

Page | 65
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Return (unconditional and conditional)

affected

Bytes
Flags
Syntax Operation Description Example

The program
sequence is RET
transferred
from the Before Execution:
subroutine to
RET stands for
the calling If SP=2095H
return from the
program. Memory
subroutine.
2095 50
The two bytes 2096 20
PC (Lower

None
RET from the top 1
byte) (SP)
of stack are PC=XXXX H
PC (Higher
copied into After Execution:
byte) (SP+1)
the program
SP SP+2
counter and PC=2050 H
the program SP=2097 H
counter
execution
begins at the
new address.
RC
If condition Before Execution:
(CY=1) is If SP=2095H
true, it Memory
returns to the 2095 50
calling
2096 20
program

None
RC Return on Carry 1
PC=3000 H
If condition
After Execution:
(CY!=1) is not
IF CY=1 IF CY=0
true, it
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

RNC
If condition Before Execution:
(CY=0) is If SP=2095H
true, it Memory
returns to the 2095 50
calling
2096 20
RNC Return with No program
None

1
Carry
PC=3000 H
If condition
After Execution:
(CY!=0) is not
IF CY=0 IF CY=1
true, it
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

If condition RP
(S=0) is true,
it returns to Before Execution:
the calling If SP=2095H
Return on
None

RP program Memory 1
positive
2095 50
If condition 2096 20
(S!=0) is not
true, it PC=3000 H

Page | 66
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
continues the After Execution:
sequence IF S=0 IF S=1
PC=2050 H PC=3000 H
SP=2097 H SP=2095 H

RM

If condition Before Execution:

(S=1) is true, If SP=2095H
it returns to Memory
the calling 2095 50
program 2096 20
Return on

None
RM 1
minus
If condition PC=3000 H
(S!=1) is not After Execution:
true, it IF S=1 IF S=0
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

RPE
If condition
(P=1) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
Return on Parity

None
RPE 2096 20 1
Even
If condition
(P!=1) is not PC=3000 H
true, it After Execution:
continues the IF P=1 IF P=0
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H
RPO
If condition
(P=0) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
Return on Parity
None

RPO 2096 20 1
Odd
If condition
(P!=0) is not PC=3000 H
true, it After Execution:
continues the IF P=0 IF P=1
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H
RZ
If condition
(Z=1) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
None

RZ Return on Zero 2096 20 1

If condition
(Z!=1) is not PC=3000 H
true, it After Execution:
continues the IF Z=1 IF Z=0
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H

Page | 67
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
RNZ

If condition Before Execution:

(Z=0) is true, If SP=2095H
it returns to Memory
the calling 2095 50
program 2096 20
Return on NO

None
RNZ 1
Zero
If condition PC=3000 H
(Z!=0) is not After Execution:
true, it IF Z=0 IF Z=1
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

2.3.5. STACK, I/O and MACHINE CONTROL GROUP

affected
Bytes
Flags
Syntax Operation Description Example

Example 1:
PUSH B

Before Execution:
Let SP = 3000 H
Push the B = 55 H
content of C = 66 H
register pair rp
((SP-1))  (rh) to stack After Execution:
((SP-2))  (rl) ((SP-1))  (B)
((SP-2))  (C)
(SP)  (SP)-2 The stack
PUSH rp pointer register (SP)  (SP)-2
is decremented
The "rp" can be and the contents 2FFF = 55 H
one of the of the high order 2FFE = 66 H
Push the following register register (B, D, H, SP = 2FFD H
content of pairs: A) are copied None 1
register into that Example 2:
pair rp to BC location. The PUSH PSW
stack DE stack pointer
HL register is Before Execution:
PSW (Program decremented Let SP = 3000 H
Status Word, again and the A = 77 H
which includes contents of PSW = 88 H
the accumulator the low-order
and flags) register (C, E, L, After Execution:
flags) are copied ((SP-1))  (A)
to that ((SP-2))  (PSW)
location.
(SP)  (SP)-2

2FFF = 77 H
2FFE = 88 H
SP = 2FFD H

Page | 68
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Example 1:
POP B

Before Execution:
Let SP = 3000 H
3000 = 55 H
3001 = 66 H

B = XX H
The contents of C = XX H
(rl)  ((SP)) the memory
(rh)  ((SP+1)) location pointed After Execution:
out by the stack (rl)  ((3000))
(SP)  (SP)+2 pointer register (rh)  ((3000 + 1))
is copied to the
low-order (SP)  (3000) +2
POP (retrieve) a register (C, E, L,
POP rp 16-bit value from status flags) of C = 55 H
the stack and load the operand. B = 66 H
it into the The stack BC = 6655 H
POP specified register pointer is SP = 3002 H
(retrieve) a pairs (rp). The incremented

None
1
16-bit value "rp" can be one of by 1 and the
from the the following contents of that
stack and register pairs: memory Example 2:
load it into location are POP PSW
rp BC copied to
DE the high-order Before Execution:
HL register (B, D, H, Let SP = 3000 H
PSW (Program A) of the 3000 = 55 H
Status Word, operand. The 3001 = 66 H
which includes stack
the accumulator pointer register PSW = XX H
and flags) is again A = XX H
incremented by
1. After Execution:
(PSW)  ((3000))
(A)  ((3000 + 1))

(SP)  (3000) +2

PSW = 55 H
A = 66 H
SP = 3002 H
SPHL
Copy H and L SPHL
Copy H and
None

(SP) (HL) registers to the The value stored in the HL register pair 1
L registers
stack pointer. is copied into the stack pointer (SP).
to the stack
pointer
XTHL
The contents of the L register are
exchanged with the stack
Exchange the
(L) (SP) location pointed out by the contents of
values of the HL
the stack pointer
None

XTHL register pair 1

(H) (SP+1) register. The contents of the H register
with the stack's
are exchanged with
top two bytes.
the next stack location (SP+1); however,
the contents of the
stack pointer register is not altered.
IN Port Example:
(A)  (Port IN instruction
address
address reads data from
None

2
Input ) the specified
IN 10 H
accumulato input port and

Page | 69
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
r from I/O Port address is loads it into the IN instruction reads data from the input
Port the 8-bit accumulator (A). port with an address of 10H and stores
immediate value the data in the accumulator (A)
that represents
the address of
the input port
from which data
is to be read.
(Port address)
(A)
OUT instruction
OUT Port
sends the data Example:
address Port address" is
stored in the OUT 20 H
the 8-bit
accumulator to

None
Output from immediate value 2
accumulator the output port OUT instruction sends the data stored in
that represents
to I/O Port address the accumulator to the output port with
the address of
specified in the an address of 20H.
the output port
instruction
to which data is
to be sent
EI
Enable Interrupt used to enable interrupts in the 8085 microprocessor except

None
the TRAP interrupt. When interrupts are enabled using the "EI" instruction, the 1
Enable
microprocessor will respond to interrupt requests from external devices.
Interrupts
DI Disable Interrupt is used to disable interrupts in the 8085 microprocessor
temporarily except the TRAP interrupt. When interrupts are disabled using the

None
1
Disable "DI" instruction, the microprocessor will not respond to interrupt requests
Interrupts from external devices.
This is a
multipurpose
instruction used
to read the status
of
interrupts 7.5,
RIM
6.5, 5.5 and read
serial data input

None
Read 1
bit. The
Interrupt
instruction loads
Mask
eight bits in the
accumulator with
the
following Figure 1
interpretations as
shown in figure 1
This is a
multipurpose
instruction and
used to
implement the
SIM
8085 interrupts
7.5, 6.5, 5.5, and
None

Set 1
serial data
Interrupt
output. The
Mask
instruction
interprets the
accumulator
contents as
shown in figure 2 Figure 2
NOP
No operation is performed when this instruction is executed. The registers and
None

flags and memory remain unaffected. The purpose of the "NOP" instruction is to 1
No
provide a delay.
operation
"Halt" is used to halt or stops the execution of the microprocessor and put it into
HLT a halt state. When the microprocessor is in a halt state, it stops fetching and
None

1
executing instructions until it is reset or interrupted.
NOTE:

Page | 70
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Halt and The "HLT" instruction is often used to save power when the microprocessor is
enter wait not actively performing tasks and needs to wait for external events or interrupts
state to resume processing.

Page | 71
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

UNIT
16-bit Microprocessor and
Peripheral devices
SYLLABUS
16-bit Microprocessors (8086): Architecture, Pin Description, Physical address, Segmentation,
Addressing modes.
Peripheral Devices: 8237 DMA Controller, 8255 Programmable Peripheral Interface,
8253/8254 Programmable Timer/Counter, 8259 Programmable Interrupt Controller, 8251
USART and RS 232C.
16-BIT MICROPROCESSOR
3.1 Introduction to 16-bit Microprocessor 8086

 The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late

1970s.
 The architecture of the 8086 microprocessor is based on a complex instruction set
computer (CISC) architecture, which means that it supports a wide range of instructions,
many of which can perform multiple operations in a single instruction.

3.1.1 8086 Internal Architecture:

Draw the architecture of 8086 Microprocessors and explain its all blocks.
AKTU Question Paper 2022-23, 10 MARKS

Figure 3.1: 8086 Microprocessor Internal Architecture

Page | 72
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Figure 3.1 shows the 8086 Microprocessor internal architecture.
The 8086 microprocessor has two main execution units:
i. The Bus Interface Unit (BIU) and
ii. The Execution Unit (EU).
The BIU is responsible for fetching instructions from memory and decoding them, while the
EU executes the instructions. The BIU also manages data transfer between the
microprocessor and memory or I/O devices.

1. The Bus Interface Unit (BIU):

BIU performs the following functions:
 It generates the 20-bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, Instruction Queue, and an
Address Generation Circuit.
Memory Segmentation
Memory segmentation is the method where whole memory is divided into the smaller parts called
segments, and each segment can be up to 64 KB (kilobytes) in size. This segmentation allows the
processor to access a total of 1 MB (megabyte) of memory.
 DATA SEGMENT
 CODE SEGMENT
 STACK SEGMENT and
 EXTRA SEGMENT.
Each segment can be up to 64 KB (kilobytes) in size. Segment registers store starting address of
each segments in memory.

Maximum size of segment:

 All offsets are limited to 16-bits. It means that the maximum size possible for segment is
216= 65,535 bytes (64 KB).
 The offset of the first location within the segment is 0000 H. The offset of the last location
in the segment is FFFF H i.e. the address within each segment is ranging between 0000 H
to FFFF H (64 KB).

Segment Registers:
The 8086 has four primary segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment). Each of these registers holds a 16-bit value that represents
the base address of a specific segment in memory.
Code Segment (CS) register : CS is a 16 Bit register, holds the base address for the Code
(64 KB) Segment. All programs are stored in the Code Segment and
accessed via the IP.
Data Segment (DS) register : DS is a 16 Bit register, holds the base address for the Data
(64 KB) Segment.
Stack Segment register : SS is a 16 Bit register, holds the base address for the Stack
(64 KB) Segment.

Extra Segment register : ES is a 16 Bit register, holds the base address for the Extra
(64 KB) Segment.

Instruction Pointer (IP):

 It is a 16-bit special-purpose register.
 It points to the memory location of the next instruction to be executed.
 It is automatically incremented after each instruction fetch.
 IP gets a new value whenever a branch instruction occurs.

Page | 73
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
 The code segment (CS) is multiplied by 10H to give the 20-bit physical address of the Code
Segment.
 The address of the next instruction is calculated by using the formula CS x 10H + IP.

Investigate the need of pre-fetch instruction queue in 8086.

AKTU Question Paper 2021-22, 2 MARKS
Instruction Queue:
 It is a 6-byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
 Gets flushed whenever a branch instruction occurs.
 The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can
have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size
instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.

Address Generation Circuit:

 The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address
using Segment and Offset addresses using the formula:
 In Bus Interface Unit (BIU) the circuit shown by the symbol ‘Σ’ is responsible for the calculation
unit which is used to calculate the physical address of an instruction in memory.
Physical Address = (Segment Address x 10H) + Offset Address

Address Bus:
The 8086 microprocessor has a 20-bit address bus, which can address up to 1 MB of memory (220
= 1,048,576), and a 16-bit data bus, which can transfer 16-bit data between the microprocessor
and memory or I/O devices.

Data Bus:
The data bus is used to transfer data between the microprocessor and memory. The data bus is
16 bits wide, allowing the 8086 to transfer 16-bit data words at a time.

Control Bus: The control bus is used to transfer control signals between the microprocessor and
other components in the computer system. The control bus is used to send signals such as read,
write, and interrupt requests, and to transfer status information between the microprocessor and
other components.

The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers,
the Instruction Register and Instruction Decoder, and the Flag/Status Register.

The functional parts of EU are explained as below.

Arithmetic Logic Unit (ALU): The ALU is responsible for performing 8-bit and 16-bit arithmetic
and logical operations on data. It can handle operations such as addition, subtraction,
multiplication, division, bitwise AND, OR, XOR, and more.

General-Purpose Registers:
8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two 8-bit parts (higher and lower) i.e. AH, AL, BH, BL,
CH, CL, DH and DL to store 8-bit data.

AX register: (Combination of AL and AH Registers)

It holds operands and results during multiplication and division operations. Also, an accumulator
during String operations.
BX register: (Combination of BL and BH Registers)
It holds the memory address (offset address) in indirect addressing modes.

Page | 74
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
CX register: (Combination of CL and CH Registers)
It holds the count for instructions like a loop, rotates, shifts and string operations.
DX register: (Combination of DL and DH Registers)
It is used with AX to hold 32-bit values during multiplication and division

Index and Pointer registers:

 EU has two 16-bit index register and two 16-bit pointer registers designated as SI (Source
Index Register), DI (Destination Index Register), SP (Stack Pointer Register) and BP (Base
Pointer Register).
 SI is often used as an offset or index when accessing source data during string operations.
 DI serves as an offset or index for destination data during string operations.
 The SP register points to the top of the stack in memory. It's crucial for managing the stack,
including push and pop operations.
 BP serves as a base pointer in stack frame operations and is often used for accessing
parameters and local variables within functions.

Control Unit:
The Control Unit in the 8086 microprocessor is a component that manages the overall operation
of the microprocessor. It interprets the opcode of an instruction, determines the operation to be
performed, and generates control signals to execute that operation.

Instruction Decode:
 The EU decodes the instruction fetched from memory to understand what operation needs to
be performed and which operands to use.
 It works in parallel with the Prefetch Unit, which fetches instructions from memory and stores
them in a queue.

Flag Register:
The 8086 flag register contents indicate the results of computation in the ALU. It also contains
some flag bits to control the CPU operations.
It consists of 9 active flags out of 16. The remaining 7 flags marked ‘X’ are undefined flags.
These 9 flags are of two types:
 Conditional flags (6) and
 Control flags (3)

Figure 3.2: 8086 Flag register format

Page | 75
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The conditional flags are:
Carry Flag (CF) : CF=1; Whenever there is a carry or borrow out of the MSB (most
significant bit) of a result
CF=0; Otherwise.

Parity Flag (PF) : PF=1; If the number of 1’s in the result are even.
PF=0; If the number of 1’s in the result are odd.

Auxiliary Carry : AF=1; If a carry is generated out of the lower nibble (out of D3 bit)
Flag (AF) AF=0; Otherwise.

Zero Flag (ZF) : ZF=1; If the result of an operation is zero.

ZF=0; Otherwise.

Sign Flag (SF) : SF=1; if the MSB of the result is 1. For signed operations such a
number is treated as negative.
SF=0; Otherwise.

Overflow Flag (OF) : It is used to detect signed arithmetic overflow in operations.

OF=1; If the result of a signed operation is too large to fit in the
number of bits available to represent it.
OF=0; Otherwise.
The Control flags are:

Trap Flag (TF) : TF=1; the execution will be done step by step where it executes one
instruction at a time i.e. start single stepping mode. This is useful for
debugging.
TF=0; Otherwise (the free-running operation will be done).

Interrupt Flag (IF) : IF=1; interrupts are enabled and can be serviced by the CPU.
IF=0; interrupts are disabled.

Direction Flag (DF) : This flag is used for string operations.

DF=1; SI and DI are in auto-decrementing mode in string operations.
DF=0; SI and DI are in auto-incrementing mode in string operations.

Features of 8086 microprocessor:

 16-bit architecture.
 Segmented memory model.
 16-bit registers for data and addressing.
 Rich instruction set.
 Operated at a clock frequency of 5 MHz
 Versatile memory addressing modes.
 Multitasking potential due to segmentation.
 Up to 1 MB addressable memory.
 16-bit data bus, 20-bit address bus.
 Eight general-purpose registers.

3.1.2. Pin Description of 8086 Microprocessor

An 8086 microprocessor is also a 40 pin IC but has few separate pin configurations for minimum
and maximum mode.
The 8086 microprocessor operates in 2 modes that are
 Minimum mode and
 Maximum mode.
The minimum mode is a single processor configuration while the maximum mode is a multiple
processor configuration.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The figure below represents the pin diagram of 8086 microprocessor:

Figure 3.3: 8086 microprocessor Pin diagram

From figure 3.3, it is clear that from pin number 24 to 32, we have shown the different
configuration for minimum and maximum mode. Excluding these 8 pins, the rest 32 pins are the
same for both minimum as well as maximum mode.

The pin description of 8086 Microprocessor

Pin
Pin Name Description
No.
1& These two pins acts as the ground.
VSS
20
These are the multiplexed address and data bus.
2 to AD0 – The 8086 microprocessor has 20-bit address bus and 16-bit data bus.
16 AD14 and So, the 16 lines of the address and data bus are multiplexed together
& 39 AD15 At a particular time only either the address or the data bus will be
enabled from the multiplexed buses.
NMI is Non-maskable interrupt. These interrupts are generated inside
the processor. When an NMI occurs, then an interrupt service routine
17 NMI
is generated by the interrupt vector table.

INTR stands for an interrupt request.

18 INTR The INTR pin in the 8086 microprocessor is used to allow external
hardware devices to request the CPU's attention for processing

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
specific tasks or data. When a device sends an interrupt request to the
INTR pin, the CPU acknowledges it, pauses its current operation, and
processes the interrupt. This enables efficient communication
between the CPU and external devices.
It provides timing to the microprocessor for operations. Its frequency
19 CLK is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
̅̅̅̅̅̅̅̅̅ pin is used to reset the microprocessor, returning it to its
The 𝐑𝐄𝐒𝐄𝐓
̅̅̅̅̅̅̅̅̅ initial or default state. When a low-level signal (logic 0) is applied to
21 𝐑𝐄𝐒𝐄𝐓
the ̅̅̅̅̅̅̅̅̅
𝐑𝐄𝐒𝐄𝐓 pin, it forces the 8086 CPU to restart its operation from the
beginning, clearing all registers.
READY signal is used by the peripherals and memory devices in order
to show the readiness for the next operation.
22 READY It is an active high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait state.

̅̅̅̅̅̅̅ pin is Low, execution continues otherwise the processor

If the 𝐓𝐄𝐒𝐓
23 ̅̅̅̅̅̅̅
𝐓𝐄𝐒𝐓
waits in an "idle" state.
QS0 and QS1: These two pins indicate the status of the 6-byte pre-fetch
queue present in the architecture of 8086.
QS0 QS1 STATUS
24 & 0 0 No operation
QS0 and QS1
25 0 1 First byte from instruction queue
1 0 Empty instruction queue
1 1 Subsequent byte from instruction queue

These are basically 3 status pins and are active low. This means that if
the status at all the 3 pins is 0 then it shows that multiple interrupts
are to be handled in maximum mode.
The table below is representing the status of the processor in
different combinations
̅̅̅̅
𝐒𝐨 ̅̅̅̅
𝐒𝟏 ̅̅̅̅
𝐒𝟐 Status
26 ̅̅̅̅ 0 0 0 Interrupt acknowledgement (INTA)
𝐒𝐨 , ̅̅̅̅
𝐒𝟏 & ̅̅̅̅
𝐒𝟐
to
0 0 1 I/O Read
28
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 None

When this signal is active, it indicates to the other processors not to

ask the CPU to leave the system bus. It is activated using the LOCK
29 ̅̅̅̅̅̅̅̅
𝐋𝐎𝐂𝐊 prefix on any instruction.
Example: LOCK XCHG reg., Memory; Register is any register and
memory are the address.
These are the Request/Grant signals used by the other processors
30 & ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓 𝟎 and requesting the CPU to release the system bus. When the signal is
31 ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓 𝟏 received by CPU, then it sends acknowledgment. ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓 𝟎 has a
̅̅̅̅ /𝐆𝐓
higher priority than 𝐑𝐐 ̅̅̅̅̅̅
𝟏 .
̅̅̅̅
𝐑𝐃 =0; The microprocessor is performing read operation with either
32 ̅̅̅̅
𝐑𝐃
memory or I/O devices.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The MN/𝐌𝐗 ̅̅̅̅̅ pin shows whether the 8086 microprocessor is
operating in the minimum mode or maximum mode.

̅̅̅̅̅ ̅̅̅̅̅ = 0; the 8086 is operating in maximum mode i.e., multiple

MN/𝐌𝐗
33 MN/𝐌𝐗
processors.
̅̅̅̅̅ = 1; the 8086 is operating in minimum mode i.e., single
MN/𝐌𝐗
processor.

̅̅̅̅̅̅
𝐁𝐇𝐄 is an acronym for Bus High Enable. The combination of the ̅̅̅̅̅̅
𝐁𝐇𝐄
signal and S7 status informs about the existence of the data on the bus.
Also, different combinations show whether the bus is containing
overall 16-bit, upper byte or lower byte of the data.
34 ̅̅̅̅̅̅/ S7
𝐁𝐇𝐄 ̅̅̅̅̅̅
𝐁𝐇𝐄 S7 Status
0 0 All 16-bit data will be accessed
0 1 Upper byte of the data will be accessed
1 0 Lower byte of the data will be accessed
1 1 None or Idle
35 A16/S3, Out of 20 address bits, 4 are present in the multiplexed form with the
to A17/S4, status signals. In the case of memory operations, these pins act as an
38 A18/S5 and address bus and contain the memory address of any particular
A19/S6 instruction or data.
However, from I/O operations these pins are low that shows the status
of the processor.
Basically, the signal at S3 and S4 show that which segment is currently
accessed by the microprocessor among the four segments present in
it.
S3 S4 STATUS
0 0 Extra Segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment
S5: when enabled, shows the presence of an interrupts in the
microprocessor. So, basically, it serves as an interrupt flag.

S6: Shows the status of the bus master for the current operation i.e.
Whether the 8086 is the bus master or any other proficient device is
acting as the bus master.
When S6= 0; it indicates the 8086 is holding the access of the bus
otherwise it is high i.e., 1.
40 VCC The external power supply of +5V is connected to the microprocessor

The Pin description of 8086 Microprocessor minimum mode:

Pin
Pin Name Description
No.

̅̅̅̅̅̅̅ is an interrupt acknowledgement signal. When the

𝐈𝐍𝐓𝐀
24 ̅̅̅̅̅̅̅
𝐈𝐍𝐓𝐀
microprocessor receives this signal, it acknowledges the interrupt.

ALE stands for address enable latch.

ALE=1; The AD0 to AD15 are acting as address lines A0 to A15 during T1
ALE
25 clock.
ALE=0; The AD0 to AD15 are acting as data lines D0 to D15 during later
clock

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

̅̅̅̅̅̅
𝐃𝐄𝐍 is used for data enable and this is an active low pin.
26 ̅̅̅̅̅̅
𝐃𝐄𝐍 ̅̅̅̅̅̅
𝐃𝐄𝐍0; then the transceiver gets enabled and it separates the data from
the multiplexed address and data bus.

DT/𝐑̅ pin is used to show whether the data is getting transmitted or is

̅ received.
27 DT/𝐑 ̅ =1; provides the information regarding the transmission of data.
DT/𝐑
DT/𝐑̅ =0; indicates reception of data.

̅̅̅ pin indicates whether the processor is performing an operation

M/𝐈𝐎
̅̅̅ with memory or I/O devices.
28 M/𝐈𝐎 ̅̅̅ = 1; operation is carried out through the memory.
M/𝐈𝐎
̅̅̅ = 0; operation is carried out through the I/O devices.
M/𝐈𝐎

̅̅̅̅̅ =0; indicates that the processor is performing write operation

𝐖𝐑
29 ̅̅̅̅̅
𝐖𝐑
from either memory or I/O devices.
This pin is used as a response pin for the hold request. Once request for
accessing the buses is produced by an external entity. Then the
30 HLDA
microprocessor acknowledges the device that its request will be
considered once it gets over by the current operation.
HOLD signal indicates to the processor that external devices are
31 HOLD
requesting to access the address/data buses.

3.1.3. Memory Segmentation and Physical Address

Explain the memory segmentation of 8086 in details.

AKTU Question Paper 2022-23, 10 MARKS
Discuss the various memory segments in 8086.
AKTU Question Paper 2021-22, 2 MARKS
Discuss the memory segmentation in 8086 and the various segments of the memory.
AKTU Question Paper 2020-21, 2 MARKS
Memory Segmentation
Memory segmentation is the method where whole memory is divided into the smaller parts called
segments, and each segment can be up to 64 KB (kilobytes) in size. This segmentation allows the
processor to access a total of 1 MB (megabyte) of memory.
 DATA SEGMENT
 CODE SEGMENT
 STACK SEGMENT and
 EXTRA SEGMENT.
Each segment can be up to 64 KB (kilobytes) in size. Segment registers store starting address of
each segments in memory.

Maximum size of segment:

 All offsets are limited to 16-bits. It means that the maximum size possible for segment is
216= 65,535 bytes (64 KB).
 The offset of the first location within the segment is 0000 H. The offset of the last location
in the segment is FFFF H i.e. the address within each segment is ranging between 0000 H
to FFFF H (64 KB).

The 8086 microprocessor has 20 lines address bus. With 20 address lines, the memory, allowing
it to address memory of up to 220 bytes i.e. 220= 1,048,576 bytes (1 MB). 8086 can access memory
with address ranging from 00000 H to FFFFF H.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure 3.4: 8086 Memory segmentation

Explain the physical address, offset address and segment address in context to 8086.
AKTU Question Paper 2021-22, 2 MARKS

The starting (base) address and end address (top) of each segment are as below:

Segment Starting address End (top) address Total Size

Data Segment 2000 H 2FFF H 64 KB
Code Segment 3000 H 3FFF H 64 KB
Stack Segment 5000 H 5FFF H 64 KB
Extra Segment 7000 H 7FFF H 64 KB

Segment Register:
The 8086 has four primary segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment). Each of these registers holds a 16-bit value that represents
the base address of a specific segment in memory.

Offset Address:
Within each segment, memory is addressed using an offset value. The offset is a 16-bit value that
specifies the location of data or instructions within the segment. It's essentially a displacement
from the base address of the segment.

Physical Address:
The 20-bit address of a data or instructions is called its Physical Address i.e. a physical address
represents a specific location in the memory where data or instructions are stored. To calculate
the physical address of a memory location, the 8086 combines the value in the segment register
with the offset. This 20-bit physical address allows access to up to 1 MB of memory.

Physical address = (Base address×10H) + Effective address

Page | 81
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure 3.5: Formation of 20-bit physical address

Default segment registers and offset registers used to calculate physical address are as shown in
table 3.1.
Table 3.1: Default segment registers and offset registers
Segment
Offset Register Function
Register
CS IP Address of the next instruction
DS BX, DI, SI Address of the data
SS SP, BP Address in the stack
ES BX, DI, SI Address of the destination data (for string operations)

Rules of Segmentation
 The starting address of a segment should be such that it can be evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation:

The main advantages of segmentation are as follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e. segmentation allows the use of
16-bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it
would require 20-bit registers.
 It is possible to enhance the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area.

Example 1: If [CS]=234AH, [IP]=1234H find the physical address.

Solution: CS×10H = 234A0H
+
IP = 1234H
------------------------------------------
Physical Address =246D4H
------------------------------------------
Example 2: The value of Code Segment CS Register is 4042H and the value of different offsets is
as follows: BX:2025H, IP: 0580H, DI: 4247H. Calculate the physical address of the memory
location pointed by the CS register.

Solution:
The offset of the CS Register is the IP register. Therefore, the effective address of the memory
location pointed by the CS register is calculated as follows:
Physical address = (Base address of CS register X 10H) + Address of IP
Physical address = 4042 X 10H + 0580

Page | 82
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
=40420+0580
Physical address =409A0H
Example 3: Calculate the effective address for the following register: SS: 3640H, SP: 1735H, BP:
4826H

Solution:
Both SP and BP are the offsets for Stack Register (SS). The address calculated when BP is taken as
the offset gives the starting address of the stack. The address when SP is taken as the offset
denotes the memory location where the top of the stack lies.
Therefore, the effective address for both these cases is:
(SS X 10H) + SP = 3640H X 10H + 1735H
= 36400H + 1735H
= 37B35H
(SS X 10H) + BP = 3640H X 10H + 4826H
= 36400H + 4826H
= 3AC26H

Example 4: The value of the DS register is 3032H. And the BX register contains a 16-bit value
which is equal to 3032H. 0008H is added to BX. ADD BX, 0008H, the register AX contains some
value which needs to be stored at a location as follows: MOV [BX], AX
Calculate the address at which the value of the AX will be stored

Solution:
After executing the first instruction, the value of BX Register is as follows:
BX = 303AH
The BX register is an offset of the Data Segment (DS) register. So, the location at which the value
of the AX register will be stored is calculated as follows:
(DS X 10H) + BX = 3032H X 10H +303AH
= 30320H + 303AH
= 3335AH

Example 5: You are provided the following values: DS: 3056H, IP: 1023H, BP: 2322H and SP:
3029H. Can you calculate the effective address of the memory location as per the DS register?

Solution:
No, the effective address of the DS register cannot be calculated from the given values because
none of the given offset is an offset of the DS Register.

3.1.4. Instruction format of 8086

An 8086 instruction consists of different fields. One filed is called the operation code or op code.
Opcode indicates the operation to be performed by the instruction. The other fields are called the
operands. Operands indicate the data or the address of the data to be operated upon by the
instruction.
A general instruction format is shown in the figure 3.6.
Opcode Operand . . . . Operand
Figure 3.6: General instruction format

Page | 83
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3.1.5. Addressing Modes of 8086
Discuss the various addressing modes in 8085 along-with examples.
AKTU Question Paper 2020-21, 10 MARKS
Discuss the various addressing modes available in 8086 along-with examples.
AKTU Question Paper 2021-22, 10 MARKS

The Intel 8086 microprocessor supports various addressing modes, which determine how
operands (data) are accessed or addressed in instructions. These addressing modes provide
flexibility in how data is fetched or manipulated during program execution. The commonly used
addressing modes of the 8086 are as follows:

1 Immediate In this addressing mode, the operand is a constant value specified in the
Addressing: instruction itself.
Example: MOV AX, 1234; loads the value 1234 H into the AX register.

2 Register In this addressing mode, the operand is stored in one of the CPU registers.
Addressing: Example: ADD AX, BX; adds the value in the BX register to the AX
register.
3 Direct In this addressing mode, the operand's address is directly specified in the
Addressing: instruction.
Example: MOV AX, [1592H]
MOV AL, [0A00H]; moves the value at memory address 0A00H into the
AL register.
4 Register In this addressing mode addressing mode allows data to be addressed at
Indirect any memory location through an offset address held in any of the
Addressing: following registers: BP, BX, DI & SI.
Example: MOV AX, [BX]; Suppose the register BX contains 4895H, then
the contents 4895H are moved to AX
5 Based In this addressing mode, the offset address of the operand is given by the
Addressing: sum of contents of the BX/BP registers and 8-bit/16-bit displacement.
Example: MOV DX, [BX+04]

6 Based-index In this addressing mode, the operands offset address is found by adding
addressing the contents of SI or DI register and 8-bit/16-bit displacements.
mode: Example: MOV BX, [SI+16]
7 Based In this addressing mode, the operands offset is computed by adding the
indexed with base register contents and Index registers contents and 8 or 16-bit
displacement displacement.
mode: Example: MOV AX, [BX+DI+08]

8 Scaled Index In this addressing mode, an index register is multiplied by a scaling factor
Addressing and added to a base register to form an address.
Mode Example: MOV AL, [BX+SI*2] moves the value at the memory location
pointed to by (BX+SI*2) into the AL register.

Page | 84
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3.1.6. EVOLUTION OF MICROPROCESSORS:
Explain the various generations of microprocessor.
AKTU Question Paper 2022-23, 10 MARKS

Microprocessors have evolved through several generations, each marked by significant

improvements in processing power, architecture, and capabilities. Here's an overview of the
major generations of microprocessors:

First Generation (1971-1976):

 The first microprocessor was the Intel 4004, released in 1971.
 These early microprocessors had limited processing power and were primarily used
in calculators and simple control systems.
 They featured 4-bit data buses and clock speeds measured in kilohertz.
 The 8085 was released in 1976. It is 8-bit microprocessor and can operate with 3 MHz.
This microprocessor is used for general purpose applications (example: Traffic signal
etc.)

Second Generation (1976-1990):

 The Intel 8086, released in 1978, marked the beginning of this generation.
 8-bit and 16-bit microprocessors were common, offering increased processing power
and expanded memory addressing capabilities.
 Key microprocessors included the Intel 8088, 8086, and Motorola 68000 series.
 Clock speeds increased into the megahertz range, and microprocessors started to be
used in early personal computers.

Third Generation (Late 1980s-1990s):

 The introduction of 32-bit microprocessors, such as the Intel 80386 and 68020,
signaled the third generation.
 These processors offered greater processing power, 32-bit memory addressing, and
support for multitasking and protected memory.
 Advanced instruction sets and cache memory were introduced to boost performance.
 This era saw the rise of personal computers and workstations.

Fourth Generation (1990s-Present):

 The fourth generation includes the Pentium series (e.g., Intel Pentium) and other 32-
bit and 64-bit processors.
 Clock speeds continued to rise, and processors incorporated advanced features like
MMX, SSE, and SIMD instructions for multimedia applications.
 Mobile processors (e.g., ARM-based processors) and server processors (e.g., Intel
Xeon) became prominent.
 The microarchitecture became more complex, with multiple cores and hyper-
threading.

Fifth Generation (Present and Beyond):

 The fifth generation is characterized by the proliferation of multi-core processors,
increased energy efficiency, and advancements in parallel processing.
 Processors are designed for artificial intelligence (AI), machine learning, and Internet
of Things (IoT) applications.
 Graphics Processing Units (GPUs) and specialized accelerators play a crucial role in
data-intensive workloads.
 Quantum computing, neuromorphic computing, and other emerging technologies are
pushing the boundaries of what's possible in computing.

These generations represent the major milestones in the development of microprocessors,

with each generation building upon the advancements of the previous one.

Page | 85
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
As technology continues to evolve, microprocessors are expected to become more powerful,
energy-efficient, and versatile, enabling a wide range of applications in both consumer and
industrial domains.

PREVIOUS YEAR AKTU EXAM QUESTIONS ON 8086

MICROPROCESSOR

8086 ARCHITECTURE
Draw the architecture of 8086 Microprocessors and explain its all blocks.
AKTU Question Paper 2022-23, 10 MARKS

Investigate the need of pre-fetch instruction queue in 8086.

AKTU Question Paper 2021-22, 2 MARKS

MEMORY SEGMENTATION

Explain the memory segmentation of 8086 in details.

AKTU Question Paper 2022-23, 10 MARKS

Discuss the various memory segments in 8086.

AKTU Question Paper 2021-22, 2 MARKS

Discuss the memory segmentation in 8086 and the various segments of the memory.
AKTU Question Paper 2020-21, 2 MARKS

PHYSICAL ADDRESS
Explain the physical address, offset address and segment address in context to 8086.
AKTU Question Paper 2021-22, 2 MARKS

ADDRESSING MODES OF 8086

Discuss the various addressing modes in 8085 along-with examples.
AKTU Question Paper 2020-21, 10 MARKS

Discuss the various addressing modes available in 8086 along-with examples.

AKTU Question Paper 2021-22, 10 MARKS

EVOLUTION OF MICROPROCESSORS
Explain the various generations of microprocessor.
AKTU Question Paper 2022-23, 10 MARKS

Page | 86
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

PERIPHERAL DEVICES
Peripheral Devices: 8237 DMA Controller, 8255 Programmable Peripheral Interface,
8253/8254 Programmable Timer/Counter, 8259 Programmable Interrupt Controller, 8251
USART and RS 232C.

3.2 Peripheral devices

Peripheral interfacing devices are hardware components or integrated circuits (ICs) designed to
facilitate the connection and communication between a microprocessor and external peripheral
devices.

3.2.1 Direct Memory Access Controller 8237:

With the help of a functional block diagram and working of 8257 DMA controller.
AKTU Question Paper 2022-23, 10 MARKS
Explain Direct Memory Access (DMA).
AKTU Question Paper 2022-23, 2 MARKS
Explain Direct Memory Access (DMA).
AKTU Question Paper 2020-21, 2 MARKS
Illustrate the process of DMA with the help of 8237 DMA controller.
AKTU Question Paper 2020-21, 10 MARKS
Direct Memory Access is a process where data is transferred between two peripherals
directly without the involvement of the microprocessor.

This process employs the 2 signals HOLD and HLDA pin on the microprocessor.

HOLD: This is an active high input signal to the 8085 microprocessor from another master
requesting the use of the address and data buses. After receiving the Hold request, the
microprocessor relinquishes the buses. The Hold Acknowledge (HLDA) signal is sent out. The
microprocessor regains the control of the buses after HOLD goes low.

HLDA (Hold Acknowledge): This is an active high output signal indicating that the
microprocessor is relinquishing control of the buses.

A DMA controller uses these signals as if it were a peripheral requesting the MPU for the control
of the buses. The MPU communicates with the controller by using the Chip Select line, buses, and
control signals. Once the controller has gained control, it plays the role of a processor for data
transfer.

To perform data transfer operation, the DMA should have the following
1 a data bus,
2 an address bus,
3 Read/Write control signals, and
4 control signals to disable its role as a peripheral and to enable its role as a processor.

This process is called switching from the slave mode to the master mode.

3.2.2 The 8237 DMA Controller:

 The 8237 is a programmable Direct Memory Access controller (DMA) with a 40-pin
package.
 It has four independent channels with each channel capable of transferring 64 K bytes.

Page | 87
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
DMA CHANNEL AND INTERFACING:

Figure 3.7: 8237A DMA controller with Internal Registers

Figure 3.7 shows a logical pin out and internal registers of the 8237A and interfacing with the
8085 using a 3-to-8 decoder.

The 8237 has four independent channels, CHO to CH3. Internally, two 16-bit registers are
associated with each channel: One is used to load a starting address of the byte to be copied
and the second is used to load a count of the number of bytes to be copied.

Figure 3.7 shows eight such registers that can be accessed by the MPU. The addresses of these
registers are determined by four address lines, A3 to A0, and the Chip Select (CS) signal.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Address lines Hex
Selected Channels/Register etc.
A3 A2 A 1 A0 Address
0000 00 H CHO Memory Address Register (MAR)
0001 01 H CH0 Count Register
0010 02 H CH1 Memory Address Register (MAR)
0011 03 H CH1 Count Register
.
.
.

1111 0F H WR all Mask register bits

The address 0000 on lines A3 to A0 selects CHO Memory Address Register (MAR) and address
0001 selects the next register, CH0 Count. Similarly, all the remaining registers are selected in
sequential order. The last eight registers are used to write commands or read status as
shown in figure 3.7, the MPU accesses the DMA controller by asserting the signal Y_0 of the
decoder. Therefore, the addresses of these internal registers range from 00 to 0FH as follows:

3.2.3 DMA SIGNALS:

In figure 3.7: signals are divided into two groups
i. The left of the 8237 is used for interfacing with the microprocessor
ii. The right-hand side of the 8237 is for communicating with peripherals.

The signals that are necessary to understand the DMA operations are explained as follows:
CLK: Clock input to 8237. The maximum clock frequency is 5 MHz. In the 8085 system, the
processor clock is inverted and applied to CLK 8237.
CS: Logic low chip select signal. It is an input signal to select 8237 during programming mode.
RESET : Reset input to 8237. Connected to a system reset, when the RESET signal
goes high the command, status, request, and temporary registers are
cleared. It also clears the first-last flip-flop and sets the mask register.
READY : Ready input signal and it is tied to VCC for normal timings. When READY
input is tied low, the 8237 enters a wait state. This is used to get extra time
in DMA machine cycles to transfer data between slow memory and IO
devices.
HRQ : Hold request output signal. It is the hold request signal sent by 8237 to the
processor HOLD pin, to make a request for the bus to perform a DMA
transfer.
HLDA : Hold acknowledge input signal. It is the hold acknowledge signal to be sent
by the processor to inform the acceptance of the hold request.
DREQ3 – : These are the four independent, asynchronous input signals to the DMA
DREQ0 channels from peripherals such as floppy disks and the hard disk. Used by
IO devices to request for DMA to transfer.
DACK3 – : These are output lines to inform the individual peripherals that a DMA is
DACK0 granted. DREQ and DACK are equivalent to handshake signals in I/O
devices.
DB7 – DB0 : Data bus lines. These pins are used for data transfer between the processor
and DMA.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
̅̅̅̅̅
𝐈𝐎𝐑 : Bidirectional IO read control signal. It is an input control signal for reading
the DMA controller during programming mode and an output control signal
for reading the IO device during DMA (memory) write cycle.
̅̅̅̅̅̅
𝐈𝐎𝐖 : Bidirectional IO writes control signal. It is an input control signal for writing
the DMA controller during programming mode and an output control signal
for writing the IO device during DMA (memory) read cycle.
EOP : End of process. It is a bidirectional low active signal. It is used either as an
input to terminate a DMA process or as an output to inform the end of the
DMA transfer to the processor. This output can be used as an interrupt to
terminate DMA.
A3 – A0 : Four bidirectional address lines. Used as input address during
programming mode to select internal registers. During DMA mode the low-
order four bits of memory address are output by 8237 on these lines.
A7 – A4 : Four unidirectional address lines. Used to output the memory address bits
A7 to A4 during DMA mode.
AEN : Address enable output signal. It is used to enable the address latch
connected to DB7 – DB0 pins of 8237. It is also used to disable any buffers in
the system connected to the processor.
ADSTB : Address strobe output signal. It is used to latch the high-byte memory
address issued through DB7 to DB0 lines by 8237 during DMA mode into an
external latch.
̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐑 : Memory read control signal. It is an output control signal issued during a
DMA read operation.
̅̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐖 : Memory write control signal. It is an output control signal issued during
DMA write operation.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3.2.4 INTERFACING 8237A DMA CONTROLLER WITH THE 8085:

Figure 3.8: Interfacing 8237A DMA Controller with the 8085

The DMA is used to transfer data bytes between I/O such as floppy disk and the system memory
or from memory to memory at high speed. In includes 8-data lines, 4-control signals (𝐈𝐎𝐑 ̅̅̅̅̅, 𝐈𝐎𝐖
̅̅̅̅̅̅,
̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐑, 𝐌𝐄𝐌𝐖) and 8-address lines A7-A0. It needs 16 address lines to access 64 KB.
Therefore, an additional 8 lines must be generated as shown in figure 3.7.
When a data transfer begins, DMA places the low-order byte on the address bus and the high-
order byte o the data bus and asserts AEN (address enable) and ADSTB bus i.e. it places the 16-
bit address on the system bus.
After the transfer of the first byte, the latch is updated when the lower byte generates a carry or
borrow.
Figure 3.8 has two latches, one latch (373 #1) to latch a high-order address from the data bus by
using the AEN and ADSTB signals, and the second latch (373 #2) to demultiplex the 8085 bus and
generate the low-order address bus by using the ALE (Address Latch Enable from the 8085)
signal. The AEN signal is connected to the ̅̅̅̅
OE signal of the second latch to disable the low-order
address bus from the 8085 when the first latch is enabled to latch the high-order byte of the
address.

3.2.5 PROGRAMMING THE 8237:

To implement the DMA transfer, the 8237 should be initialized by writing into various control
registers discussed earlier in the DMA channels and interfacing section.

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To initialize the 8237, the following steps are necessary.
1 Write a control word in the Mode register that selects the channel and specifies the type
of transfer (Read, Write, or Verify) and the DMA mode (block, single-byte, etc.).
2 Write a control word in the Command register that specifies parameters such as priority
among four channels, DREQ and DACK active levels, and timing, and enables the 8237.
3 Write the starting address of the data block to be transferred in the channel Memory
Address Register (MAR).
4 Write the count (the number of the bytes in the data block) in the channel Count register.
5 The starting address of the data block is 4075H and subsequent data bytes have memory
addresses in increasing order.
6 The Command parameters should be: normal timing. fixed priority, late write. DREQ and
DACK are both active low.
7 Set up the demand mode whereby the DMA can complete the data transfer without any
interruption.

MVI A, 00000100B ; Command

OUT 08H ; Send command register
MVI A, 00000111B ; Mode
OUT OBH ; Send to Mode register
MVI A, 75H ; Low-order byte of starting address
OUT 06H ; Output to CH3 memory Address Register
MVI A, 40H ; Higher-order byte of starting address
OUT 06H ; Output to CH3 memory Address Register
MVI A, FFH ; Low-order byte of the count 03FF H
OUT 07H ; Output to CH3 Count register
MVI A, 03H ; High-order byte of the count 03FF H
OUT 07H ; Output to CH3 Count register
MVI A, 10000000B ; Command
OUT 08H ; Send to Command register

3.2.6 DMA OPERATION:

The DMA controller can be classified under two modes:
i. The microprocessor and peripherals such as floppy disks. The DMA plays two roles in
a given system: It is an I/O to the microprocessor (Slave Mode) and
ii. It is a data transfer processor to peripherals such as floppy disks (Master Mode).

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3.3 8255 PROGRAMMABLE PERIPHERAL INTERFACE:
Explain the pin diagram of 8255 along-with the block diagram.
AKTU Question Paper 2020-21, 10 MARKS

Explain the CWR of 8255 Programmable Peripheral Interface and also discuss the BSR
mode. AKTU Question Paper 2022-23, 2 MARKS

With the help of a functional block diagram explain the organization and working of 8255
microprocessor. AKTU Question Paper 2022-23, 2 MARKS

Figure: 8255 interfacing with microprocessor

 PPI 8255 is a general purpose programmable I/O device designed to interface the
microprocessor with its outside world such as ADC, DAC, keyboard etc.

It contains the following blocks

1. Data bus buffer
2. Read/Write control logic
3. Port A and Port B
4. Port C
5. Group A and Group B control

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
1. DATA BUS BUFFER:
 The 8-bit bidirectional data bus buffer is used to interface the 8255 internal data bus with
the system data bus (Microprocessor).
 The direction of the data buffer is decided by read and write control signals.
 When the read is activated, it transmits data to the system data bus.
 When a write is activated, it receives data from the system data bus.

2. READ/WRITE CONTROL LOGIC:

 The control signals are 𝐑𝐃
̅̅̅̅ & 𝐖𝐑
̅̅̅̅̅ and address signals used are A0, A1 and 𝐂𝐒 ̅̅̅̅.
 The signals 𝐑𝐃 & 𝐖𝐑 are connected to 𝐈𝐎𝐑 & 𝐈𝐎𝐖 or 𝐌𝐄𝐌𝐑 & 𝐌𝐄𝐌𝐖
̅̅̅̅ ̅̅̅̅̅ ̅̅̅̅̅ ̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅
 The address lines of A0 & A1 of 8085 are directly connected to address lines A 0 & A1 of
8255.
 The 8255 operation/selection is enabled/disabled by ̅𝐂𝐒 ̅̅̅ signal. The ̅𝐂𝐒̅̅̅ is connected to
address chip select decoder.

3. PORT A AND PORT B

 Port A and port B consist of an 8-bit bidirectional data output latch/buffer and an 8-bit
data input buffer.
 The function of ports A and B is decided by the control bit pattern available in GA and GB
control.
 The functions of ports A and B are also independent of the mode of operation.

4. PORT C
 Port C consists of an 8-bit bidirectional data output latch/buffer and an 8-bit data input
buffer.
 It is divided into 2 sections, Port C upper PCU and Port C lower PCL. These two sections
can be programmed and used separately as a 4-bit I/O port.
 It can be used as
i. Simple I/O
ii. Handshake signals
iii. Status signal inputs.
 Port C is used in combination with port A & Port B for both the status and handshaking
signals.

5. GROUP A AND GROUP B CONTROL:

 The 8255 I/O ports are divided into 2 sections. Group A (GA) and Group B (GB).
 Group A consists of PORT A and PORT C upper.
 Group B consists of PORT B and PORT C lower.
 Each group is programmed through software.
 Group A controls port A with higher order port C bits whereas group B controls port B
with lower order port C bits.
Depending upon the value if ̅𝐂𝐒
̅̅̅, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).
̅𝐂𝐒
̅̅̅ A1 A0 OPERATION Address
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Selection X

3.3.1 8255 has two modes of operation

1. Bit set reset (BSR) mode
2. Input/output (I/O) mode (Mode 0, Mode 1 & Mode 2)

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
BSR (BIT SET RESET MODE):
The content of the control word register will be as follows, when used in the BSR mode

Figure: Control Word Register in BSR mode

 The BSR mode is a port C bit set/reset mode.

 If MSB of Control Word Register (D7) is 0, PPI works in BSR mode. In this mode only, Port
C bits are used for set or reset.
 The individual bit of port C can be set or reset by writing the control word in the control
register.
 At a time, only a single bit of port C can be Set or Reset.
 Is used for control or ON/OFF switch.
 BSR control word doesn’t affect ports A and B functioning.

The D3 D2 D1 bits in Control Word Register in the BSR mode

D3 D2 D1 Particular bit of Port C selected
0 0 0 Bit 0
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7

INPUT/OUTPUT (I/O) MODE:

Figure: Input / Output Mode

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
If MSB of Control Word Register (D7) is 1, PPI works in input-output mode. This is further divided
into three modes:
1. Mode 0: Input / Output mode
2. Mode 1: Input / Output with handshaking
3. Mode 2: Bidirectional I/O port with handshaking
Mode 0:
 This is a basic input/output mode, whose features are:
 All the three ports (Port A, Port B & Port C) can be programmed in either input or output
mode.
 Ports don’t have handshake or interrupt capability

Mode 1:
 In this mode, input or outputting of data is carried out by taking the help of handshaking
signals, also known as strobe signals. The basic features of this mode are:
 Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.
 I/Ps and O/Ps are latched.
 Interrupt logic is supported.
 Handshake signals are exchanged between CPU and peripheral prior to data transfer.
 In this mode, Port C is called status port.
 There are two groups in this mode Group A and Group B. They can be configured
separately. Each group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for
handshaking in each group.

Mode 2:

 In this mode, the ports can be utilized for the bidirectional flow of information by
handshaking signals.
 The pins of group A can be programmed to acts as bidirectional data bus and the Port C
upper (PC7 – PC4) are used by the handshaking signal. The rest 4 lower Port C bits are
utilized for I/O operations.
 Port B can be programmed in mode 0 & 1 and in mode 1 the lower bits of Port C of group
B are used for handshaking signals.
 It also has interrupt handling capacity.

3.3.2 PIN DIAGRAM OF 8255:

It consists of 40 pins that operates in +5V regulated power supply out of which 24 pins are for
I/O that are programmable in groups of 12 pins and has three distinct modes of operation.

Figure: Pin diagram of 8255

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Symbol Name Function

These are 8-bit bi-directional data bus lines, connected to the system
D0-D7 Data Bus
data bus for data transfer between CPU and 8255.

These are input, active HIGH address lines used to distinguish

̅𝐂𝐒
̅̅̅ Chip select different ports of 8255 such as Port A, Port B, Port C, and Control
register.

It is the signal used for read operation. A low signal at this pin shows
̅̅̅̅
𝐑𝐃 Read that CPU is performing read operation at the ports or status word
through data buffer.

It is the signal used for write operation. A low signal at this pin allows
̅̅̅̅̅
𝐖𝐑 Write the CPU to perform write operation over the ports or control register
of 8255 using the data bus buffer.

Address These are basically used to select the desired port among all the
A0-A1
lines ports of the 8255. i.e. Port A, Port B, Port C, and Control register.

This is an active HIGH input signal used to reset 8255. When 8255 is
RESET Reset reset, it clears the control word register and all ports are set to input
mode.

These are 8-bit bidirectional I/O pins used to send data to the
PA0- Port A pins
peripheral or to read data from the peripheral. The contents are
PA7 0 to 7
transferred to/from Port A.

Port B pins
PB0-PB7 These are 8-bit bidirectional I/O pins used the same as PA0-PA7
0 to 7

These are 8-bit bidirectional I/O pins. These lines are divided into 2
Port C pins sections i.e. PC0-PC3 and PC4-PC7. These two sections can be
PC0-PC7
0 to 7 individually used to transfer 4 bits of data from two separate port C
sections.

3.3.3 8253/8254 PROGRAMMABLE INTERVAL TIMER (PIT):

Demonstrate the architecture of 8253/54 Programmable Timer and discuss the control
word register.
AKTU Question Paper 2021-22, 10 MARKS
Name the 06 operating modes of 8254.
AKTU Question Paper 2022-23, 2 MARKS

The Intel 8253 Programmable Interval Timer (PIT) is timing device commonly used in
microprocessor-based systems to generate precise time delays and control events. It provides
a reliable and accurate timing reference for various applications.

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit counters each capable of handling
clock inputs up to 10 MHz. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT”
output. To operate a counter, a 16-bit count is loaded in its register. On command, it begins to
decrement the count until it reaches 0, then it generates a pulse that can be used to interrupt
the CPU.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Functional Block Diagram of 8254 Timer

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT.

Data Bus Buffer:

It is a tristate, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions
 Programming the modes of 8253/54.
 Loading the count registers.
 Reading the count values.

Read/Write Logic:
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode,
the RD and WR signals are connected to IOR and IOW, respectively. In the memory mapped I/O
mode, these are connected to MEMR and MEMW. Address lines A0 & A1 of the CPU are connected
to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word register
and counters are selected according to the signals on lines A0 & A1.
̅̅̅̅ A1 A0 OPERATION
𝐂𝐒
0 0 0 Counter 0
0 0 1 Counter 1
0 1 0 Counter 2
0 1 1 Control Word Register

COUNTERS:
Each counter consists of a single, 16 bit-down counters, which can be operated in either binary
or BCD. Its input and output are configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Control Word Register:
This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation. Following
table shows the result for various control inputs.

Format of Control Word 0f 8254 Timer

3.3.4 OPERATION OF 8253:

The functions of the 8253/54 can be described by Write and Read operation.

WRITE Operation:
 Write a control word into control register.
 Load the low-order byte of a count in the counter register.
 Load the high-order byte of count in the counter register.

READ OPERATION:
1. Simple Read:
It involves reading a count after inhibiting the counter by controlling the gate input or the
clock input of the selected counter, and two I/O read operations are performed by the
CPU. The first I/O operation reads the low-order byte, and the second I/O operation reads
the high order byte.

2. Counter Latch Command:

In the second method, an appropriate control word is written into the control register to
latch a count in the output latch, and two I/O read operations are performed by the CPU.
The first I/O operation reads the low-order byte, and the second I/O operation reads the
high order byte.

3. Read-Back Command (Available only for 8254):

The third method uses the Read-Back command. This command allows the user to check
the count value, programmed Mode, and current status of the OUT pin and Null count flag
of the selected counter(s).

8254 MODES OF OPERATION:

1. Mode 0 (Interrupt on terminal count)
2. Mode 1 (Programmable Monoshot)
3. Mode 2 (Rate Generator)
4. Mode 3 (Square Wave Generator)

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
5. Mode4(Software Triggered Strobe)
6. Mode 5 (Hardware Triggered Strobe)
The Description and operation of various modes of timer are depicted in the figures below.

MODE 0: INTERRUPT ON TERMINAL COUNT:

 In this mode, OUT is low.
 Once a count is loaded the counter is decremented after every cycle and when count
reaches zero, the OUT goes high.
 This can be used as an interrupt. The OUT remains high until a new count or command
word is loaded.
MODE 0: INTERRUPT ON TERMINAL COUNT
Write control word using counter 1, read load LSB, Mode 0, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 1 0 1 0 0 0 0
Control Word = 50 H Let Count = 04

This is used for event counting. After writing the control word, OUT is low at first. It will remain
low until the counter reaches 0, it is decremented by 1 after each clock cycle. Then the OUT
goes high, and remains high until a new count is there or a new Mode 0 control word is written
into the counter. The GATE=1 indicates enable counting, and 0 indicates disable counting.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

1. The output will be initially high
2. The output will go low on the CLK pulse following the rising edge at the gate input.
3. The output will go high on the terminal count and remain high until the next rising edge
at the gate input.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

Write control word using counter 0, read load LSB, Mode 1, Binary
Counter

Control Word Select Binary

Operation Mode Select
Counter Counter
0 0 0 1 0 0 1 0
Control Word = 12 H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

OUT will be high at first, it will go low on the clock pulse following a trigger to begin the one-
shot pulse. It will remain 0 until the counter reaches 0.

MODE 2: RATE GENERATOR

This mode functions like a divide by-N counter.
1. The output will be initially high.
2. The output will go low for one clock pulse before the terminal count.
3. The output then goes high, the counter reloads the initial count and the process is
repeated.
4. The period from one output pulse to the next equals the number of input counts in the
count register.

MODE 2: RATE GENERATOR

Write control word using counter 1, read load LSB, Mode 2, Binary
Counter

Control Word Select Binary

Operation Mode Select
Counter Counter
0 1 0 1 0 1 0 0
Control Word = 54 H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Initially OUT is low. When the counting is enabled, it goes HIGH. This process repeats
periodically. This mode is used as frequency divided.

MODE 3: SQUARE WAVE GENERATION:

1. Initially output is high.
2. For even count, counter is decremented by 2 on the falling edge of each clock pulse. When
the counter reaches terminal count, the state of the output is changed and the counter is
reloaded with the full count and the whole process is repeated.
3. If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After
timeout, the output goes low and the full count is reloaded. The first clock pulse
decrements the count by 3 and subsequent clock pulse decrement the count by two. Then
the whole process is repeated. In this way, if the count is odd, the output will be high for
(𝑛 + 1)/2 counts and low for (𝑛 − 1)/2 counts.

MODE 3: SQUARE WAVE GENERATION

Write control word using counter 1, read load MSB, Mode 3, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 1 1 0 0 1 1 0
Control Word = 66 H Let Count = 04

If the GATE is 1, then the counting is enabled, otherwise it is disabled. This mode is used to
generate the square wave. The time period is equal to count. If the count is even, the on-time of
wave is count/2. Otherwise on-time is (count+1)/2 and off-time is (count-1)/2.

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MODE 4: SOFTWARE TRIGGERED STROBE

1. The output will be initially high
2. The output will go low for one CLK pulse after the terminal count (TC).

MODE 4: SOFTWARE TRIGGERED STROBE

Write control word using counter 0, read load LSB, Mode 4, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 0 0 1 1 0 0 0
Control Word = 18 H Let Count = 04

If the GATE is 1, then the counting is enabled, otherwise it is disabled. Initially OUT value is
high and go low when count is at the last stage. The count is reloaded again for subsequent
clock pulse.

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

1. The output will be initially high.
2. The counting is triggered by the rising edge of the Gate.
3. The output will go low for one CLK pulse after the terminal count (TC).
MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)
Write control word using counter 0, read load LSB, Mode 5, Binary
Counter
Select Binary
Control Word Operation Mode Select
Counter Counter
0 0 0 1 1 0 1 0
Control Word = 1A H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Initially OUT value is high. The counting is triggered by the rising edge of the Gate (Clock pulse).
When initial count is expired the OUT becomes low for one clock pulse, then high again. After
writing the control word and the initial count, the counter will not be loaded until clock pulse
after one trigger.

3.4 PIN DIAGRAM OF 8253/54:

Figure: Pin diagram of 8253/8254

Intel 8253 is a 24 Pin programmable IC. It has three counters which work independently and
whose width is of 16-bits.
VCC and GND These are the Power supply and ground pins which 8253 uses +5V as power
supply

D7-D0 These are 8-bit bidirectional data bus lines, connected to the system data bus
for data transfer between 8085 and 8254.

̅̅̅̅
RD ̅̅̅̅=0, the microprocessor reads the data from the
It is active low pin. When 𝐑𝐃
Selected counter

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

̅̅̅̅̅
WR It is active low pin. When ̅̅̅̅̅ 𝐖𝐑=0, the microprocessor writes into
counter/control register i.e. writes control information/loading of counters.

A1 & A0 A1 & A0 pins are connected to the address bus. These pins are used for the
selection of counters and control word register.

A1 A0 OPERATION
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register

̅̅̅
CS ̅̅̅= 0 then 8254
This is an active low input signal, used to select the 8254 IC. If CS
will be active and take part in data transfer from/to 8085 otherwise 8254 will
be in the de-active state.

CLK0 Clock input for counter 0

CLK1 Clock input for counter 1

CLK2 Clock input for counter 2

Gate0 Controls function of counter 0 (i.e. gate terminals for triggering purpose)

Gate1 Controls function of counter 1 (i.e. gate terminals for triggering purpose)

Gate2 Controls function of counter 2 (i.e. gate terminals for triggering purpose)

Out0 Out0 is output terminal of counter 0

Out1 Out0 is output terminal of counter 1

Out2 Out0 is output terminal of counter 2

3.4.1 APPLICATIONS OF 8253/8254:

 To generate an accurate time delay
 As an event counter
 Square wave generator
 Rate generator
 Digital one shot

FEATURES OF 8253/54:
The most prominent features of 8253/54 are as follows:
 It has three independent 16-bit down counters.
 It can operate from DC up to 10MHz.
 The three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the status of the
counter.
 Counters can be programmed in six different modes.

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3.4.2 DIFFERENCE BETWEEN 8253 AND 8254:
Sl.
8253 8254
No.
1 Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
2 It uses N-MOS technology It uses H-MOS technology
3 Read-Back command is not available Read-Back command is available
Reads and writes of the same counter Reads and writes of the same counter can
cannot be interleaved. be interleaved.
(cannot perform read and write (interleaving reads and writes of the
4
operations on the same counter same counter is a synchronization
simultaneously or in an alternating technique that allows multiple tasks to
fashion) access and manipulate a counter)

3.5 8259 PROGRAMMABLE INTERRUPT CONTROLLER:

The 8259 is a programmable interrupt controller specially designed to work with Intel
microprocessor 8080, 8085, 8086, 8088. The main features of 8259 programmable interrupt
controller are given below:
1. It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins
on the processor in place of one INTR (in 8085)/INT (in 8086) pin.
2. The chip can vector an interrupt request anywhere in the memory map from 0000H to
FFFFH in 8085 microprocessor. However, all the eight interrupts are spaced at an interval
of either four or eight locations. This eliminates the major drawback of 8085 interrupts
in which all interrupts are vectored to memory location on page 00H i.e., TRAP, RST7.5,
RST6.5 and RST5.5 are vectored to memory locations 0024H, 003CH, 0034H and 002CH
respectively.
3. It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of
interrupts can be changed under running condition. Some of the desired lower priority
interrupts may be allowed to be acknowledged during the service of higher priority
interrupts.
4. Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5 and
RST5.5 interrupts of 8085.
5. The status of pending interrupts, in service interrupts, and masked interrupts can be read
at any time similar to RST interrupts of 8085.
6. The chip can be programmed to accept interrupt requests either as level triggered or edge
triggered interrupt request unlike your RST interrupts where some are edge triggered
and some are level triggered. However, all interrupts must be either level triggered or
edge triggered.
7. If required, nine 8259 can be cascaded in a master-slave configuration mode to handle 64
interrupt inputs. In this case, the interrupting devices send their interrupt requests either
to slave 8259 or to master 8259 directly. The slave 8259 send their interrupt to master
interrupt request inputs and the master will send a single interrupt to microprocessor
interrupt pin INTR/INT.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure: Block Diagram of 8259

INTERRUPT REQUEST REGISTER (IRR): The interrupts at IRQ input lines are handled by
Interrupt Request Register internally. IRR stores all the interrupt requests in it in order to serve
them one by one on the priority basis.
IN-SERVICE REGISTER (ISR): This register stores all the interrupt requests those are being
served, i.e. ISR keeps a track of the requests being served.
PRIORITY RESOLVER: This unit determines the priorities of the interrupt requests appearing
simultaneously. The highest priority is selected and stored into the corresponding bit of ISR
during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in
fixed priority mode. The priorities however may be altered by programming the 8259 in rotating
priority mode.

INTERRUPT MASK REGISTER (IMR): This register stores the bits required to mask the interrupt
puts. IMR operates on IRR at the direction of the Priority Resolver.

INTERRUPT CONTROL LOGIC: This block manages the interrupt and interrupt acknowledge
signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts
interrupt acknowledge (INTA) signal from CPU that causes the 8259 to release vector address on
to the data bus.

DATA BUS BUFFER: This tristate bidirectional buffer interfaces internal 8259 bus to the
microprocessor system data bus. Control words, status and vector information pass through
buffer during read or write operations.

READ WRITE CONTROL LOGIC: This circuit accepts and decodes commands from the CPU. This
also allows the status of the 8259 to be transferred on to the data bus.

CASCADE BUFFER/COMPARATOR: This block stores and compares the ID's of all the 8259 used
in the system. The three I/O pins CAS0-2 are outputs, when the 8259 is used as a master. The
same pins act as inputs when the 8259 is in slave mode. The 8259 in master mode sends the ID
of the interrupting slave device on these lines. The slave thus selected, will send its pre-
programmed vector address on the data bus during the next INTA pulse.

INTERRUPT SEQUENCE:
The powerful features of the 8259 in a microcomputer system are its programmability and the
interrupt routine addressing capability. The latter allows direct or indirect jumping to the specific
interrupt routine requested without any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU being used. The events occur as follows
in an 8085 system:
1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the
corresponding IRR bit(s).

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
2. The 8259 evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259 will also release a CALL instruction code
(11001101) onto the 8-bit Data Bus through its D7-0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the
CPU group.
6. These two INTA pulses allow the 8259 to release its preprogrammed subroutine address
onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the
higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte
CALL instruction released by the 8259. In the AEOI mode the ISR bit is reset at the end of
the third INTA pulse.
7. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end
of the interrupt sequence.
When the 8259 PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle
is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes
inactive immediately after the second INTA pulse. After an unspecified amount of time the INT
line is activated again to signify the higher priority interrupt waiting for service. This inactive
time is not specified and can vary between parts.

3.5.1 PIN DIAGRAM OF 8259:

Figure: Pin Diagram of 8259

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Bi-directional, tristate, buffered data lines. Connected to data bus directly or
D0-D7
through buffers
̅̅̅̅
RD Active low read control
̅̅̅̅̅
WR Active low write control
A0 Address input line, used to select control register
̅̅̅
CS Active low chip select
CAS0-2 Bi-directional,3-bit cascade lines. In master mode, PIC places slave ID no. on
these lines. In slave mode, the PIC reads slave ID no. from master on these lines.
It may be regarded as slave- select.
̅̅̅/EN
SP ̅̅̅̅ Slave program / enable. In non-buffered mode, it is SP-bar input, used to
distinguish master/slave PIC. In buffered mode, it is output line used to enable
buffers.
INT Interrupt line, connected to INTR of microprocessor
̅̅̅̅̅̅̅
INTA Interrupt ack, received active low from microprocessor
IR 0-7 Asynchronous IRQ input lines, generated by peripherals.

3.6 8251 USART & RS 232C:

USART stands for Universal Synchronous and Asynchronous Receiver Transmitter

Figure: Architecture of 8251 USART

1.Data Bus Buffer: It basically interfaces the 8251 with the internal system buses of the
processor.
The data bus buffer has 8-bit bidirectional data bus that allows the transfer of data bytes, status
or command word between the processor and external devices.

2.Read/Write Control Logic: This functional unit generates a control signal for the operation of
8251 according to the signal present in the control bus of the processor. Basically, it performs
decoding operation of the control signal produced by the processor, so that respective operation
can be performed by the USART.

The control formats for system operation is stored in control and command word registers
present in the read/write logic unit.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The signals handled by the read/write control logic unit are discussed below:
 CS: It is chip select. A low signal at this pin shows that processor has selected 8251 in order
to communicate with the peripheral devices.
 C/D: As the system has control, status and data register. So, when a high signal is present at
this pin then control or status register is addressed. While in case of low signal data register
is addressed.
 RD and WR: Both read and write are active low signal pins. A low signal at RD shows that the
processor is reading the control, status or data bytes from the 8251. While at WR indicates
the write operation over the data bus of 8251.
 CLK and RESET: CLK stands for clock and it produces the internal timing for the device. While
an active high signal at the RESET pin puts the 8251 in the idle mode.
3. Transmit Buffer: This unit is used to change the parallel data received from the CPU into serial
data by inserting the necessary framing information. Once the data is transformed into serial
form, then in order to transmit it to the external devices, it is provided to the TxD pin of the 8251.
This unit consists of 2 registers. These are as follows:
 Buffer register: Basically, the data provided by the processor is stored in the buffer register.
As we know that initially, the CPU provides parallel data to 8251. So, the processor loads the
parallel data to the buffer register. Further, this data is fed to the output register.
 Output register: The parallel data from the buffer register is fed to the empty output register.
This register changes the 8-bit parallel data into a stream of serial bits. Then further the serial
data is provided at the TxD pin so as to have its transfer to the peripheral device.
It performs both synchronous and asynchronous transmission and reception. Thus, in case of
asynchronous transmission, start and stop bit is added by the transmitter in order to notify the
external devices about the data transmission.
But in case of synchronous transmission, the clock signal is used thus there exists no need of
adding additional bits expect the parity bit (if required).

4. Transmit Control: As the name of the unit is itself indicating that it is controlling the
transmission action. And it does so by accepting and sending signals both externally and
internally.
The various control signal generated by this unit are as given below:
 TxRDY: It implies transmit ready. This signal is used to notify the processor that the buffer
register of the 8251 is empty and ready to accept the data.
 The status read operation is utilized by the processor in order to check the presence of the
signal.
 TxE: This stands for transmitter empty. It is an active high signal that indicates that the output
buffer is empty and thus data received from the processor can be loaded to it for conversion.
 TxC: It stands for transmitter clock and is an active low pin. It controls the rate of character
transmission by the USART.
 However, 8251 offers programmable clock rate. As by writing appropriate mode word in the
mode set register the clock division can be programmed.

5. Receive Buffer:
 This unit takes the serial data from the external devices, changes the serial data into the
parallel form so that it can be accepted by the processor. It consists of 2 registers: receiver
input register and buffer register.
 When the external device is ready to send the data to the 8251 then it sends a low signal
to the RxD line of the 8251. In asynchronous mode, once 8251 receives a low signal it
considers that signal as start bit of the data.
 So, once the start bit is successfully accepted by 8251, then it also receives the whole data
bits in serial form along with parity and stop bits.
 Once the data is received by the receiver input register then it converts the data bits in
parallel form and sends it to the receiver buffer register.
 In case of the synchronous mode of operation, according to the clock input, the external
device loads the serial data bits in the receiver input register. And on converting the serial
data to parallel format the receiver input register sends the data to the buffer register.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

6. Receiver Control
This unit controls the operation of the receiver buffer. It manages the data reception, along with
that it also detects the presence of false start bit, error in parity bit, framing errors etc.
 RxRDY: It stands for receiver ready. When this signal goes high then it indicates that the
receiver buffer register is holding the data and is ready to transfer it to the processor. Once
the CPU reads the data sent by the 8251 then this pin is reset.
 RxC: It stands for receiver clock. This clock signaling controls the rate at which the 8251
receives the data in the synchronous mode of operation. It is provided by the modem and is
equal to the baud rate. While asynchronous mode offers the clock rate as 1, 16 or 64 times of
the baud rate as it is programmable.
7. Modem Control: This unit of 8251 holds input and output control signals that simplify the
operation of the whole system. The control circuitry for handing various signals is provided by
the modem control unit. It includes DTS, RTS, DTR and CTS.
These are all active low signals.
 DSR: Stands for data set ready and the signal is used to check whether the data set is ready or
not when the processor is in the urge of communication.
 DTR: Implies data terminal ready. An active-low signal at this pin shows that the 8251 is now
ready to accept the data from the processor.
 RTS: It stands for the request to send. A low signal shows an assertion for data transmission.
 CTS: Clear to send. When 8251 receives a low signal at this pin then it clears all the data
present in the modem in order to allow further communication.

3.7 RS232C

Figure: DB-9 Male and Female Connector

Pin Description
1 Data carrier detect (DCD)
2 Received data (RxD)
3 Transmitted data (TxD)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (DSR)
7 Request to send (RTS)
8 Clear to send (CTS)
9 Ring indicator (Rl)

RS232 is an Interface and the protocol between DTE (data terminal equipment) and DCE (data
communication equipment) using serial binary data exchange. Here C is used for the current
version. Universal Asynchronous Data Receiver & Transmitter (UART), attached in a
motherboard, used in connection with RS232 for transmitting data to any serial device like
modem or printer from its DTE interface.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure: RS 232C
3.7.1 ELECTRICAL SPECIFICATIONS:
1. Voltages:
There can be two states in the signal level of RS232C pins.
 Mark state – It is the high bit which is represented by binary 1 and have negative
voltages. Its voltage limits for transmitting signal ranges from -5 to -15V. Its voltage
limits for receiving signals ranges from -3 to -25V.
 Space state – It is the low bit which is represented by binary 0 and have positive
voltages. Its voltage limits for transmitting signal ranges from +5 to +15V. Its voltage
limits for receiving signals ranges from +3 to +25V.

2. Cables and Wires:

The maximum cable length for RS232C is equals to 15.24 meters or equal to the capacitance of
2500pF. Limits for the impedance of wires ranges from 3 ohms to 7 ohms.

3. Data and Slew rates:

Rate of data transmission through RS232C is up to 20Kbps. The rate of change in signal levels
i.e. slew rate is up to 30V/microsecond.

4. Current:
Maximum current rating is 3Amps at the maximum operating voltage of 250V AC.

3.7.2 WORKING OF RS 232C:

Figure: RS 232C Connection and Signals

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
RS232C requires 25 pins connector for connecting DTE and DCE. Here is the list of pins and
signals of RS232C and the connection between DTE and DCE using drivers and receivers.

An RS232 pinout 9 pin cable features nine pins:

1. Data Carrier Detect: After a data terminal is detected, a signal is sent to the data set that is
going to be transmitted to the terminal.
2. Received Data: The data set receives the initial signal via the receive data line (RxD).
3. Transmitted Data: The data terminal gets a signal from the data set, a confirmation that
there is a connection between the data terminal and the data set.
4. Data Terminal Ready: A positive voltage is applied to the data terminal ready (DTR) line, a
sign that the data terminal is prepared for the transmission of data.
5. Signal Ground: A return for all the signals on a single interface, the signal ground (SG) offers
a return path for serial communications. Without SG, serial data cannot be transmitted
between devices.
6. Data Set Ready: A positive voltage is applied to the data set ready (DSR) line, which ensures
the serial communications between a data terminal and a data set can be completed.
7. Request to Send: A positive voltage indicates the request to send (RTS) can be performed,
which means the data set is able to send information to the data terminal without
interference.
8. Clear to Send: After a connection has been established between a data terminal and a distant
modem, a clear to send (CS) signal ensures the data terminal recognizes that communications
can be performed.
9. Ring Indicator: The ring indicator (RI) signal will be activated if a modem that operates as
a data set detects low frequency. When this occurs, the data terminal is alerted, but the RI
will not stop the flow of serial data between devices.

HANDSHAKING:
Before the actual data transfer, signals are transmitted from DTE to DCE in order to make
connections by a process known as handshaking. Following is the sequence of signal
handshaking:
 Initially, the computer activates RTS signal to modem when a data is transferred from
computer to modem.
 Modem in turn activates the DCD and then the CTS gets activated.
 Computer then sends data on TXD. After the data transmission is completed, the computer
deactivates the RTS which causes the modem to deactivate CTS.

APPLICATIONS:
It is used in establishing communication between the computer and embedded systems.
1. Due to its lower costs, it plays a vital role in CNC machines and servo controllers
2. Some microcontroller boards and PLC machines uses RS232C.
3. RS232C ports are used to communicate in headless systems in the absence of any network
connection.
4. Many Computerized Numerical Control Systems are containing RS232C port.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

UNIT
8051 Microcontroller Basics
SYLLABUS
8051 Microcontroller Basics: Inside the Computer, Microcontrollers and Embedded Processors,
Block Diagram of 8051, PSW and Flag Bits, 8051 Register Banks and Stack, Internal Memory
Organization of 8051, IO Port Usage in 8051, Types of Special Function Registers and their uses in
8051, Pins Of 8051. Memory Address Decoding, 8031/51 Interfacing with External ROM And RAM.
8051 Addressing Modes.

4.1 INTRODUCTION TO MICROPROCESSOR & MICROCONTROLLERS:

MICROPROCESSOR:

Fig. 4.1: Block diagram of Microprocessor.

 The microprocessor mainly contains CPU and general-purpose registers. It does not have
built-in RAM, ROM, I/O ports etc. on the chip.
 The microprocessors are commonly referred to as general-purpose microprocessor.
Examples:
Intel: 8086, 80286, 80386, 80486, Pentium etc.
Motorola: 68000, 68010, 68020, 68030 etc.

Note: The microprocessor is the heart of microcomputer.

4.1 MICROCONTROLLER:

Fig. 4.2: Block diagram of Microcontroller.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 A Microcontroller is a single integrated circuit (IC) that is capable of performing
specific task (e.g. washing machine, toy, Telephone, Printer, Video game etc.
 Microcontroller has a CPU (a microprocessor) and in addition it has built-in RAM, ROM,
Input/output devices, Timers/Counters on a single chip.
Examples: 8051, 8052, ARM processor etc.
Note:

Fig. 4.3: Shows applications of microcontroller

4.1.2 DIFFERENCE BETWEEN MICROPROCESSOR & MICROCONTROLLER:

Sl.
Microprocessor Microcontroller
No.
1

Fig.4.4: Block diagram of Fig.4.5: Block diagram of

microprocessor microcontroller
2 It contains only CPU. The RAM, ROM, Microcontroller has a CPU (a
Input/output devices, timers & counters microprocessor) and in addition it has built-
are separately interfaced. in RAM, ROM, Input/output devices,
Timers/Counters on a single chip.
3 Designers decides the amount of ROM, Fixed amount of on-chip ROM, RAM and
RAM and Input /output ports etc. Input /output ports etc.
4 It has many instructions to move data It has one or two instructions to move data
between memory & CPU. between memory & CPU.
5 It has one or two-bit handling instructions. It has many bit handling instructions. {ex:
CLRC, SETB P1.0 etc.,}
6 It has single memory for data & program. It has separate memory for data & program.

7 Access time for memory & I/o devices are Less access time for built – in memory & I/o
more. devices.
8 Large number of instructions set. Limited number of instructions set.
9 Few pins are multifunctional. More number of pins are multifunctional.
10 Very few bit handling instructions Many bit handling instructions
11 Design is very flexible Design is less flexible
12 Versatile. Not versatile.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
13 High cost Low cost
14 General-purpose applications. Single-purpose applications in which cost,
space & power are critical.
15 Examples: Intel: 8086, 80286, 80386, Examples:8051, 8052, ARM processor, PIC
80486, Pentium etc. Motorola: 68000, controllers etc.
68010, 68020, 68030 etc.

4.1.3 RISC & CISC

Reduced Instruction Set Computer (RISC)
 The Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes
a small, highly-optimized set of instructions, rather than a more specialized set of instructions
often found in other types of architectures.
 A simplified instruction set provides higher performance when combined with
microprocessor architecture capable of executing those instructions using fewer
microprocessor cycles per instruction.

Complex instruction set computing (CISC)

 The Complex instruction set computing architecture is a type of microprocessor design
contains a large set of computer instructions that range from very simple to very complex
and specialized.
 In CISC architecture, single instructions can execute several low-level operations such as
a load from memory, an arithmetic operation, and a memory store or capable of multi-
step operations or addressing modes within single instructions.

4.1.4 Difference between RISC and CISC processors:

Sl. No. RISC CISC
1 Only few instructions. Many instructions.
2 Highly pipelined. Not pipelined or Less pipelined.
Instruction interpreted by the micro
3 Instruction executed by the hardware.
program.
Complex instructions taking multiple
4 Simple instructions taking one cycle.
cycles.
5 Multiple register set. Single register set.
6 Very few instructions refer memory. Most of instructions may refer memory.
7 Fixed length instructions. Variable length instructions.
8 Complexity is in the compiler. Complexity is in the micro-program.
9 Few addressing modes. Many addressing modes.
Only Load/Store instructions access
10 Many instructions can access memory.
memory
Coding in RISC processor requires
Coding in CISC processor is simple i.e.
11 more number of lines. i.e. program size
program size is small
is large
12 It has multi-clock. It has single-clock.
Examples: PIC Microcontroller series
13 Examples: INTEL 80286, 80386 etc.
etc.

4.1.5 SELECTION OF MICROCONTROLLERS:

 List the points to be considered during the selection of a microcontroller for an
application.
The three criteria in choosing microcontrollers are as follows:
1. Microcontroller must perform the required task efficiently & cost effectively i.e.
 Speed

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 Amount of RAM & ROM on chip
 Power consumption
 The number of input pins & the timer on the chip
 Cost per unit
 Easy to upgrade
 Packaging (The number of pins & the packaging format. This determines the required
space & assembly layout.)

2. Availability of assembler, debuggers, complier, emulator, technical support and expertise

both in-house and outside.

3. Microcontroller availability in needed quantities both now and in the future.

4.1.6 EMBEDDED MICROCONTROLLERS

A microcontroller can be considered as a system with a processor, memory and
peripherals and can be used as an embedded system.
The majority of microcontrollers in use today are embedded in other machinery, such as
automobiles, telephones, home appliances, and peripherals for computer systems.

4.2 8051 ARCHITECTURES:

Analyze the architecture of 8051 microcontroller along-with a suitable block diagram.
AKTU Question Paper 2021-22, 10 MARKS
Describe the architecture of 8051 with neat diagram.
AKTU Question Paper 2022-23, 10 MARKS

Fig. 4.6: Block diagram of 8051 Microcontroller

Central processing unit (CPU):

 The 8051 Central processing unit consists of 8-bit arithmetic & Logic unit (ALU),
Registers: A, B, PSW, SP, 16-bit program counter & “Data pointer registers” (DPTR).

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 The ALU can perform arithmetic functions on 8-bit data i.e. addition, subtraction,
multiplication & division.
 Similarly, the logic unit perform logical operations such as AND, OR, NOT etc.

Register:
Register are used to store information temporarily, while the information could be
 a byte of data to be processed, or
 an address pointing to the data to be fetched
The majority of 8051 register are 8-bit registers. The most widely used registers are
 Accumulator (A), for all arithmetic and logic instructions.
 B, R0, R1, R2, R3, R4, R5, R6, R7.
 DPTR (data pointer), and PC (Program Counter).
A register (Accumulator):
 Accumulator is a 8 bit register & is widely used for arithmetic and data transfer
operations.
 The arithmetic operations are addition, subtraction, multiplication, division & Boolean bit
manipulating etc.
 The data transfer operation between the 8051 microcontroller and any external memory.
Note: It can be accessed through its SFR address of 0E0H.
B-register:
 The B-register is always used with the A-register to store 8-bit result of multiplication &
division operations
 It is used as temporary register where data may be stored.

Note: It can be accessed through its SFR address of 0F0H.

BUS:
Bus is a collection of wires which work as a communication channel or medium for transfer of
data. The 8051 has two types of buses:
1) Address Bus (16-bits) and
2) Data Bus (8-bits)

Program Counter (PC):

 PC is a16-bit register which points to the address of the next instruction to be executed.
 The PC is automatically incremented after every instruction byte is fetched.
 PC is the only register that does not have an internal address.
 When 8051 is RESET, the default value of PC is 0000 H.

Input-Output ports (I/O Ports):

 The 8051 has 4 Input/output ports i.e. PORT 1, PORT 2, PORT 3 and PORT 4 and each port
has 8 Input/output pins.
 It has total 32 Input/output pins and each pin can be configured as input or output pin.

Times & Counters

Fig. 4.7: Timer 0 & Timer 1

The 8051 has two 16-bit timers/counters, they can be used either as
 Timers to generate a time delay or as
 Event counters to count events happening outside the microcontroller.
The two timers are

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
i) Timer/Counter T0 and
ii) Timer/Counter T1
 Each register can be used either for Timer or counter and can be divided into Two 8-bit
registers called Timer Low (TL) and Timer High (TH).
4.2.1 STACK (8-bit)
Explain the organization of stack in 8051.
AKTU Question Paper 2021-22, 2 MARKS

 The stack is a section of RAM used by the CPU to store information temporarily. This
information could be data or an address.
 The register used to access the stack is called the SP (stack pointer) register. The stack
pointer in the 8051 is only 8 bits wide
 The storing of a CPU register in the stack is called a PUSH, and loading the contents of the
stack back into a CPU register is called a POP.

Data pointer (DPTR):

Fig. 4.8: DPTR

 DPTR is a 16-bit register, which holds a 16-bit address.

 DPTR can be split into 2 parts:
 DPL: Data pointer Low byte having internal address 82h.
 DPH: Data pointer high byte having internal address 83h.
 DPTR is very useful for string operations and look up table operations.

Memory Organization:
The 8051 microcontroller's memory is divided into
1) Internal RAM – 128 bytes: Used for temporarily storing and keeping intermediate
results and variables.
2) ROM – 4Kbytes: Used for permanent saving program being executed
Special Function Registers (SFR):
The operations of 8051 are done by a group of specific internal registers, each called a special
function Register (SFR).

Interrupts:
The 8051 Microcontroller has 6 interrupts:
RESET, INT0, INT1, Timer0 (TF0), Timer1 (TF1), Serial Port (TI/RI)

Program status (PSW) or Flag register:

Analyze the PSW of 8051 and also explain the relevant flag bits.
AKTU Question Paper 2021-22, 10 MARKS

Describe the different flags available in 8051 Program Status Word.

AKTU Question Paper 2020-21, 2 MARKS

CY AC F0 RS1 RS0 OV - P
D7 D6 D5 D4 D3 D2 D1 D0

Fig. 4.9: Program Status Word.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 The program status word (PSW) register is an 8-bit register. It is also referred to as the
flag register. The only 6 bits are used by the 8051. The two unused bits are user-definable
flags.
 The Carry (CY), Auxiliary carry (AC), Overflow (OV) and Parity (P) are called Conditional
flags because these flags indicate some conditions that resulted after an instruction was
executed.

Carry Flag (CY):

After performing arithmetic & logic operation if there is a carryout from the MSB (D 7 i.e. 7th-bit)
then CY = 1, otherwise CY = 0

Auxiliary carry Flag (AC): After performing arithmetic & logic operation if a carry from D3 to D4
bit then AC = 1, otherwise AC = 0.

FO: Available for user for general purpose

RS 1 & RS 0: These two bits are used to change Register Bank and are shown below in table.
Table: Register Bank Selector
RS1 RSO Register Bank Address
0 0 Bank 0 00H-07H
0 1 Bank 1 08H-0FH
1 0 Bank 2 10H-17H
1 1 Bank 3 18H-1FH

Overflow Flag (OV):

OV flag is set to 1 if either of the following two conditions occurs:
i) There is a carry from D6 to D7, but no carry out of D7 (CY = 0).
ii) There is a carry out from D7 bit (CY = 1) but no carry from D6 to D7 bit.

Parity Flag (P):

Parity flag indicates the number of 1’s present in the accumulator.
i) If the number of 1’s in the accumulator is odd then P = 1.
ii) If the number of 1’s in the accumulator is even then P = 0.

4.2.2 APPLICATIONS OF MICROCONTROLLERS:

The applications of microcontroller are:
Home Appliances Office Automobiles
TVs, VCR, Camcorders,
Remote Controller, Video
Telephones, Computers, Engine control, ABS, Air
games, Cellular phones,
Security Systems, Fax Machines, bags, Transmission control,
Telephones, Paging,
Copiers, Laser Printer, Color Climate Control, Keyless entry,
Camera, Answering
Printer etc. Trip computer etc.
machines, Musical
Instruments etc.

Example 4.1
Show the status of the CY, AC and P flag after the addition of 38H and 2FH in the following
instructions.
MOV A, #38H
ADD A, #2FH ; after the addition A=67H, CY=0
Solution:
1 1 1 1
38 0 0 1 1 1 0 0 0

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

+ 2F + 0 0 1 0 1 1 1 1

67 1 0 1 1 0 0 1 1 1

CY = 0 since there is no carry beyond the D7 bit

AC = 1 since there is a carry from the D3 to the D4 bit
P = 1 since the accumulator has an odd number of 1s (it has five 1s)

Example 4.2
Show the status of the CY, AC and P flag after the addition of 9CH and 64H in the following
instructions.
MOV A, #9CH
ADD A, #64H ; after the addition A=00H, CY=1
Solution:
1 1 1 1 1 1
9C 1 0 0 1 1 1 0 0
+ 64 + 0 1 1 0 0 1 0 0

1 00 1 0 0 0 0 0 0 0 0

CY = 1 since there is a carry beyond the D7 bit

AC = 1 since there is a carry from the D3 to the D4 bit
P = 0 since the accumulator has an even number of 1s (it has zero 1s)

Example 4.3
Show the status of the CY, AC and P flag after the addition of 88H and 93H in the following
instructions.
MOV A, #88H
ADD A, #93H ; after the addition A=1BH, CY=1
Solution:
1
66 1 0 0 0 1 0 0 0
+ 93 + 1 0 0 1 0 0 1 1

1 1B 1 0 0 0 1 1 0 1 1

CY = 1 since there is a carry beyond the D7 bit

AC = 0 since there is no carry from the D3 to the D4 bit
P = 0 since the accumulator has an even number of 1s (it has four 1s)

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.2.3 SPECIAL FUNCTION REGISTER (SFR):
The functions of any 5 SFR can be explained i.e. Accumulator, PSW, B register, Ports, Timers, DPTR
etc.

Fig. 4.10: Special Function Register.

 The operations of 8051 are done by a group of specific internal registers; each called a
Special Function Register (SFR) and its address ranges from 80H to FFH (80 bytes).
 There are 21 Special function registers (SFR) in 8051 microcontroller and these are
Register A, Register B, PSW, PCON etc. and each of these registers are of 1-byte size. Some
of these special function registers are bit addressable, while some are byte addressable.

4.2.4 FEATURES OF 8051 MICROCONTROLLER:

The Feature of 8051 is as follows
1) 8-bit CPU.
2) 4 Kbytes Internal ROM (Program Memory).
3) 128 bytes Internal RAM (Data Memory).
4) It has four 8-bit ports (Port 1, 2, 3 & 4), total 32 input/output lines.
5) Two 16-bit timers (T0 & T1).
6) One Full duplex serial communication port (data Transmitter/ Receiver).
7) Six Interrupt sources.
8) 16-bit program counter (PC) & data pointer (DPTR).
9) 8-bit Stack pointer.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.3 MEMORY ORGANIZATION:
Explain the internal memory organization of the microcontroller 8051.
AKTU Question Paper 2020-21, 10 MARKS

The 8051 microcontroller's memory is divided into

1. Data Memory (RAM) and
2. Program Memory (ROM).

Data Memory (RAM)

The Data Memory is used for temporarily storing data, keeping intermediate results and
variables used during the operation of the microcontroller.

The Data memory is of two types:

1. Internal RAM and
2. External RAM.

1. Internal RAM
The internal data memory consists of 256 bytes; these are divided into two parts:
i) Internal data RAM- 00H-1FH (128 bytes)
ii) Special function registers- 80H-FFH (128 bytes)

Internal data RAM

Fig. 4.11: Internal data RAM

The Internal data RAM is divided into 3 parts:

1) Register banks or General-purpose RAM
2) Bit addressable area

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
3) Scratch pad area

4.3.1 Register banks or General-purpose RAM

State the function of RS1 and RS0 bits in the flag register of Intel 8051 microcontroller.
AKTU Question Paper 2021-22, 2 MARKS
Explain the utility of the register banks in 8051.
AKTU Question Paper 2020-21, 2 MARKS
The selection of the register banks and their addresses are given below:
RS1 RS0 REGISTER BANK ADDRESS
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH
 The 8051 microcontroller consists of four register banks: Bank 0, Bank 1, Bank 2, Bank
3. Each register bank contains 8 registers of 1 byte. So total 32 register in register bank.
 To change the register bank, we have to set values of PSW register bits RS0 and RS1.
 Only one register bank is in use at a time.
 When 8051 is RESET, by default register bank 0 is selected.
Note:

Fig. 4.12: Register Banks

4.3.2 Bit addressable RAM
Describe the bit-addressable RAM space available in 8051.
AKTU Question Paper 2021-22, 2 MARKS

Fig. 4.13: Bit addressable RAM

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

 The area of bit addressable RAM is usually used to store bit variables.
 The address ranges from 20h to 2Fh (16 bytes) is bit-addressable RAM. Each bit can be
accessed from 00H to 7FH.
 The total bit addressable location are 16 bytes x 8 bits = 128 bits.
 Each bit can be accessed from 00H to 7FH.
 The programming using bit addressable area saves wastage of memory.

Note:
For example, Bit 0 of byte 20h has the bit address 0, and bit 7 of byte 2Fh has the bit address 7Fh).

Scratch pad area

 The upper 80 bytes are scratch pad area which is used for general purpose storing of data.
 The Scratch pad area is in the address range 30H to 7FH.
 The Scratch pad area can be used for stack memory.

Special function registers (SFR)

 The operations of 8051 are done by a group of specific internal registers; each called a
Special Function Register (SFR) and its address ranges from 80H to FFH (80 bytes).
 There are 21 Special function registers (SFR) in 8051 micro controller and these are
Register A, Register B, PSW, PCON etc. and each of these registers are of 1 byte size. Some
of these special function registers are bit addressable, while some are byte addressable.
 SFRs are used to control timers, counters, serial ports, I/O ports and peripherals.

Fig. 4.14: Special Function Register

4.3.3 External RAM

Fig. 4.15: External RAM

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 External data memory is 64 K Bytes read/write memory.
 The external data memory is indirectly accessed through a Data Pointer Register, it is
slower than access to internal data memory.

PROGRAM MEMORY:
The Program Memory is used for permanent saving program being executed.

Fig. 4.16: Program memory (ROM)

 The 8051 microcontroller has an on chip internal program ROM of 4K size and if needed
can add an external memory of size 60K maximum by interfacing i.e. total 64K size
memory.
 The Program memory accessed through EA pin. The EA is an active low input.

 When EA is connected to VCC i.e. EA =1, the 8051 can access 4 K bytes of internal ROM i.e.
0000H to 0FFFH and external ROM of 60 K bytes i.e. 1000H to FFFFH.
 When EA is connected to GND i.e. EA =0, then all program fetches are directed to external
ROM i.e. 0000H to FFFFH.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.4. I/O PORTS FUNCTIONS:
Discuss the significance of I/O ports along-with their dual roles in 8051.
AKTU Question Paper 2021-22, 10 MARKS

Fig.4.17: Pin diagram of 8051 showing I/O ports

Features of I/O ports
 An 8051 microcontroller has four I/O ports P0, P1, P2 & P3, where each port has 8 bits
i.e. total 32 I/O pins which can be configures as input or output ports.
 All the ports upon reset are configures as input, ready to use it as input port.
 To use any of these ports as an input port, it must be programmed by writing 1 to all
the bits.
 To use any of these ports as an output port, it must be programmed by writing 0 to all
the bits.
Examples: (Refer After reading instruction set)

i) Port 0 configured as output port

MOV A, #00H ; A=00H
MOV P0, A ; Make Port 0 as output port.

ii) Port 1 configured as input port

MOV A, #0FFH ; A=FFH
MOV P1, A ; Make Port 1 as input port.

iii) Port 2: P2.0 to P2.3 configured as input & P2.4 to P2.7 configured as output port.
MOV A, #0F0H ; A=F0H
MOV P2, A ; Make P2.0 to P2.3 as output & P2.4 to P2.7 as input pins.

4.4.1 PORT 0 (Pins 32-39)

 Port 0 occupies a total of 8 pins.
 To use the pins of PORT 0 as both input and output port, each pin must be connected
externally to 10 KΩ pull-up resistors because P0 is an open drain.
 Upon reset, Port 0 is configured as input port.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

Fig.4.18: Port 0 with 10 KΩ Pull-Up Resistors

 Port 0 is multiplexed address and data to save pins.

 Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data.
 When connecting an 8051 to an external memory, port 0 provides both address and
data.
 Port 0 provides the lower 8 bits address via A0 – A7

Example 4.4: (Refer After reading instruction set)

Write an Assembly Language Program (ALP) to toggle Port 0 continuously.

Solution:
The P0 is 1st loaded with 55H = 01010101 and its complement i.e. 10101010 = AAH is
given to P0 continuously.

BACK: MOV A, #55H

MOV P0, A
ACALL DELAY ; Delay routine not shown
MOV A, #0AAH
MOV P0, A
ACALL DELAY ; Delay routine not shown
SJMP BACK

Example 4.5: (Refer After reading instruction set)

Write an ALP to configure Port 0 first as an input port and then data is received from P0
and sent to P1.

MOV A, #0FFH ; A=FF hex

MOV P0, A ; make P0 an i/p port by writing it all 1s
BACK: MOV A, P0 ; get data from P0
MOV P1, A ; send it to port 1
SJMP BACK ; keep doing it

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.4.2 PORT 1 (Pins 1-8)
 Port 1 occupies a total of 8 pins.
 Port 1 does not need any pull-up resistors since it already has pull-up resistors
internally.
 Upon reset, Port 1 is configured as input port.

Example 4.6: (Refer After reading instruction set)

Write an ALP to continuously send out to port 0 the alternating value 55H and AAH.

MOV A, #55H
BACK: MOV P1, A
ACALL DELAY
CPL A ; complement register A
SJMP BACK

4.4.3 PORT 2 (Pins 21-28)

 Port 2 occupies a total of 8 pins.
 Port 2 does not need any pull-up resistors since it already has pull-up resistors
internally.
 Upon reset, Port 2 is configured as input port.
 In many 8051-based systems, P2 is used as simple I/O. Port 2 is also designated as
A8 - A15, indicating its dual function.

4.4.4 PORT 3 (Pins 10-17)

 Port 3 occupies a total of 8 pins.
 Port 3 does not need any pull-up resistors since it already has pull-up resistors
internally.
 Upon reset, Port 3 is configured as input port.
 Port 3 has the additional functions of proving some extremely important signals such as
interrupts.
Table 1 PORT 3 Alternative Functions
P3 bit Pin No. Function Description
 In 8051, the data is received from or transmitted to RXD &
P3.0 10 RxD TXD pins.
 The data is transmitted out of 8051 through the TXD line.
P3.1 11 TxD The data is received by 8051 through the RXD line.

External interrupt 0 and External interrupt 1

P3.2 12 ̅̅̅̅̅̅̅̅
𝐈𝐍𝐓 𝟎  The 8051 has two external hardware interrupts i.e.
Interrupt 0 & Interrupt 1. These two pins are used in
Timers/Counter operation. These Pins are triggered by
P3.3 13 ̅̅̅̅̅̅̅̅
𝐈𝐍𝐓 𝟏
external circuits.

Timer/counter 0 & Timer/counter 1

 The 8051 has two 16-bit Timers/ Counters. T0 -Timer0
P3.4 14 T0
register (16-bit) T1 -Timer1 register (16-bit).
 These can be used either as Timers to generate a time
delay or as counters to count events happening outside
the microcontroller.
P3.5 15 T1
Each 16-bit registers can be accessed as two separate 8-
bit registers.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
External data memory write & memory read. These are
̅̅̅̅̅ active low pins.
P3.6 16 𝐖𝐑
 When RD =0, microcontroller reads the data from
external RAM.
̅̅̅̅  When WR =0, microcontroller writes the data into
P3.7 17 𝐑𝐃
external RAM.

Note:
Table 2 RESET Values 0f 8051 ports
RESET Values
PORTS
Binary Hex
P0 11111111 FF
P1 11111111 FF
P2 11111111 FF
P3 11111111 FF
 Name the pins of 8051 used for external memory interfacing and list their functions.

Ans. The pins which are used for external memory interfacing are:
.
Refer pin details of 8051 to explain the functions of each pin.

4.5 8051 PIN DIAGRAM:

Illustrate the pin diagram of 8051 with the help of a suitable diagram and explain the
utility of the pins available in 8051.
AKTU Question Paper 2020-21, 10 MARKS

Fig. 4.19: Pin diagram of 8051 microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

The 8051 microcontroller is a dual in-line pin packages has 40 pins, out of which 32 pins are
assigned for Ports P0, P1, P2 and P4, where each port takes 8 pins.
The rest of the pins are VCC, GND, XTAL1, XTAL2, RST, EA , ALE/ PROG and PSEN .

Pin
Pin Name Description
No.

Port 1 Port 1 is an 8-pin bi-directional Port. Each of these pins can

1-8
(P1.0-P1.7) be configured as either input or output pins.

 When a pulse (square wave) is applied to this pin,

9 RST (Reset) microcontroller will terminate all its activities & reset.
 Program counter is loaded with 0000.

Port 3 is an 8-pin bi-directional Port with dual function.

Port 3
10-17 Each of these pins can be configured as either input or
(P3.0-P3.7)
output pins.

 In 8051, the data is received from or transmitted to RXD &

TXD pins.
10-11 RXD & TXD
 The data is transmitted out of 8051 through the TXD line.
 The data is received by 8051 through the RXD line.

 The 8051 has two external hardware interrupts i.e.

Interrupt 0 & Interrupt 1. These two pins are used in
12-13 INT 0 & INT 1 Timers/Counter operation.
 These Pins are triggered by external circuits.

 The 8051 has two 16-bit Timers/ Counters. T0 -Timer0

register (16-bit) T1 -Timer1 register (16-bit).
 These can be used either as Timers to generate a time
14-15 T0 & T1 delay or as counters to count events happening outside
the microcontroller.
 Each 16-bit registers can be accessed as two separate 8-
bit registers.

These are active low pins.

 When RD =0, microcontroller reads the data from

16-17 RD & WR external RAM.
 When WR =0, microcontroller writes the data into
external RAM.

 The 8051 has an on-chip oscillator but requires an

external clock to run it.
 A Quartz crystal oscillator is connected to inputs XTAL1 &
XTAL2 with two capacitors having values 30PF.
18-19 XTAL2 & XTAL1
 If an external frequency (from AFO) has to be applied,
then it must be applied between XTAL1 & ground. XTAL2
must be left open.
 Oscillator frequency may vary from 10MHz to 40MHz.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
20 VSS It is a ground pin i.e. VSS=0V

 Port 2 is an 8-pin bi-directional Port.

Port 2  If external memory is not used, these pins can be used as
21-28 either input or output pins.
(P2.0-P2.7)  If external memory is used then the higher address i.e.
A8-A15 will appear on this port.

 PSEN is an active low input to 8051.

29 PSEN (program store  PSEN is an output pin used to access the external
Enable) program memory (ROM). This pin is connected to the
OE pin of the ROM.

 ALE is an output pin. It is used for demultiplexing the

address and the data bus.
ALE/ PROG  When ALE=1, Port 0 is providing lower order address
30 (A0-A7).
(Address Latch
 When ALE=0, Port 0 is used as data lines (D0-D7).
Enable)
 This pin also has program pulse input PROG during
EEPOM programming.

 EA is an active low input to 8051.

 When EA is connected to VCC i.e. EA =1, the 8051 can
EA /VPP (External
access 4 K bytes of internal ROM i.e. 0000 H to 0FFF H and
31 Access
external ROM of 60 K bytes i.e. 1000 H to FFFF H.
Enable/Programming
supply voltage)  When EA is connected to GND i.e. EA =0, then all program
fetches are directed to external ROM i.e. 0000 H to
FFFF H.

 Port 0 is an 8-pin bi-directional Port.

 Port 0 is also multiplexed low order address and data bus
i.e. AD0-AD7.
Port 0  If external memory is not used, then these pins can be
(P0.0-P0.7) used as either input or output pins.
32-39
 If external memory is used then the lower address and
data lines AD0-AD7 will appear on this port.
 When ALE=1, Port 0 is providing lower order address
(A0-A7).
 When ALE=0, Port 0 is used as data lines (D0-D7).

40 VCC DC power supply +5V is connected to this pin.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.6 EXTERNAL MEMORY (ROM & RAM) INTERFACING:
4.6.1 Interfacing External Data

Fig. 4.20: Interfacing 8051 with External Data Memory

 To address up to 64 K Bytes of external data memory then the hardware should be

configured as shown in figure 1.9.1.
 The MOVX instruction is used to access the external data memory.
 The Port 0 outputs the low address (A0 to A7) while Port 2 outputs the high address
(A8 to A15).
 The Port 0 is a multiplexed address/data bus. The LATCH is used to demultiplex address
and data bus. The LATCH will be enabled when ALE=1, so output of LATCH has lower
order address A0-A7 as shown in Fig 1.9.1.
 The RD & WR pins are used when a RAM has to be accessed.
 When RD = 0, a data byte can be read from a RAM location.
 When WR = 0, a data byte can be written into a RAM location.

4.6.2 INTERFACING EXTERNAL ROM:

Fig. 4.21: Interfacing 8051 with External Program Memory.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 To address up to 64 K Bytes of external Program memory then the hardware should be
configured as shown in figure 1.9.2.
 The Port 0 outputs the low address (A0 to A7) while Port 2 outputs the high address
(A8 to A15).
 The Port 0 is a multiplexed address/data bus. The LATCH is used to demultiplex address
and data bus. The LATCH will be enabled when ALE=1, so output of LATCH has lower
order address A0-A7 as shown in Fig 1.9.2.
 The MOVC instruction is used to get data from code space.
 The EA is an active low input pin. When EA is connected to GND i.e. EA =0, then all
program fetches are directed to external ROM i.e. 0000 H to FFFF H.
 The PSEN is an active low pin used to access the external program memory (ROM),
PSEN pin is connected to the OE pin of the ROM chip.
 To access the program code, EA must be grounded then PSEN will go low to enable the
external ROM to place a byte of program code on the data bus.

Example 4.8:
Interface 4K RAM to 8051 Microcontroller

Fig. 4.22: Interface 4K RAM to 8051 Microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Example 4.9:
Interface 4K ROM to 8051 Microcontroller

Fig. 4.23: Interface 4K ROM to 8051 Microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Example 4.10:
Interface 4K ROM & 4K RAM to 8051 Microcontroller

Fig. 4.24: Interface 4K ROM & 4K RAM to 8051 Microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Example 4.11:
Interface 8K RAM to 8051 Microcontroller

Fig. 4.25: Interface 8K RAM to 8051 Microcontroller

Example 4.12:
Interface 8K ROM to 8051 Microcontroller
 Describe the method of interfacing 8K PROM to 8051 microcontroller
10-Mark

Fig. 4.26 a: Interface 8K ROM to 8051 Microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Interface 8K DATA ROM to 8051 Microcontroller

Fig. 4.26 b: Interface 8K DATA ROM to 8051 Microcontroller

Interface 8K of single external ROM for both CODE and DATA.

Fig. 4.26 c: Interface 8K of single external ROM for both CODE and DATA

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Example 4.13:
Interface 8K EPROM & 4K RAM to 8051 Microcontroller

Fig. 4.27: Interface 8K EPROM & 4K RAM to 8051 Microcontroller

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
Example 4.14:
Interface 16K EPROM & 8K RAM to 8051 Microcontroller.

Fig. 4.28: Interface 16K EPROM & 8K RAM to 8051 Microcontroller.

Example 4.15: Interfacing 8 Kbyte RAM and 8 Kbyte ROM to 8051 microcontroller.

Fig. 4.29: Interfacing 8 Kbyte RAM and ROM with 8051.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics

Example 4.16: Interfacing 8 Kbyte RAM and 8 Kbyte ROM to 8051 microcontroller.

Fig. 4.30: Interfacing 8 Kbyte RAM and ROM with 8051.

Example 4.17: Interfacing 16 Kbyte DATA RAM, DATA ROM and PROM to 8051
microcontrollers.

Fig. 4.31: Interfacing 16 Kbyte DATA RAM, DATA ROM and PROM to 8051
microcontrollers.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.7 8051 ADDRESSING MODES:
Explain the various addressing modes of 8051 microcontroller.
AKTU Question Paper 2022-23, 10 MARKS

Illustrate the addressing modes of 8051 microcontroller. Support your answer with
suitable examples.
AKTU Question Paper 2021-22, 10 MARKS
Compare the immediate and direct addressing mode in context to 8051 instruction set.
AKTU Question Paper 2020-21, 2 MARKS

The CPU can access data in various ways. The data could be in a memory or in register or it may
be an immediate value (CONSTANT). The various ways of accessing these data are called
addressing mode.
There are 5 addressing modes in 8051
1. Immediate addressing mode
2. Resister addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Indexed addressing mode.

Immediate addressing mode

 In Immediate addressing mode, the source operand is a constant. The immediate data
must be preceded by the pound sign, “#”.
 This addressing mode can load information into any registers, including 16-bit DPTR
register and 8051 ports.
Examples:
MOV R1, #50 ;load 50 into R1
MOV B, #50H ;load 50H into B
MOV A, #35H ;load 35H into A
MOV DPL, #66H
MOV DPH, #55H ; DPTR=5566H
MOV DPTR, #5566H ;DPTR=5566H
;This is the same as above
MOV DPTR, #69925 ;illegal Value because value is > 65535 (FFFFH)
MOV P1, #35H ;load 35H into Port 1

Resister addressing mode

 Resister addressing mode Use registers to hold the data to be manipulated.
 The source and destination registers must match in size.
 The movement of data between Rn registers is not allowed.
Examples:
MOV A, R1 ; copy contents of R1 into A
MOV R3, A ; copy contents of A into R3
ADD A, R2 ; add contents of R2 to A
ADD A, R0 ; add contents of R0 to A
MOV R5, A ; save accumulator in R5
MOV R7, DPL ; Lower byte of DPTR copied to R7
MOV R6, DPH ; Higher byte of DPTR copied to R7

MOV DPTR, A ; will give an error because A=8 bit and DPTR= 16-bit
MOV R4, R7 ; is invalid

Direct addressing mode

 The entire 128 bytes of RAM can be accessed using direct addressing mode. The RAM
locations 30-7FH are most often used.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 The register bank locations are accessed by its address or by its register names.
 In this instruction address is given as a part of the instructions.
Examples:
MOV R1, 30H ; Save content of RAM location 30H in R1
MOV 50H, A ; Save content of A in RAM location 50H
MOV A, 4 ; is same as copying R4 into A
MOV A, R4 ; copy R4 into A
NOTE:
 The “#” sign distinguishes between the immediate and direct addressing mode. The
absence of the “#” sign is the direct addressing mode.

Register indirect addressing mode

 In Register indirect addressing mode, a register is used to hold the address of the data
(as a pointer to the data).
 Only register R0 and R1 are used for this purpose. The R2 – R7 cannot be used to hold the
address of an operand located in RAM.
 When R0 and R1 hold the addresses of RAM locations, they must be preceded by the “@”
sign.
Examples:
MOV A, @R1 ; move contents of RAM whose address is held by R1 into A
MOV @R0, B ; move contents of B into RAM whose address is held by R0
MOV @R1, 04H ; move contents of 04H into RAM whose address is held by R1
MOV 30H, @R1 ; move contents of RAM whose address is held by R1 into RAM
30H
MOVC A, @A+DPTR ; the contents of A are added to the 16-bit register DPTR to form
the 16-bit address of the needed data.

Advantages
 The advantage is that it makes accessing data dynamic rather than static as in direct
addressing mode. Looping is not possible in direct addressing mode.
Limitations
 R0 and R1 are the only registers that can be used for pointers in register indirect
addressing mode Since R0 and R1 are 8 bits wide, their use is limited to access any
information in the internal RAM.
 The accessing of externally connected RAM or on-chip ROM need 16-bit pointer. In such
case, the DPTR register is used.

NOTE:
 Indexed addressing mode is widely used in accessing data elements of look-up table
entries located in the program ROM.

Indexed addressing mode

 Indexed addressing mode is widely used in accessing data elements of look-up table
entries located in the program ROM space.
 Only program memory can be accessed in the index addressing. Either the DPTR or PC
can be used as an index register.
Examples:
MOVC A, @A+DPTR
MOVC A, @A+PC

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
4.8 SPECIAL FUNCTION REGISTERS (SFR’s):
Discuss the significance of following SFR’s of 8051- PSW, TCON.
AKTU Question Paper 2022-23, 10 MARKS

Fig. 4.32 a: SFR Register

In 8051 microcontroller there are 21 Special function registers (SFR) and this includes
Register A, Register B, Processor Status Word (PSW), PCON etc. There are 21 unique locations for
these 21 special function registers and each of these registers is of 1-byte size.
The 21 SFR of 8051 Microcontroller are categorized into seven groups these are:
 CPU Registers: A and B Register
 Status Register: PSW (Program Status Word) Register
 Pointer Registers: DPTR (Data Pointer: DPL, DPH) and SP (Stack Pointer) Registers
 I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port 3)
 Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP Registers
 Peripheral Data Registers: TL0, TH0, TL1, TH1 and SBUF Registers

Accumulator (A register):
 It is an 8-bit register.
 It holds a data and receives the result of the arithmetic instructions.
 ACC is usually accessed by direct addressing and its physical address is E0H. Accumulator
is both byte and bit addressable. if you want to access the second bit (i.e. bit 1), you may
use E1H and for third bit E2H and so on.

Fig. 4.32 b: Accumulator Register

B Register:
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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
 It is 8-bit register.
 It is bit and byte-addressable register.
 You can access 1-bit or all 8-bits by a physical address F0 H. Suppose to access a bit 1, we
have to use F1 H.
 The B register is only used for multiplication and division arithmetic operations.

Fig. 4.33: B Register

PSW (Program Status Word) Register:

The PSW (Program Status Word) Register is also called as Flag Register. It is one of the important
SFRs in 8051 microcontrollers. It is also an 8-bit register. It consists of Flag Bits or status bits that
reflect the current state of the CPU.
PSW flag register is both bit and byte addressable. The physical address of PSW starts from D0H.
The individual bits are accessed by using bit address D1, D2 … D7. The two unused bits are user-
defined flags. Four of the flags are called conditional flags, which means that they indicate a
condition which results after an instruction is executed. These four are CY (Carry), AC (auxiliary
carry), P (parity), and OV (overflow).

Fig. 4.34: PSW Register

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
PSW Register Bits

Timer/Counter Register:
 The 8051 has two 16-bit Programmable timers / counters (Timer 0 – Timer 1).
 Which can be used either as timer to generate a time delay or as counter to count events
happening outside the microcontroller.
 The Counters and Timers in 8051 microcontrollers contain two special function
registers: TMOD (Timer Mode Register) and TCON (Timer Control Register).

TMOD Register:
 TMODE register is an 8-bit register.

Fig. 4.35: TMOD Register

TMOD Register:
 Gate: when Gate control is set. Timer/counter is enable only while the INTx pin is high
and the TRx control pin is set. When it is cleared, the timer is enabled whenever the TRx
control bit is set.
 C/T: The Timer or counter selection. When cleared for timer operation (input from
internal system clock). Set for counter operation (input from Tx input pin).
 Mode selects bits of TMODE register: The M1 and M0 are mode select bits, which are
used to select the timer operations. There are four modes to operate the timers.

Mode Selection Bits of TMOD Register

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
TCON Register:
Timer Control or TCON is an 8-bit Register and is used to start or stop the Timers of 8051
Microcontroller. It also contains bits to indicate if the Timers has overflowed. The TCON SFR also
consists of Interrupt related bits.

Fig. 4.36: TCON Register

SP (Stack Pointer):
 The stack is a portion of a RAM Used by the CPU to store data or memory address on
temporary basis.
 The stack pointer register is used to access the stack is known as SP register. The stack
pointer register is 8-bits wide. It can take a value of 00 to FFH. The RAM memory location
08H is the first location used for the stack. When the 8051 microcontroller is initialized,
the SP register contains the value 07H.
 If we want to store CPU register data into the stack this is known as PUSH operation and
if we getting the data from stack back into a CPU register this is known as a POP operation.

Fig. 4.37: SP Register

PC (program Counter):
 It is a 16-bit register. It is use to hold the address of the memory location from where the
next instruction to be fetched.
 When the 8051 initializes PC starts at 0000h and it is automatically is incremented every
time after an instruction is executed. (So, in this way PC maintain the sequence of program
execution).
 Due to this the width of the PC decides the max program length in bytes.

IE (Interrupt Enable):
The IE or Interrupt Enable Register is used to enable or disable individual interrupts. If a bit is
SET, the corresponding interrupt is enabled and if the bit is cleared, the interrupt is disabled. The
Bit7 of the IE register i.e. EA bit is used to enable or disable all the interrupts.

IP (Interrupt Priority):
The IP or Interrupt Priority Register is used to set the priority of the interrupt as High or Low. If
a bit is CLEARED, the corresponding interrupt is assigned low priority and if the bit is SET, the
interrupt is assigned high priority

PCON (Power Control):

The PCON or Power Control register, as the name suggests is used to control the 8051
Microcontroller’s Power Modes and is located at 87H of the SFR Memory Space. Using two bits in
the PCON Register, the microcontroller can be set to Idle Mode or Power down Mode.

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Microprocessor & Microcontroller Unit-4: 8051 Microcontroller Basics
SCON (Serial Control):
The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s Serial Port. It is
located as an address of 98H. Using SCON, we can control the Operation Modes of the Serial Port,
Baud Rate of the Serial Port and Send or Receive Data using Serial Port.

DP (Data pointer register):

 The data pointer is a 16-bit register used to hold the 16-bit address of data memory. This
can also be used as two 8-bit register namely DPH and DPL. Data Pointer can be used as
a single 16-bit register (as DPTR) or two 8-bit registers (as DPL and DPH).
 The 8-bit data pointers are used for accessing internal RAM and SFR. The 16-bit data
pointer is used for accessing external data memory.
 The contents of data pointer are programmable using instructions. It is used by
the 8051 to access external memory using the address indicated by DPTR.

Fig. 4.38: Data Pointer Register

Port Registers:
8051 microcontrollers have 4 bidirectional I/O ports. Port 0, Port 1, Port 2 and Port 3 (P0, P1, P2
and P3). Which can be work as input or output port. Each port having 8-bits. Hence, total 32
input/output pins allow the microcontroller to communicate with outside world means this port
allow to be connected with the peripheral devices.

Fig. 4.39: Input output Port Register

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

UNIT
Assembly programming and
instruction of 8051
SYLLABUS

Assembly programming and instruction of 8051: Introduction to 8051 assembly programming,

Assembling and running an 8051 program, Data types and Assembler directives, Arithmetic, logic
instructions and programs, Jump, loop and call instructions, IO port programming. Programming
8051 Timers. Serial Port Programming, Interrupts Programming,
Interfacing: LCD & Keyboard Interfacing, ADC, DAC & Sensor Interfacing, External Memory
Interface, Stepper Motor and Waveform generation.

5.1: PROGRAMMING 8051 TIMERS

The 8051 has two16-bit timers/counters, they can be used either as
 Timers to generate a time delay or
 Event counters to count events happening outside the microcontroller.
The two timers are
i) Timer/Counter T0 and
ii) Timer/Counter T1

Fig.: Timer 0 & Timer 1

 Each register can be used either for Timer or counter and can be divided into Two 8-bit
registers called Timer Low (TL) and Timer High (TH) as shown in Fig.
 Both timers 0 and 1 use the same register, called TMOD (timer mode), to set the various
timer operation modes.
 TCON is a bit-addressable 8-bit register used for timer control.

5.2 Timer Resistors

5.2.1: TIMER 0 Register:

Fig. 5.1: Timer 0 register

 The 16-bit register of Timer 0 is accessed as low byte and high byte.
 The low byte register is called TL0 and the high byte register is called TH0.
 These registered can be accessed like any other registers such as A, B, R0 to R7 etc.
Example:
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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
MOV TLO, # 55H ; Move the value 55H into TL0 register
MOV R1, TL0 ; Copy the content of TL0 into R1 register.

5.2.2: TIMER 1 Register:

Fig. 5.2: Timer 0 register

 The 16-bit register of Timer 1 is accessed as low byte and high byte.
 The low byte register is called TL1 and the high byte register is called TH1.
 These registered can be accessed like any other registers such as A, B, R0 to R7 etc.
Example:
MOV TH1, # 55H ; Move the value 55H into TH1 register
MOV R1, TH1 ; Copy the content of TH1 into R1 register.

5.3: TMOD (Timer Mode) register

 Timer 0 & Timer 1 use the same register, called TMOD, to set the various timer operation
modes.
 TMOD is an 8-bit register in which, the lower 4 bits are for Timer 0 and the upper 4 bits
are for Timer 1.

Fig.5.3: TMOD register

5.3.1: FOR TIMER 1:
Bit 7: Gate (Gating control)
 When GATE=1, the Timer 1 can be started/stopped by the external sources i.e.
hardware control. The Timer 1 will start only when GATE=1, TR1 =1 & ̅̅̅̅̅̅̅
𝐈𝐍𝐓𝟏=1.
 When GATE=0, the Timer 1 can be started/stopped by the software control
(instructions). The Timer 1 will start only when GATE=1 & TR1 =1 (regardless of the
̅̅̅̅̅̅̅ pin).
State of 𝐈𝐍𝐓𝟏

Bit 6: C/T (Timer or Counter selected)

 When C/𝐓 ̅ =0, Timer mode selected. In Timer mode, Timer 1 will increment every
machine cycle.
 When C/𝐓 ̅ =1, counter mode selected. In counter mode, Timer1 will count events
(pulses) on T1 pin (P3.5).

Bit 5 & 4: M1 & M0 (Mode bit 1 & Mode bit 0)

T1M1 T1M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
5.3.2: FOR TIMER 0:
Bit 3: Gate (Gating control)
 When GATE=1, the Timer 0 can be started/stopped by the external sources i.e.
̅̅̅̅̅̅̅=1.
hardware control. The Timer 0 will start only when GATE=1, TR0 =1 & 𝐈𝐍𝐓𝟎
 When GATE=0, the Timer 0 can be started/stopped by the software control
(instructions). The Timer 0 will start only when GATE=0 & TR0 =1 (regardless of the
̅̅̅̅̅̅̅ pin).
State of 𝐈𝐍𝐓𝟎

̅ (Timer or Counter selected)

Bit 2: C/𝐓
 When C/𝐓 ̅ =0, Timer mode selected. In Timer mode, Timer 0 will increment every
machine cycle.
 When C/𝐓 ̅ =1, counter mode selected. In counter mode, Timer 0 will count events
(pulses) on T0 pin (P3.4).

Bit-1 & 0: M1 & M0 (Mode bit 1 & Mode bit 0)

T0M1 T0M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

Note: TMOD register configuration for Timer 0/1 in Mode 1 & Mode 2.

Table 5.1: TMOD register configuration

TMOD
Timer & Mode TMOD Register
value

Timer 0, Mode 1 01H

Timer 1, Mode 1 10H

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Timer 0, Mode 2 02H

Timer 1, Mode 2 20H

Problem.5.1:
Find the values of TMOD to operate as timers in the following modes.
(a) Mode 1 Timer 1
(b) Mode 2 Timer 0, Mode 2 Timer 1
(c) Mode 0 Timer 1
Solution:
a) TMOD is 00010000 = 10H The gate control bit and C/T bit are made 0, and the unused
timer (Timer 0 bit is also 0)
b) TMOD is 01010010 = 52H
c) TMOD is 00000000H = 00H

Problem.5.2:
Indicate which mode and which timer are selected for each of the following
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV TMOD, #12H
Solution:
We convert the value from hex to binary
(a) TMOD = 00000001, mode 1 of timer 0 is selected.
(b) TMOD = 00100000, mode 2 of timer 1 is selected.
(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1 are selected.

Problem.5.3:
Find the timer’s clock frequency and its period for various 8051-based system, with the
crystal frequency 11.0592 MHz when C/T bit of TMOD is 0.

Solution:

Fig.5.4: Divide by 12 circuit

We know that in 8051, XTAL oscillator frequency is divide by 12 circuit as shown in figure
1
Frequency f = 12 × 11.0592MHz = 𝟗𝟐𝟏. 𝟔 𝐊𝐇𝐳
1 1
Time T = f = 921.6KHz = 𝟏. 𝟎𝟖𝟓 𝝁𝐬

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Machine Cycle

Fig.5.5: Machine cycle

In 8051, two pulses constitute a state and machine cycle is made up of six states. Some
instructions may require more than one machine cycle.
The time required to execute an instruction is given by

C × 12 d
T=
f
Where, T is the time for instruction to be executed
f is the crystal frequency and
C is the number of machine cycles.

Problem 5.4:
For 8051 microcontroller, find the time taken for an instructions which takes
i) 1 Machine cycle
ii) 2 Machine cycle
iii) 4 Machine cycles
Solution:
𝐂×𝟏𝟐 𝐝 1×12
i) 𝐓 = = 6 = 𝟏. 𝟎𝟖𝟓 𝝁𝐒𝐞𝐜
𝐟 11.0592×10
𝐂×𝟏𝟐 𝐝 2×12
ii) 𝐓 = = = 𝟐. 𝟏𝟕𝟎 𝝁𝐒𝐞𝐜
𝐟 11.0592×106
𝐂×𝟏𝟐 𝐝 4×12
iii) 𝐓 = 𝐟 = 11.0592×106 = 𝟒. 𝟑𝟒𝟎 𝝁𝐒𝐞𝐜

5.4: TCON Register (Timer Control Register)

 TCON (timer control) register is a bit-addressable 8-bit register.

 The upper four bits (bit 4 to bit 7) are used to store the TF and TR bits of both timer 0 & 1.

Fig. 5.6: TCON Register

 The lower four bits (bit 0 to bit 3) are set aside for controlling the interrupt bits.
Bit Bit Function
Bit
Name
7 TF1 Timer 1 Overflow flag.
TF1=1, when timer 1 register overflows.
TF1=0, when processor vectors to execute interrupt service routine
located at program address 001Bh.

6 TR1 Timer 1 run control bit. Set/Cleared by software.

TR1=1, Timer 1 is turned on (i.e. enable timer to count)
TR1=0, Timer 1 is off (i.e. halt timer)

5 TF0 Timer 0 Overflow flag.

TF0=1, when timer 0 register overflows.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
TF0=0, when processor vectors to execute interrupt service routine
located at program address 000Bh.

4 TR0 Timer 0 run control bit. Set/Cleared by software.

TR0=1, Timer 0 is turned on (i.e. enable timer to count)
TR0=0, Timer 0 is off (i.e. halt timer)

3 IE1 External interrupt 1 Edge flag.

̅̅̅̅̅̅̅).
Set to 1 when a high-to-low edge signal is received on port 3.3 (𝐈𝐍𝐓𝟏
Cleared when processor vectors to interrupt service routine at program
address 0013h. (Not related to timer operations).

2 IT1 External interrupt 1 signal type control bit.

Set to 1 by program to enable external interrupt 1 to be triggered by a
falling edge signal.
Set to 0 by program to enable a low-level signal on external interrupt 1 to
generate an interrupt.

1 IE0 External interrupt 0 Edge flag.

̅̅̅̅̅̅̅).
Set to 1 when a high-to-low edge signal is received on port 3.2 (𝐈𝐍𝐓𝟎
Cleared when processor vectors to interrupt service routine at program
address 0003h. (Not related to timer operations).

0 IT0 External interrupt 0 signal type control bit.

Set to 1 by program to enable external interrupt 1 to be triggered by a
falling edge signal.
Set to 0 by program to enable a low-level signal on external interrupt 0 to
generate an interrupt.

Note: The instructions used for Timer Control Registers (TCON)

INSTRUCTIONS USED FOR TIMER 0

SETB TR0 SETB TCON.4

CLR TR0 CLR TCON.4

OR
SETB TF0 SETB TCON.5

CLR TF0 CLR TCON.5

INSTRUCTIONS USED FOR TIMER 1

SETB TR1 SETB TCON.6

CLR TR1 CLR TCON.6

OR
SETB TF1 SETB TCON.7

CLR TF1 CLR TCON.7

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
5.5: TIMER MODES:
 In 8051, timer can operate in any one of four modes: Mode 0, Mode 1, Mode 2 & Mode 3.
 The M1 & M0 bits in TMOD register determines the type of mode.
 The C/𝐓
̅ =0, Timer mode selected.

5.5.1: TIMER IN MODE 1:

The following are the characteristics and operations of mode1:
1. It is a 16-bit timer; therefore, it allows value of 0000 to FFFF H to be loaded into the timer’s
register TL and TH
2. After TH and TL are loaded with a 16-bit initial value, the timer must be started. This is
done by SETB TR0 for timer 0 and SETB TR1 for timer 1
3. After the timer is started, it starts to count up
 It counts up until it reaches its limit of FFFF H.
 When it rolls over from FFFF H to 0000, it sets high a flag bit called TF (timer flag).
Each timer has its own timer flag: TF0 for timer 0, and TF1 for timer 1. This timer flag
can be monitored
 When this timer flag is raised, one option would be to stop the timer with the
instructions CLR TR0 or CLR TR1, for timer 0 and timer 1, respectively
4. After the timer reaches its limit and rolls over, in order to repeat the process. The registers
TH and TL must be reloaded with the original value, and TF must be reset to 0.

TIMER 0 IN MODE 1:

Fig.5.7: Block diagram of Timer 0 in Mode 1

̅ =0, TMOD=01H & TCON=10H

Note: C/𝐓

Steps to program Timer 0 in Mode 1

1. Load the TMOD register with 01 H to operate in Timer 0 in Mode 1
2. Load registers TL0 and TH0 with initial count value (16-bit value i.e. 0000H to FFFF H)
3. Start the Timer 0 by setting TR0 in TCON register (SETB TR0)
4. Timer 0 started and it counts until it reaches its maximum value i.e. FFFF H and it rolls
over to 0000H. Now it will set the TF0 bit in TCON register.
Keep monitoring TF0 with the “JNB TF0, here” instruction until TF0 is set.
5. Stop the Timer 0 (Set TR0=0)
6. Clear TF0 flag for the next round.
7. Go back to Step 2 to load TH0 and TL0 again.

TIMER 1 IN MODE 1:

Fig. 5.8: Block diagram of Timer 1 in Mode 1

̅ =0, TMOD=10H & TCON=40H

Note: C/𝐓

Steps to program Timer 1 in Mode 1

1. Load the TMOD register with 10 H to operate in Timer 1 in Mode 1
2. Load registers TL1 and TH1 with initial count value (16-bit value i.e. 0000H to FFFF H)
3. Start the Timer 1 by setting TR1 in TCON register (SETB TR1)

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
4. Timer 1 started and it counts until it reaches its maximum value i.e. FFFF H and it rolls
over to 0000H. Now it will set the TF1 bit in TCON register.
Keep monitoring TF1 with the “JNB TF1, here” instruction until TF1 is set.
5. Stop the Timer 1 (Set TR1=0)
6. Clear TF1 flag for the next round.
7. Go back to Step 2 to load TH1 and TL1 again.

5.5.2: TIMER IN MODE 2:

The following are the characteristics and operations of mode 2:
1. It is an 8-bit timer; therefore, it allows only values of 00 to FFH to be loaded into the timer’s
register TH.
2. After TH is loaded with the 8-bit value, the 8051 gives a copy of it to TL Then the timer must be
started. This is done by the instruction SETB TR0 for timer 0 and SETB TR1 for timer 1.
3. After the timer is started, it starts to count up by incrementing the TL register.
 It counts up until it reaches its limit of FF H.
 When it rolls over from FF H to 00, it sets high the TF (timer flag).
4. When the TL register rolls from FF H to 0 and TF is set to 1, TL is reloaded automatically with
the original value kept by the TH register.
 To repeat the process, we must simply clear TF and let it go without any need by the
programmer to reload the original value.
 This makes mode 2 an auto-reload, in contrast with mode 1 in which the programmer has
to reload TH and TL.

TIMER 0 IN MODE 2:

Fig. 5.9: Block diagram of Timer 0 in Mode 2

̅ =0, TMOD=02H & TCON=10H

Note: C/𝐓

Steps to program Timer 0 in Mode 2

1. Load the TMOD register with 02H to operate in Timer 0 in Mode 2.
2. Load initial values into TH0 register (8-bit value i.e. 00H to FFH). The TH0 content is
automatically copied into TL0 register.
3. Start the Timer 0 by setting TR0 in TCON register (SETB TR0)
4. Timer 0 started and it counts until it reaches its maximum value i.e. FFH and it rolls over
to 00H. Now, it will set the TF0 bit in TCON register and the TL0 is reloaded automatically
with the initial value (i.e. TH0 value).
Keep monitoring TF0 with the “JNB TF0, here” instruction until TF0 is set.
5. Clear TF0 flag for the next round.
6. Go back to Step 4, since mode 2 is auto-reload.

TIMER 1 IN MODE 2:

Fig.5.10: Block diagram of Timer 1 in Mode 2

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
̅ =0, TMOD=20H & TCON=40H
Note: C/𝐓

Steps to program Timer 1 in Mode 2

1. Load the TMOD register with 20 H to operate in Timer 0 in Mode 2.
2. Load initial value into TH1 register (8-bit value i.e. 00H to FF H). The TH1 content is
automatically copied into TL1 register.
3. Start the Timer 1 by setting TR1 in TCON register (SETB TR1)
4. Timer 1 started and it counts until it reaches its maximum value i.e. FF H and it rolls over
to 00H. Now, it will set the TF1 bit in TCON register and the TL1 is reloaded automatically
with the initial value (i.e. TH1 value).
Keep monitoring TF1 with the “JNB TF1, here” instruction until TF1 is set.
5. Clear TF1 flag for the next round.
6. Go back to Step 4, since mode 2 is auto-reload.

5.6: COUNTER MODE:

 In 8051, Timer / counter can be used as an event counter by setting C/𝐓
̅ =1 in TMOD
register.
 In counter mode, the source of clock pulse is from external source.

For Counter 0 clock pulse is fed through T0 (P 3.4) and Counter 1 clock pulse is fed through T1
(P 3.5).

Fig.5.11: Block diagram of Counter

5.6.1: COUNTER 0 IN MODE 1:

Fig. 5.12: Block diagram of Counter 0 in Mode 1

̅ =1, TMOD=05H & TCON=10H

Note: C/𝐓

Steps to program Counter 0 in Mode 1

1. Load the TMOD register with 05 H to operate in Counter 0 in Mode 1.
2. Load registers TL0 and TH0 with initial count value (16-bit value i.e. 0000H to FFFF H)
3. Start the Counter 0 by setting TR0 in TCON register (SETB TR0)
4. Counter 0 started and it counts until it reaches its maximum value i.e. FFFF H and it rolls
over to 0000H. Now it will set the TF0 bit in TCON register.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Keep monitoring TF0 with the “JNB TF0, here” instruction until TF0 is set.
5. Stop the Counter 0 (Set TR0=0)
6. Clear TF0 flag for the next round.
7. Go back to Step 2 to load TH0 and TL0 again.
5.6.2: COUNTER 1 IN MODE 1:

Fig. 5.13: Block diagram of Counter 1 in Mode 1

̅ =1, TMOD=50H & TCON=40H

Note: C/𝐓

Steps to program Counter 1 in Mode 1

1. Load the TMOD register with 50H to operate in Counter 1 in Mode 1.
2. Load registers TL1 and TH1 with initial count value (16-bit value i.e. 0000H to FFFF H)
3. Start the Counter 1 by setting TR1 in TCON register (SETB TR1)
4. Counter 1 started and it counts until it reaches its maximum value i.e. FFFF H and it rolls
over to 0000H. Now it will set the TF1 bit in TCON register.
Keep monitoring TF1 with the “JNB TF1, here” instruction until TF1 is set.
5. Stop the Counter 1 (Set TR1=0)
6. Clear TF1 flag for the next round.
7. Go back to Step 2 to load TH1 and TL1 again.

5.6.3: COUNTER 0 IN MODE 2:

Fig.5.14: Block diagram of Counter 0 in Mode 2

̅ =1, TMOD=06H & TCON=10 H

Note: C/𝐓

Steps to program Counter 0 in Mode 2

1. Load the TMOD register with 06 H to operate in Counter 0 in Mode 2.

2. Load initial value into TH0 register (8-bit value i.e. 00 H to FF H). The TH0 content is
automatically copied into TL0 register.
3. Start the Counter 0 by setting TR0 in TCON register (SETB TR0)
4. Counter 0 started and it counts until it reaches its maximum value i.e. FFH and it rolls over
to 00H. Now, it will set the TF0 bit in TCON register and the TL0 is reloaded automatically
with the initial value (i.e. TH0 value).
Keep monitoring TF0 with the “JNB TF0, here” instruction until TF0 is set.
5. Clear TF0 flag for the next round.
6. Go back to Step 4, since mode 2 is auto-reload.
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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
5.6.4: COUNTER 1 IN MODE 2:

Fig.5.15: Block diagram of Counter 1 in Mode 2

̅ =1, TMOD=60H & TCON=40 H

Note: C/𝐓

Steps to program Counter 1 in Mode 2

1. Load the TMOD register with 60 H to operate in Counter 1 in Mode 2.
2. Load initial value into TH1 register (8-bit value i.e. 00 H to FF H). The TH1 content is
automatically copied into TL1 register.
3. Start the Counter 1 by setting TR1 in TCON register (SETB TR1)
4. Counter 1 started and it counts until it reaches its maximum value i.e. FF H and it rolls
over to 00H. Now, it will set the TF1 bit in TCON register and the TL1 is reloaded
automatically with the initial value (i.e. TH1 value).
Keep monitoring TF1 with the “JNB TF1, here” instruction until TF1 is set.
5. Clear TF1 flag for the next round.
6. Go back to Step 4, since mode 2 is auto-reload.

 Differentiate between timers and counters

Sl.
TIMER COUNTER
No.

1 ̅=𝟎
C/𝐓 ̅ =1
C/𝐓

Counters are used to count the events that

2 Timers are used to generate time delay.
occur outside the 8051.

For timer operation clock pulses are For counter operation externals clock pulses
3
provided by crystal oscillator circuit. are applied to pin P3.4 (T0) and P3.5 (T1).

The register is incremented in response to a

Timer register incremented for every
4 1- to -0 transition at its corresponding to
machine cycle.
external input pin (T0, T1).

A timer accumulates series events of a A counter accumulates an unknown

known interval over an interval that is quantity of external events over a known
being measured. The measurement of interval of time. The measurement of
5 interest is typically the time elapsed interest is typically frequency when the
between two events. events are periodic. If the events are
random, the measurement involves event
density over time.

Maximum count rate is 1/12 of oscillator Maximum count rate is 1/24 of oscillator
6
frequency. frequency.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
5.7: MAXIMUM COUNT VALUE:
The maximum count value of the timers in each mode is given in the table
Table: Maximum count value of the timer in each mode
Maximum count value
Timer Mode Timer size Initial value
Hexadecimal (H) Decimal (d)

Mode0 13-bit 0000H 1FFF H 8191

Mode1 16-bit 0000H FFFF H 65535

Mode2 8-bit 00H FF H 255

Mode3 8-bit 00H FF H 255

FORMULAE
𝟏𝟐
Time delay = [Maximum Count Value −( Initial count +1)] × ( Crystal Frequency )
Crystal Frequency
Initial Count = [Maximum Count Value − ( Time delay × 12
)] + 1
12
Maximum delay =[Maximum Count Value × ( )]
Crystal Frequency

Problem5. 4
Write a 8051 assembly program to generate a delay of 12 𝝁𝐬 using Timer0 in Mode1 with
XTAL frequency of 22 MHz.
Solution:
Crystal Frequency
[Initial value − 1] = Maximum value − Delay ×
12
12 𝜇s × 22 MH𝑧
= FFFF H −
12
= 65535 − 12
= 65513 (in decimals)
Initial value = 65513 + 1 = 65514 = FFEA H

 The initial value (16-bit) should be loaded into the 16 -bit timer register THTL as TH1 =
FF (MSB) and TL1 - EA (LSB).
 For timer 0 in mode 𝟏 TMOD = 𝟎𝟏 𝐇
 The initial value is loaded into Timer0 register i.e. TLO = EA H & THO = FF H.
Assembly Language Program (ALP)
ORG 00H
MOV TMOD, #01 ; Timer 0, Mode 1 (16-bit mode)
HERE: MOV TLO, #OEAH ; TL 0 = 𝐹2H, the low byte
MOV TH0, #0FFH ; TH0=FEH, the high byte
SETB TR0 ; Start timer 0
WAIT: JNB TFO, WAIT ; Wait till TF0=1
CLR TR0 ; Stop timer 0
CLR TF0 ; Clear timer 0 flag
SJMP HERE
END

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Problem 5.5
Write an ALP program to generate 50% duty cycle on P1.1. Use timer 1 in mode 1 to
generate the delay. Use an initial value of FFAA H for the timer and a crystal frequency of
11.0592 MHz. Also calculate the frequency of square wave.
Solution:

Assembly Language Program (ALP)

For timer 1 in mode 1 TMOD=10H
ORG 00H
MOV TMOD, #10 ;Timer 1, Mode 1(16-bit mode)
HERE: MOV TL1, #0AAH ;TL1=AAH, the low byte
MOV TH1, #0FFH ;TH1=FFH, the high byte

CPL P1.1 ;Toggle the PORT 1 pin P1.1

LCALL DELAY ;Call delay
SJMP HERE ;repeat again

DELAY: SETB TR1 ;Start timer T1

WAIT: JNB TF1, WAIT ;wait till TF1=1

CLR TR1 ;stop timer 1

CLR TF1 ;clear timer 1 flag
RET ;return to main program
END

Fig. 5.16: Square wave with 50% duty cycle

In this example, the same delay is used for both ON time and OFF time of the square wave i.e.
T1 = T2
The time period of the square wave is
We know that T1 = T2 T = T1 + T2

T = T1 + T1 = 2T1 OR 2T2
The time delay is given by
𝟏𝟐
Time Delay 𝐓𝟏 = × (Final value − Initial value + 𝟏)
Crystal Frequency
12
= × (FFFF − FFAA + 1) = 1.085 𝜇s × 56 H = 1.085 𝜇s × 86 D
11.0592 MHz
Time Delay 𝐓𝟏 = 𝟗𝟑. 𝟑𝟏𝝁𝐬
1 1
Hence frequency of square wave 'f' = = = 𝟓. 𝟑𝟓𝟖𝟒𝐊𝐇𝐳
2 T1 2 × 93.31𝜇sec

Problem 5.6
Generate a square wave with an ON time of 4 ms and an OFF time of 3 ms on pin P1.1.
Assume crystal frequency of 22 MHz. Use timer 1 in mode 1.

Solution:
In this example, the square wave has different ON time (4ms) and OFF time (3ms), hence the intial
values for ON time & OFF time are different and need to compute separtely.

Note: Timer 1 in mode 1 is an 16-bit mode. Therefore the maximim count value is FFFFH.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

TMOD = 10H for Timer1 in Mode 1

ON-Time Initial Value Computation:

𝐎𝐍 - time required = 𝟒 𝐦𝐬 = 𝟒 × 𝟏𝟎−𝟑 𝐬

Hence
Crystal frequency
(Initial value − 𝟏) = Maximum value of mode 𝟎 − Required delay ×
𝟏𝟐
4 × 10−3 × 22 × 106
= FFFF −
12
3 × 10−3 × 22MHz
= FFFF H −
12
= 65535 − 7333
= 58202 + 1
Initial value = E35BH

Load TL1 = 𝟓𝐁 𝐇 and 𝐓𝐇𝟏 = 𝐄𝟑 𝐇

OFF- Time Initial Value Computation:

OFF - time required = 𝟑 𝐦𝐬 = 𝟑 × 𝟏𝟎−𝟑 𝐬

Hence
Crystal frequency
(Initial value − 𝟏) = Maximum value of mode 𝟎 − Required delay ×
𝟏𝟐
3 × 10−3 × 22 MHz
= FFFF H −
12
= 65535 − 5500
= 60035 + 1
Initial value = EA84 H
Load TL1 = 𝟖𝟒 𝐇 and 𝐓𝐇𝟏 = 𝐄𝐀 𝐇

Assembly Language Program (ALP):

ORG 00H
MOV TMOD,#10H ;Timer 1, Mode 1(16-bit mode)

HERE: MOV TL1,#5BH ;TL1=5BH, the low byte

MOV TH1,#E3H ;TH1=E3H, the high byte
SETB P1.1 ;Make pin P1.1 high
ACALL DELAY ;call delay subroutine

MOV TL1,#84H ;TL1=84H, the low byte

MOV TH1,#EAH ;TH1=EAH, the high byte
CLR P1.1 ; Make pin P1.1 low
ACALL DELAY ;call delay subroutine

SJMP HERE

DELAY: SETB TR1 ;delay subroutine. Start Timer 1

WAIT: JNB TF1, WAIT ;wait till TF1=1
CLR TR1 ;stop timer 1
CLR TF1 ;clear timer 1 flag
RET ;return to main program
END
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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Problem: 5.7
Write an ALP to generate a square wave of 20 KHz on pin P2.5. Use timer 0 in mode 2 with
crytal frequency of 22 MHz.
Solution:
In mode 2, the timer is 8-bit with a maximum count value of FFH.
TMOD = 020H for Timer0 in Mode 2

The total time of a square wave 20 KHz

𝟏 𝟏
𝐓= = = 𝟓𝟎 × 𝟏𝟎−𝟔 𝐬
𝐟 𝟐𝟎𝐊𝐇𝐳

𝐓 = 𝐓𝟏 + 𝐓𝟐 = 𝟓𝟎 × 𝟏𝟎−𝟔 𝐬

𝐓𝟏 = 𝟐𝟓 × 𝟏𝟎−𝟔 𝐬 and 𝐓𝟐 = 𝟐𝟓 × 𝟏𝟎−𝟔 𝐬

Crystal frequency
(Initial value − 𝟏) = ( Maximum value of mode 𝟐) − Required delay × 𝟏𝟐
22×106
= (FF) − 25 × 10−6 s × 12
= 255 − 45.88 = 209 + 1 = D2 H
Initial value = 𝐃𝟐 𝐇

Assembly Language Program (ALP):

ORG 00H
MOV TMOD, #02H ; Timer0 in Mode 2
MOV TH0, #D2H ; Initial value loaded in TH0 register
SETB TR0 ; Start Timer 0
WAIT: JNB TF0, WAIT ; wait till TF0=1
CPL P2.5 ; Toggle the PORT 1 Pin P2.5
CLR TF0 ; clear timer 0 flag
SJMP WAIT
END
5.8: SERIAL COMMUNICATION
Introduction
Computers transfer data in two ways: Serial communication and Parallel communication.

5.8.1: Serial communication

Fig. 5.17: Serial Communication

 Serial Communication use single data line to transfer data one bit at a time.
 It is used for long distance communication.
 Serial communication is slower than parallel communication.
Example: IBM keyboards transfer data to the motherboard.

5.8.2: Parallel communication:

Fig.5.18: Parallel Communication

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

 In parallel communication, number of lines required to transfer data depends on the

number of bits to be transferred simultaneously.
 Parallel communication works only for shorter distance.
 Parallel communication is faster than serial communication.
Example: Data communication from computer to printer.

5.8.3: DATA TRANSFER RATES:

 The rate of data transfer in serial communication is stated in bps (bits per second).
Another widely used terminology for bps is Baud rate.
 The baud rate & bps are not same. The baud rate is the MODEM terminology & is
defined as the number of signal changes per second.
 In modem a single change of signal sometimes transfers several bits of data.
 For conductor wire, the baud rate & bps are the same. So, for this reason we use the term
bps & baud interchangeably.

5.8.4: BAUD RATE IN THE 8051:

 The 8051 transfers & receives data serially at many different baud rates. The baud rate in
the 8051 is programmable.
 A standard crystal frequency, XTAL=11.0592 MHz is used to generate the baud rate.
 The 8051 divides the crystal frequency by 12 to get the machine cycle frequency, i.e.
XTAL/12 = 11.0592MHz/12 = 𝟗𝟐𝟏. 𝟔𝐊𝐇𝐳.
 The 8051's serial communication UART circuitry divides the machine cycle frequency of
921.6KHz by 32 i.e. 921.6KHz/32 = 𝟐𝟖, 𝟖𝟎𝟎 𝐇𝐳, then fed the Timerl to set the baud rate
as shown in below figure.

Fig.5.18: UART Circuitry

 The 8051 baud rate is set by Timer 1 using Mode 2 (8-bit auto reload).
 To get the baud rates compatible with the PC, we must load TH1 with the values shown in
below table.
Table: Timer 1 TH1 register values for various Baud Rates
TH1 Baud Rate
DECIMAL HEX SMOD = 0 SMOD = 1
-3 FD 9,600 19,200
-6 FA 4,800 9,600
-12 F4 2,400 4,800
-24 E8 1,200 2,400
Note: XTAL 𝟏𝟏. 𝟎𝟓𝟗𝟐 𝐌𝐇𝐳

Note:
1. To use a higher crystal frequency.
2. To change a SMOD bit in the PCON register i.e. SMOD=1 will double the baud rate
as shown in above table.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Fig.5.19: Frequency Devision

5.8.5: SCON (serial control) register

Fig. 5.20: SCON Serial Port Control Register (Bit addressable)

SCON is an 8-bit register used to program the start bit, stop bit, and data bits of data framing,
among other things.

Bit BIT FUNCTION

Bit
Name
Serial Port Mode specifier
SM0 SM1 OPERATION

0 0 Serial Mode 0
7 & SM0 &
6 SM1 0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start bit

1 0 Serial Mode 2

1 1 Serial Mode 3

5 SM2 This enables the multiprocessing capability of the 8051.

Receive Enable

It is a bit-addressable register
4 REN
When REN=1, it allows 8051 to receive data on RxD pin.

If REN=0, the receiver is disable.

Transfer bit 8

3 TB8 Set/Cleared by hardware to determine state of the 9th bit data transmitted in 9-
bit UART (In mode 2 & 3). We make TB8=0 since it is not used in our application.

Receive bit 8

2 RB8 Set/Cleared by hardware to indicate state of the 9th bit data received -bit UART
(In mode 2 & 3). We make RB8=0 since it is not used in our application.

1 TI Transmit Interrupt

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
When 8051 finishes the transfer of 8-bit character

 It raises TI flag to indicate that it is ready to transfer another byte.

 TI bit is raised at the beginning of the stop bit.
Receive Interrupt

When 8051 receives data serially via RxD, it gets rid of the start and stop bits and
0 RI places the byte in SBUF register

 It raises the RI flag bit to indicate that a byte has been received and should be
picked up before it is lost.
 RI is raised halfway through the stop bit.

5.8.6: SBUF register

 SBUF is an 8-bit register used solely for serial communication.
 The byte data to be transmitted on the serial port (TxD line) is written into SBUF register.
 Data is framed with the start and stop bits and transferred serially via the TxD line.

Fig.5.21: SBUF register

 The SBUF can be accessed like any other register in the 8051. as
MOV SBUF, #’E’ ; load SBUF=45h, ASCII for ‘E’
MOV SBUF, A ; copy accumulator into SBUF
MOV A, SBUF ; copy SBUF into accumulator
 SBUF holds the byte of data when it is received by 8051 RxD line.
 When the bits are received serially via RxD, the 8051 deframes it by eliminating the stop
and start bits, making a byte out of the data received, and then placing it in SBUF.
 The previous data must be read before the new byte completes. Otherwise, the old data
will be lost.

5.8.7 PCON Register:

 PCON register is an 8-bit Special Function Register.

 PCON is not bit addressable register.
 The internal address of PCON register is 87H

Bit BIT FUNCTION

Bit
Name
Serial mode bit (SMOD) used to determine the baud rate with Timer 1. When
7 SMOD 8051 is powered up, SMOD is zero. We can set it to high by software and
thereby double the baud rate.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Baud Rate
SMOD = 0 SMOD = 1
Baud Rates Baud Rates
9,600 19,200
4,800 9,600
2,400 4,800
1,200 2,400
4,5 - Not used by 8051 microcontroller.
&6
GF1 & General purpose flags not implemented
2&3
GF0
PD IDL Status

0 0 Normal Power mode

PD & Idle mode

0&1 0 1
IDL
1 0 Power down mode

1 1 Power down mode

5.9: Programming the 8051 to transfer data serially

Steps used to program 8051 to transfer data serially
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in mode 2 (8-bit
auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8-bit
data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1.
5. TI is cleared by CLR TI instruction.
6. The character byte to be transferred serially is written into SBUF register.
7. The TI flag bit is monitored with the use of instruction “JNB TI, xx” to see if the character
has been transferred completely.
8. To transfer the next byte, go to step 5.

IMPORTANCE OF THE TI FLAG:

To understand the importance of the role of TI, look at the following sequence of steps that the
8051 goes through in transmitting a character via 𝐓𝐱𝐃
1 The byte character to be transmitted is written into SBUF register.
2 The start bit is transferred.
3 The 8-bit character is transferred one bit at a time.
4 The stop bit is transferred. It is during the transfer of the stop bit that the 8051 raises the
𝐓𝐈 flag (TI=1), indicating that the last character was transmitted and it is ready to transfer
the next character.
5 By monitoring the TI flag, make sure that we are not overloading the SBUF register. If we
write another byte into SBUF register before TI is raised, the untransmittcd portion of the
previous byte will be lost. In other words, when the 8051 finishes transferring a byte, it
raises the TI flag to indicate it is ready for the next character.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
6 After SBUF is loaded with a new byte, the TI flag bit must be forced to 0 by the "CLR TI"
instruction in order for this new byte to be transferred.

5.10: PROGRAMMING THE 8051 TO RECEIVE DATA SERIALLY:

In programming the 8051 to receive character bytes serially, the following steps must be taken:
1 The TMOD register is loaded with the value 𝟐𝟎𝐇,. indicating the use of TIMER1 in mode 2
(8-bit auto-reload) to set the baud rate.
2 The TH1 is loaded with one of the four values to set the baud rate for serial data transfer
(Assuming 𝐗𝐓𝐀𝐋 = 𝟏𝟏. 𝟎𝟓𝟗𝟐𝐌𝐇𝐳 ).
3 The SCON register is loaded with the value 𝟓𝟎𝐇, indicating serial mode 1, where an 8-bit
data is framed with start and stop bits.
4 TR1 is set to 𝟏 to start Timer 1.
5 RI is cleared by the "CLR RI" instruction.
6 The RI flag bit is monitored with the use of the transmission "JNB RI, label" to see if an
entire character has been received yet.
7 When RI is raised, SBUF has the byte. Its contents are moved into a safe place.
8 To receive the next character, go to step 5.

IMPORTANCE OF THE RI FLAG:

In receiving bits via its RxD pin, the 8051 goes through the following steps:
1 It receives the start bit indicating that the next bit is first bit of the character byte it is
about to receive.
2 The 8-bit character is received one bit at a time. When the last bit is received, a byte it is
about to receive.
3 The stop bit is received. When receiving the stop bit the 8051 makes 𝐑𝐈 = 𝟏, indicating
that an entire character byte has been received and must be placed up before it gets
overwritten by an incoming character.
4 By checking the RI flag bit when it is raised, we know that a character has been received
and is sitting in the SBUF register. We copy the SBUF contents to a safe place in some other
register or memory before it is lost.
5 After the SBUF contents are copied into a safe place, the RI flag bit must be forced to 0 by
the "CLR RI" instruction in order to allow the next received character byte to be placed in
SBUF. Failure to do this causes loss of the received character.

FORMULAE
Crystal frequency 𝟏
Baud rate = ×
𝟏𝟐 × 𝟑𝟐 (𝟐𝟓𝟔 − 𝐓𝐇𝟏)

Crystal frequency
TH1 = 𝟐𝟓𝟔 −
𝟏𝟐 × 𝟑𝟐 × Baud rate
Problem:5.8
With XTAL = 11.0592 MHz, find the TH1 value needed to have the following baud rates.
(i) 9600 (ii) 4800 (iii) 2400 (iv) 1200
Solution:
i) 9600 Baud Rate
Crystal frequency
𝐓𝐇𝟏 = 𝟐𝟓𝟔 −
𝟏𝟐 × 𝟑𝟐 × Baud rate
11.0592 × 106
TH1 = 256 − = 256 − 3 = 253
12 × 32 × 9600
𝐓𝐇𝟏 = 𝐅𝐃 𝐇

ii) 4800 Baud Rate

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Crystal frequency
TH1 = 256 −
12 × 32 × Baud rate
11.0592 × 106
TH1 = 256 − = 256 − 24 = 232
12 × 32 × 4800
𝐓𝐇𝟏 = 𝐅𝐀 𝐇

iii) 2400 Baud Rate

Crystal frequency
TH1 = 256 −
12 × 32 × Baud rate
11.0592 × 106
TH1 = 256 − = 256 − 12 = 244
12 × 32 × 2400
𝐓𝐇𝟏 = 𝐅𝟒 𝐇
iv) 1200 Baud Rate
Crystal frequency
TH1 = 256 −
12 × 32 × Baud rate
11.0592 × 106
TH1 = 256 − = 256 − 24 = 232
12 × 32 × 1400
𝐓𝐇𝟏 = 𝐄𝟖 𝐇

TH1 register values to obtain different Baud rates

Initial Value
Baud Rate
TH1 in Hexadecimal TH1 in decimal

FD -3 9600

FA -6 4800

F4 -12 2400

E8 -24 1200

Note: In 8051, serial communication uses a standard crystal frequency i.e. 11.0592MHz.

5.10.1: SCON register configuration:

For serial port communication SCON is loaded with 50H as shown in figure.

Fig.5.22: SCON register configuration

5.10.2: TMOD REGISTER CONFIGURATION:

For serial port communication TMOD register is loaded with 20H i.e. Timer1, Mode2.

Problem.5.8:
Write a program for the 8051 to transfer letter “A” serially at 9600 baud, continuously.
Solution:

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
ORH 00H
MOV TMOD,#20H ;timer 1,mode 2(auto reload)
MOV TH1,#-3 ;9600 baud rate
MOV SCON,#50H ;8-bit, 1 stop, REN enabled
SETB TR1 ;start timer 1
AGAIN: MOV SBUF,#”A” ;letter “A” to transfer
HERE: JNB TI, HERE ;wait for the last bit
CLR TI ;clear TI for next char
SJMP AGAIN ;keep sending A
END
Problem.5.9:
Write an ALP and C program to serially transmit the message “ECE” continuously at a baud
rate of 9600, 8-bit data and 1 stop bit.

Solution:
I METHOD II METHOD

ORG 00H ORG 00H

MOV TMOD, #20H MOV TMOD, #20H

MOV TH1, #-3 MOV TH1, #-3

MOV SCON, #50H MOV SCON, #50H

SETB TR1 SETB TR1

MOV A, # “E” MOV DPTR, #MESSAGE

ACALL SEND AGAIN: CLR A

MOV A, # “C” MOVC A, @A+DPTR

ACALL SEND JZ GO

MOV A, # “E” MOV SBUF, A

ACALL SEND WAIT: JNB TI, WAIT

SJMP AGAIN CLR TI

SEND: MOV SBUF, A INC DPTR

WAIT: JNB TI, WAIT GO SJMP GO

CLR TI MESSAGE: DB “ECE”,0

RET END

END

Problem.5.10:
Write an ALP and C program to serially transmit the message “HELLO” continuously at a
baud rate of 9600, 8-bit data and 1 stop bit.

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Solution:
ORG 00H
MOV TMOD, #20H
MOV TH1, #-3
MOV SCON, #50H
SETB TR1
MOV A, # “H”
ACALL SEND
MOV A, # “E”
ACALL SEND
MOV A, # “L”
ACALL SEND
MOV A, # “L”
ACALL SEND
MOV A, # “0”
ACALL SEND
SJMP AGAIN
SEND: MOV SBUF, A
WAIT: JNB TI, WAIT
CLR TI
RET
END

Problem.5.11:
Write an ALP and C program to serially transmit the message “JSSATE NOIDA” continuously
at a baud rate of 9600, 8-bit data and 1 stop bit.

Solution:
ORG 00H
MOV TMOD, #20H
MOV TH1,#-3
MOV SCON,#50H
SETB TR1
repeat: MOV DPTR,#msg
up: CLR A
MOVC A,@A+DPTR
JZ repeat
ACALL send
INC DPTR
SJMP up
send: MOV SBUF,A

here: JNB TI, here

CLR TI
RET

msg: db “JSSATE NOIDA”,0

END

5.11: INTERRUPTS
An interrupt is the occurrence of a condition (an event) that causes a temporary suspension of a
program while the event is serviced by another program (Interrupt Service Routine ‘ISR’.
OR
An interrupt is an external or internal event that interrupts the microcontroller to inform it that
a device needs its service.

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5.11.1: INTERRUPT & POLLING METHODS:

A single microcontroller can serve several devices. There are two ways to do that
1. Interrupts
2. Polling.

INTERRUPTS:
Whenever any device needs its service, the device notifies the microcontroller by sending it an
interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is
doing and serves the device. The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.

POLLING:
Microcontroller continuously monitors the status of a given device. When the conditions met, it
performs the service. After that, it moves on to monitor the next device until each one is serviced.

Comparison between interrupt and polling method

 Compare the interrupt method and polling method of servicing devices

Sl.
INTERRUPTS POLLING
No.

1 Whenever any device needs its service, Microcontroller can monitor the status of
the device notifies the microcontroller several devices and serve each of them as
by sending it an interrupt signal. Upon certain conditions are met. After that, it
receiving an interrupt signal, the moves on to monitor the next device until
microcontroller interrupts whatever it each one is serviced.
is doing and serves the device.

2 Each device can get the attention of the The polling method cannot assign priority
microcontroller based on the priority since it checks all devices in a round-robin
assigned to it. fashion.

3 Microcontroller can also ignore (MASK) Microcontroller cannot ignore (MASK) a

a device request for service. device request for service.

4 Microcontroller time is used efficiently. Microcontroller time is not efficiently used.

5.11.2: STEPS IN EXECUTING AN INTERRUPT:

Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next instruction (PC)
on the stack.
2. It also saves the current status of all the interrupts internally (i.e: not on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector table that holds the
address of the ISR.
4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps
to it. It starts to execute the interrupt service subroutine until it reaches the last
instruction of the subroutine which is RETI (return from interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place where it
was interrupted. First, it gets the program counter (PC) address from the stack by popping
the top two bytes of the stack into the PC. Then it starts to execute from that address.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
5.11.3: DIFFERENT TYPES OF INTERRUPT:
The 8051 has six sources of interrupts and only five interrupts are available to the user. The
RESET interrupt is not available to the user.

RESET: When the RESET pin is activated, the 8051 jumps to address location 0000H.

Timer Interrupts: There are two timer interrupts

1. TF0 for Timer 0 and its interrupt vector address is 000BH.
2. TF1 for Timer 1 and its interrupt vector address is 001BH

External:

Hardware Interrupts
There are two external hardware interrupts and also referred to as EX1 and EX2.
1. ̅̅̅̅̅̅̅
INT0 (P3.2) and its interrupt vector address is 0003H.
2. ̅̅̅̅̅̅̅
INT1 (P3.3) and its interrupt vector address is 0013H

Serial communication interrupt

It has a single interrupt that belongs to both receive and transmit and its interrupt vector address
is 0023H.

Table:5.2: Interrupt Vector Table

INTERRUPT ROM Location (Hex) PIN

Reset 0000 9
External hardware interrupt 0 (INT0) 0003 P3.2 (12)
Timer 0 interrupt (TFO) 000B
External hardware interrupt 1 (INT 1) 0013 P3.3 (13)
Timer 1 interrupt (TF1) 001B
Serial COM interrupt (RI and TI) 0023

5.11.4: IE AND IP REGISTERS:

INTERRUPT ENABLING DISABLING AND PRIORITY SETTING:

 Upon reset, all interrupts are disabled (masked), meaning that none will be responded to
by the microcontroller if they are activated. The interrupts must be enabled by software
in order for the microcontroller to respond to them.
 There is a register called IE (interrupt enable) that is responsible for enabling
(unmasking) and disabling (masking) the interrupts.
INTERRUPT ENABLE (IE) REGISTERS:

Fig.5.23: Interrupt Enable Register

Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each

EA IE.7 interrupt source is individually enabled or disabled by setting or clearing its
enable bit.
- IE.6 Not implemented, reserved for future use.*

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

ET2 IE.5 Enables or disables Timer 2 overflow or capture interrupt (8052 only).
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables Timer 1 overflow interrupt.
ET1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables Timer 0 overflow interrupt.
EX0 IE.0 Enables or disables external interrupt 0.

To enable an interrupt, we take the following steps:

1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect
2. The value of EA
 If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in
IE are high.
 If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register
is high.

5.11.5: Interrupt Priority

When the 8051 is powered up, the priorities are assigned according to Table. In reality, the
priority scheme is nothing but an internal polling sequence in which the 8051 polls the interrupts
in the sequence listed and responds accordingly

Table 5.3: 8051 Interrupt Priority upon Reset

Highest to Lowest Priority

External Interrupt 0 ̅̅̅̅̅̅̅)

(INT0
Timer Interrupt 0 (TF0)
External Interrupt 1 ̅̅̅̅̅̅̅)
(INT1
Timer Interrupt 1 (TF1)
Serial Communication (RI + TI)

For example, that if external hardware interrupts 0 and 1 are activated at the same time, external
interrupt 0 is responded to first. Only after ̅̅̅̅̅̅̅
INT0 has been serviced, ̅̅̅̅̅̅̅
INT1 serviced, since has the
lowest priority.

PRIORITY SETTING
Interrupt priority is done by programming a register called Interrupt Priority (IP) Register. Upon
power-up reset, the IP register contains all 0s, making the priority sequence based. To give a
higher priority to any of the interrupts, we make the corresponding bit in the IP register high.

Interrupt Priority (IP) Register:

Fig.5.24: Interrupt Priority Register

Priority bit = 1 assigns high priority. Priority bit = 0 assigns low priority.
- IP.7 Reserved
- IP.6 Reserved

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

PT2 IP.5 Timer 2 interrupt priority bit (8052 only)

PS IP.4 Serial port interrupt priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT0 IP.1 Timer 0 interrupt priority bit
PX0 IP.0 External interrupt 0 priority bit

Each interrupt source can be programmed to have one of the two priority levels by setting (high
priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register. A low priority
interrupt can itself be interrupted by a high priority interrupt, but not by another low priority
interrupt. If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served. If the requests of the same priority level are received
simultaneously, an internal polling sequence determines which request is to be serviced.

Problem:5.12
Discuss what happens if interrupts INT0, TF0, and INT1 are activated at the same time.
Assume priority levels were set by the power-up reset and the external hardware
interrupts are edge-triggered.

Solution:
If these three interrupts are activated at the same time, they are latched and kept internally. Then
the 8051 checks all five interrupts according to the sequence listed in Table. If any is activated, it
services it in sequence. Therefore, when the above three interrupts are activated, IE0 (external
interrupt 0) is serviced first, then timer 0 (TF0), and finally IE1 (external interrupt 1).

Problem:5.13
(a) Program the IP register to assign the highest priority to INT1 (external interrupt 1),
(b) Discuss what happens if INT0, INT1, and TF0 are activated at the same time. Assume the
interrupts are both edge-triggered.

Solution:
(a) MOV IP, #00000100B ; IP.2=1 assign INT1 higher priority. The instruction SETB IP.2 also will
do the same thing as the above line since IP is bit-addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than the others; therefore, when
INT0, INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1 first, then
it services INT0, then TF0. This is due to the fact that INT1 has a higher priority than the other
two because of the instruction in Step (a). The instruction in Step (a) makes both the INT0 and
TF0 bits in the IP register 0. As a result, the sequence in Table a gives a higher priority to INT0
over TF0

Problem:5.14
Assume that after reset, the interrupt priority is set the instruction MOV IP,#00001100B.
Discuss the sequence in which the interrupts are serviced.

Solution:
The instruction “MOV IP #00001100B” (B is for binary) and timer 1 (TF1) to a higher priority
level compared with the reset of the interrupts. However, since they are polled according to Table
a, they will have the following priority.

Highest Priority External Interrupt 1 (INT1)

Timer Interrupt 1 (TF1)
External Interrupt 0 (INT0)

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Timer Interrupt 0 (TF0)
Lowest Priority Serial Communication (RI+TI)

Problem:5.15
Show the instructions to
(a) Enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 (EX1),
and
(b) Disable (mask) the timer 0 interrupt, then
(c) Show how to disable all the interrupts with a single instruction.

Solution:
(a)
MOV IE, #10010110B ; enable serial, timer 0, EX1
Another way to perform the same manipulation is
SETB IE.7 ; EA=1, global enable
SETB IE.4 ; enable serial interrupt
SETB IE.1 ; enable Timer 0 interrupt
SETB IE.2 ; enable EX1

(b)
CLR IE.1 ; mask (disable) timer 0 interrupt only

(c)
CLR IE.7 ; disable all interrupts

Problem:5.16
Discuss the interrupt priority order achieved by the execution of MOV IP,#11H instruction

Ans. IP = 0 0 0 1 0 0 0 1 i.e. PS=1 & PX0=1

 After executing MOV IP,#11H instruction, two interrupts i.e. Serial port interrupt and
External interrupt 0 are assigned with priority levels
 The external interrupt 0 has highest priority. So it will be served first.
 The serial port interrupt has lowest priority and hence served after external interrupt 0.

8051 Interrupt Numbers

8051 compiler have extensive support for the interrupts.

 They assign a unique number to each of the 8051 interrupts.
 It can also assign a register bank to an ISR. This avoids code overhead due to the
pushes and pops of the R0-R7 registers.

Table5.4: 8051 Interrupt Numbers

Interrupt Name

External Interrupt 0 ̅̅̅̅̅̅̅)

(INT0
Timer Interrupt 0 (TF0)

External Interrupt 1 ̅̅̅̅̅̅̅)

(INT1
Timer Interrupt 1 (TF1)
Serial Communication (RI + TI)

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Differentiate between RET and RETI
RET
 The RET instruction returns the program from a subroutine.
 RET pops the return address from the stack and continue execution there and making the
8051 return to where it left. The high byte and low byte address of PC from the stack and
decrements the SP by 2.
 The execution of the instruction will result in the program to resume from the location
just after the CALL instruction.
 No flags are affected.
Example:
 Suppose SP=0BH originally and an interrupt is detected during the instruction ending at
location 0213H
 RAM Internal locations 0AH and 0BH contain the values 14H and 02H respectively.
 The RETI instruction leaves SP=09H and returns program execution to location 0214H.
RETI
 The RETI instruction returns the program from an interrupt subroutine.
 RETI pops the high byte and low byte address of a PC from the stack and restores the
interrupt logic to accept additional interrupts.
 SP decrements by 2 and no other registers are affected. However, the PSW is not
automatically restored to its pre-interrupt status.
 After the RETI, program execution will resume immediately after the point at which the
interrupt is detected.
 No flags are affected.
Example:
 Suppose SP=0BH originally and an interrupt is detected during the instruction ending at
location 0213H
 RAM Internal locations 0AH and 0BH contain the values 14H and 02H respectively.
 The RETI instruction leaves SP=09H and returns program execution to location 0214H.

 Explain why we cannot use RET instead of RETI as the last instruction of an ISR.
Solution:
 RET and RETI perform the same actions of popping off the top two bytes of the stack into
the program counter, and making the 8051 return to where it left.
 However, RETI also performs an additional task of clearing the interrupt-in-service flag,
indicating that the servicing of the interrupt is over and the 8051 now can accept a new
interrupt on that pin.
 If we use RET instead of RETI as the last instruction of the interrupt service routine, then
it will simply block any new interrupt on that pin after the first interrupt, since the pin
status would indicate that the interrupt is still being serviced.
 In the case of TF0, TF1, TCON.1 and TCON.3, they are cleared due to the execution of RETI.

5.11.6: ENABLING OR DISABLING OF INTERRUPTS:

Interrupts enabling or disabling can be done in two ways:
1. Using bit instructions
Method 1 Method 2 Comments
SETB EA SETB IE. 7 ; 𝐸𝐴 = 1 ; enable interrupts
SETB ET0 SETB IE. 1 ; ET0 = 1 ; enable timer 0 interrupt
SETB ET1 SETB IE. 3 ; ETl = 1 ; enable timer 1 interrupt
SETB EXO SETB IE. 0 ; EXO = 1 ; enable external 0 interrupt
CLR ES CLR IE. 4 ; ES = 0 ; disable serial interrupt

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

CLR EX1 CLR IE. 2 ; 𝐸𝑋1 = 0 ; disable external 1 interrupt

2 Using byte instruction

MOV IE, #10001011B 'OR' MOV IE, #8DH

5.12: STACK
 Stack is a section of internal RAM used by the CPU to store information temporarily. This
information could be data or an address.
 The register used to access the stack is called the stack pointer (SP) register.
 The stack pointer is a 8-bit register used by the 8051 to hold an internal RAM address that is
called the top of the stack.
 When data is to be placed on the stack, the SP increments before storing data on the stack i.e.
SP = SP+1, so that the stack grows up as data is stored.
 When 8051 is RESET, the SP is set to 07H

 As the data is retrieved from the stack, the byte is read from stack & then SP decrements i.e.
SP = SP-1 to point to the next available byte of stored data.
 Storing the data onto stack is called a PUSH.
 Retrieving the contents of the stack is called a POP.
 RAM location 08H is the 1st location used by the stack to store the data

Pushing into stack:

Example 1:
MOV R2, #30H
PUSH 2
Assume that initially Bank 0 is selected & SP=07H

SP is 1st incremented by one i.e. SP = SP+1, then the contents of R2 is stored in top of stack i.e. 08H
address.

Example 2:

ORG 00H
MOV R2, #30H
MOV R3, #40H
MOV R4, #41H
PUSH 2
PUSH 3
PUSH 4
END

Assume Bank0 is selected and SP has initially 07H

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Upper limit of stack:

 Locations 08H to 1FH in 8051 RAM can be used for stack because location 20H-2Fh of RAM are
reserved for bit addressable memory and must not be used by stack.
 If in program, we need more than 24 bytes (08H to 1FH = 24 bytes) of stack then we can change
SP to point to RAM location 30H to 7FH. This is done by the instruction ‘MOV SP,#XXH”

Popping from stack:

Example 3

POP 4
POP 3
POP 2

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Jump and Call Instructions:
Jump and call instructions replaces the contents of program counter (PC) with new address and
program execution to start from that new address. The difference of this new address from
address in program where jump or call instruction is called range of jump or call.

(Note: SADD: Short address, LADD: Long address)

Fig. 5.25: Jump instruction ranges

Jump or call instructions may have one of the three ranges:

i) Relative range: +127d to -128d
ii) Absolute range: within a page (2K bytes)
iii) Long range: 0000H to FFFFH

i) Relative range:
 The Jump can be within -128 bytes. (for backward Jump) or +127 bytes (for forward
Jump) of memory relative to the address of current program counter (PC).
 Jump or call instruction with relative range will be of 2-byte instructions. The 1st byte is
opcode and second byte is relative address of target location.
ii) Absolute range:
 In 8051, program memory is divided into logical divisions called pages each of 2k byte.
 Maximum size program memory is 64 K bytes. Size of each page is 2 K bytes. Maximum
𝟔𝟒 𝐊𝐛
number of pages = 𝟐 𝐊𝐛 = 𝟑𝟐 pages

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
 In absolute range, Jump can be within a single page.
 The upper 5-bits of PC holds the page number and lower 11-bits holds the address
within that page.
i.e., 25 → 32 page
211 → 2 Kb range

iii. Long Absolute Range:

 This range allows the Jump to anywhere in the memory location from 0000 h to FFFFh.
 The Jump or call instructions with this range will be of 3-byte instructions in which 1st
byte is opcode and 2nd and 3rd bytes represent the 16-bit address of target location.

Table: 5.5 COMPARE RELATIVE RANGE, ABSOLUTE RANGE AND LONG RANGE:
Type of Jump or
Ranges No. of bytes Example
CALL

JC, JNC, JB, JNB,

Relative range −𝟏𝟐𝟖 𝐝 to +𝟏𝟐𝟕 𝐝 2-byte instructions
JBC, JZ, JNZ,
DJNZ, CJNE
Within a page
Absolute range 2-byte instructions ACALL
(2 Kbyte)

Anywhere within
Long range program 3-byte instructions LCALL
(0000 H to FFFF H)

5.13: SUBROUTINE
A subroutine is a program that may be used many times in the execution of a larger program. The
subroutine could be written into the body of the main program everywhere it is needed, resulting
in the fastest possible code execution
Call and the stack

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
A call instruction causes a jump to the address where the called subroutine is located. At the end
of the subroutine the program resumes operation at the opcode address immediately following
the call.
The stack area of internal RAM is used to automatically store the address, called the return
address, of the instruction found immediately after the call. The stack pointer register holds the
address of the last space used on the stack.

Fig.5.26: Shows the following sequence of events.

Figure shows the following sequence of events.
1 A call opcode occurs in the program software, or an interrupt is generated in the hardware
circuitry.
2 The return address of the next instruction after the call instruction or interrupt is found
in the program counter.
3 The return address bytes arc pushed on the stack, low byte first.
4 The stack pointer is incremented for each push on the stack.
5 The subroutine address is placed in the program counter.
6 The subroutine is executed.
7 A RET (return) opcode is encountered at the end of the subroutine.
8 Two pop operations restore the return address to the PC from the stack area in internal
RAM.
9 The stack pointer is decremented for each address byte pop.

5.14: ADC0804 (ANALOG TO DIGITAL CONVERTER)

Fig. 5.27: Block diagram of ADC

 The ADC consists of an analog input, digital outputs, control lines and power supply as
shown in figure.
 ADC converts an input analog signal to a digital output.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
 ADCs are mainly classified into
i. Serial ADCs and
ii. Parallel ADCs
Pin diagram of ADC0804

Fig.5.28: Pin diagram of ADC0804

Table5.6: Pin details of ADC0804

Pin No. Pin Name Pin Function

̅̅̅
CS
1 Chip select is an active low input used to activate the ADC0804 chip.
Chip Select

It is an input signal and active low. The ADC converts the analog input
to its binary equivalent and holds it in an internal register.
2 ̅̅̅̅
RD
When CS̅̅̅ = 0,, if a high-to-low pulse is applied to the RD
̅̅̅̅ pin, the 8-
bit digital output shows up at the D0-D7.

It is an active low input used to inform the ADC0804 to start the

̅̅̅=0 when WR
conversion process. If CS ̅̅̅̅̅ makes a low to high transition,
3 ̅̅̅̅̅
WR
the ADC0804 starts converting the analog input value of Vin to an 8-
bit digital number.

 CLK IN is an input pin connects to an external source when an

external clock is used for timing. The ADC0804 chip has an
CLK IN internal clock generator.
 The CLK IN & CLK R pins are connected to a resistor and capacitor
4 & 19 &
to use internal clock generator.
CLK R
 The clock frequency is given by
𝟏
𝐟=
𝟏. 𝟏𝐑𝐂

5 ̅̅̅̅̅̅̅
INTR  This is an active low output pin.
 When ̅̅̅̅̅̅̅
INTR = 0, indicate end of conversion (EOC) to 8051.
 VIN(+) pin is connected with analog input to be converted to digital
6&7 VIN(+) & VIN(-)
 VIN(-) pin is connected to ground
 These are the differential analog input given by VIN = VIN(+) - VIN(-)
8 A GND Analog ground for analog signal

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
It is an input voltage used for the reference voltage.
9 Vref/2 If this pin is open, the analog input voltage for ADC is in the range of
0V to 5V.

10 D GND Digital ground

D0-D7 are the 8-bit digital data output pins.

18-11 D0-D7 𝐕in
𝐃out =
Step Size

VCC=5V. It is also used as a reference voltage when Vref /2 input is

20 VCC
open.

Timing diagram for data conversion by ADC0804 chip

Fig.5.28: Read and Write Timing for ADC0804

The following steps must be followed for data conversion by the ADC0804 chip.
1. Make CS=0 and send a low-to-high pulse to pin WR to start the conversion.
2. Keep monitoring the INTR pin. If INTR is low, the conversion is finished and we can go to
the next step. If INTR is high, keep polling until it goes low.
3. After the INTR has become low, we make CS=0 and send a high-to-low pulse to the RD
pin to get the data out of the ADC0804 IC chip. The timing diagram for this process is
shown in figure.
̅̅̅̅ and WR
Note: CS is set to low for both RD ̅̅̅̅̅ pulses

Write the schematic, algorithm and a program to interface a ADC 0804 to 8051

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Fig. 5.29: 8051 connections to ADC0804 with self-clocking
ALGORITHM
1 Set P1 as input port and P2.7 as input pin
̅̅̅̅̅ = low to high signal.
2 Send a start of conversion to ADC. WR
3 Wait for end of conversion by reading in the INTR pin (INTR = EOC = 0 )
4 Enable ̅̅̅̅
RD = 0, so that converted data is put on D0 − D7 lines
5 Read in the digital data on D0 − D7 using P1
6 Call hexadecimal to ASCII conversion.
7 Call data display to display the ASCII values on LCD.
Assembly language interfacing programming
RD BIT P2. 5 ; RD
WR BIT P2. 6∘ ;WR (start conversion)
INTR BIT P2. 7 ;end-of-conversion
MYDATA EQU P1 ; P1.0 − P1.7 = D0 − D7 of the ADC804
MOV P1, #0FFH ; make P1 = input
SETB INTR
BACK: CLR WR ; WR = 0
SETB WR ; WR = 1 L-to-H to start conversion
HERE: JB INTR, HERE ; wait for end of conversion
CLR RD ; conversion finished, enable RD
MOV A, MYDATA ; read the data
ACALL CONVERSION ; hex-to-ASCII conversion
ACALL DATA DISPLAY ;display the data
SETB ; make RD = 1 for next round
SJMP BACK

5.15: LCD INTERFACING

LCD is finding widespread use replacing LEDs
 The declining prices of LCD
 The ability to display numbers, characters, and graphics
 Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task
of refreshing the LCD
 Ease of programming for characters and graphics.
 LCD pins
 The pins of alphanumeric LCD module which help in interfacing with the microcontroller
are given in table 5.3.2.

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Table.5.6: LCD Commands Code

5.15.1: LCD Commands

Table 5.7: LCD Commands Code

Code
Command to LCD Instruction Register
(Hex)
1 Clear display screen
2 Return home
6 Decrement cursor (shift cursor to left)
5 Increment cursor (shift cursor to right)
7 Shift display right
8 Shift display left
A Display off, cursor off
C Display off, cursor on
E Display on, cursor off
F Display on, cursor blinking
10 Display on, cursor blinking
14 Shift cursor position to left
18 Shift cursor position to right
1C Shift the entire display to the left
80 Shift the entire display to the right

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

C0 Force cursor to beginning of 1st line

38 Force cursor to beginning of 2nd line

5.15.2: LCD Timing for READ

Fig.5.30: LCD Timing for READ

Note: Read requires an L to H pulse for the E pin

5.15.3: LCD Timing for WRITE

Fig.5.31: LCD Timing for write

Example:
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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
 Write the schematic, algorithm and a program to interface a alphanumeric LCD to
8051 and to display ‘INDIA’.

Fig. 5.32: LCD Interfacing with 8051

ALGORITHM
1. Initialize the LCD using the lcdcmd subroutine.
2. Send the ASCII value ‘I’, ‘N’, ‘D’, ‘I’, ‘A’ to PORT P1 and call lcddata subroutine with 250 ms
delay.
3. Send the commands 38H, OEH, 01H, 06H and 86H to PORT P1
4. Make RS = 0 & R/W = 0
5. Make enable Pin E=1 for a 1 ms.
6. Make enable Pin E=0
7. Return to calling program
8. Latch ASCII data on PORT P1 into data register to display on LCD
9. Send the commands 38H, OEH, 01H, 06H and 86H to PORT P1
10. Make RS = 1 & R/W = 0
11. Make enable Pin E=1 for a 1 ms.
12. Make enable Pin E=0
13. Return to calling program
14. Call delay subroutine.

Assembly language interfacing programming

To send any of the commands to the LCD, make pin RS=0. For data, make RS=1. Then send a high-
to-low pulse to the E pin to enable the internal latch of the LCD. This is shown in the code below.

;calls a time delay before sending next data/command

;P1.0-P1.7 are connected to LCD data pins D0-D7
;P2.0 is connected to RS pin of LCD
;P2.1 is connected to R/W pin of LCD
;P2.2 is connected to E pin of LCD

ORG 00H
MOV A,#38H ;Initialize LCD 2 LINES, 5X7 MATRIX
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#0EH ;display on, cursor on
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#01 ;clear LCD
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#06H ;shift cursor right
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#84H ;cursor at line 1, pos. 4

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#’I’ ;display letter I
ACALL DATAWRT ;call display subroutine
ACALL DELAY ;give LCD some time
MOV A,#’N’ ;display letter N
ACALL DATAWRT ;call display subroutine
ACALL DELAY ;give LCD some time
MOV A,#’D’ ;display letter D
ACALL DATAWRT ;call display subroutine
ACALL DELAY ;give LCD some time
MOV A,#’I’ ;display letter I
ACALL DATAWRT ;call display subroutine
ACALL DELAY ;give LCD some time
MOV A,#’A’ ;display letter A
ACALL DATAWRT ;call display subroutine

AGAIN: SJMP AGAIN ;stay here

COMNWRT: ;send command to LCD
MOV P1,A ;copy reg A to port 1
CLR P2.0 ;RS=0 for command
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse
ACALL DELAY ;give LCD some time
CLR P2.2 ;E=0 for H-to-L pulse
RET
DATAWRT: ;write data to LCD
MOV P1,A ;copy reg A to port 1
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse
ACALL DELAY ;give LCD some time
CLR P2.2 ;E=0 for H-to-L pulse
RET
DELAY: MOV R3,#50 ;50 or higher for fast CPUs
HERE2: MOV R4,#255 ;R4 = 255
HERE: DJNZ R4,HERE ;stay until R4 becomes 0
DJNZ R3,HERE2
RET
END
Example:
Write the schematic, algorithm and a program to interface a alphanumeric LCD to 8051
and to display ‘HELLO’

Fig. 5.3.4: LCD Interfacing with 8051

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

ALGORITHM
1. Initialize the LCD using the lcdcmd subroutine.
2. Send the ASCII value ‘H’, ‘E’, ‘L’, ‘L’, ‘O’ to PORT P1 and call lcddata subroutine with 250
ms delay.
3. Send the commands 38H, OEH, 01H, 06H and 86H to PORT P1
4. Make RS = 0 & R/W = 0
5. Make enable Pin E=1 for a 1 ms.
6. Make enable Pin E=0
7. Return to calling program
8. Latch ASCII data on PORT P1 into data register to display on LCD
9. Send the commands 38H, OEH, 01H, 06H and 86H to PORT P1
10. Make RS = 1 & R/W = 0
11. Make enable Pin E=1 for a 1 ms.
12. Make enable Pin E=0
13. Return to calling program
14. Call delay subroutine.

Assembly language interfacing programming

;Check busy flag before sending data, command to LCD
;p1=data pin
;P2.0 connected to RS pin
;P2.1 connected to R/W pin
;P2.2 connected to E pin

ORG 00H
MOV A,#38H ;initialize LCD 2 lines ,5x7 matrix
ACALL COMMAND ;issue command
MOV A,#0EH ;LCD on, cursor on
ACALL COMMAND ;issue command
MOV A,#01H ;clear LCD command
ACALL COMMAND ;issue command
MOV A,#06H ;shift cursor right
ACALL COMMAND ;issue command
MOV A,#86H ;cursor: line 1, pos. 6
ACALL COMMAND ;command subroutine

MOV A,#’H’ ;display letter H

ACALL DATA_DISPLAY
MOV A,#’E’ ;display letter E
ACALL DATA_DISPLAY
MOV A,#’L’ ;display letter L
ACALL DATA_DISPLAY
MOV A,#’L’ ;display letter L
ACALL DATA_DISPLAY
MOV A,#’O’ ;display letter O
ACALL DATA_DISPLAY

HERE: SJMP HERE ;STAY HERE

COMMAND:
ACALL READY ;is LCD ready?
MOV P1,A ;issue command code
CLR P2.0 ;RS=0 for command
CLR P2.1 ;R/W=0 to write to LCD
SETB P2.2 ;E=1 for H-to-L pulse

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
CLR P2.2 ;E=0,latch in
RET
DATA_DISPLAY:
ACALL READY ;is LCD ready?
MOV P1,A ;issue data
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W =0 to write to LCD
SETB P2.2 ;E=1 for H-to-L pulse
CLR P2.2 ;E=0,latch in
RET
READY:
SETB P1.7 ;make P1.7 input port
CLR P2.0 ;RS=0 access command reg
SETB P2.1 ;R/W=1 read command reg
;read command reg and check busy flag
BACK:SETB P2.2 ;E=1 for H-to-L pulse
CLR P2.2 ;E=0 H-to-L pulse
JB P1.7,BACK ;stay until busy flag=0
RET
END

5.16: Stepper motor

Introduction
 A stepper motor translates electrical pulses into mechanical movements. Stepper motors
have a permanent magnet rotor called shaft surrounded by a stator.
 A stepper motor or step motor or stepping motor is a brushless DC electric motor that
divides a full rotation into a number of equal steps. The motor’s position can then be
commanded to move and hold at one of these steps.

Fig.5.33: ROTOR Alignment Fig.5.34: Stator Windings

5.16.1: Configuration

The most common stepper motor has four stator windings that are paired with center-tapped
common as shown in figure. This type of stepper motor is commonly referred to as a four-phase
or unipolar stepper motor. The center tap allows a change of current direction in each of two coils
when a winding is grounded, thereby resulting in a polarity change of the stator. Notice that while
a conventional motor shaft runs freely, the stepper motor shaft moves in fixed repeatable
increment, which aloe one to move it to a precise position.
The direction of the rotation is dictated by the stator poles. The stator poles are determined by
the current sent through the wire coils. As the direction of the current is changed, the polarity is
also changed causing the reverse motion of the rotor. The stepper motor hers has a total of 6
leads: 4 leads representing the four-stator winding and 2 common for the center-tapped leads.

The figure explains the stepper motor control system.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Fig. 5.35: Circuit diagram of stepper motor control system

A stepper motor is brushless and synchronous motor which divides the complete rotation into
number of steps. Each stepper motor will have some fixed step angle and motor rotates at this
angle. The main principle of this circuit is to rotate the stepper motor step wise at a particular
step angle. The ULN2003A IC is used to drive stepper motor as the controller cannot provide
current required by the motor.
The circuit mainly consists of:
 8051 microcontrollers
 ULN2003A
 Stepper Motor

The circuit consists of 8051 microcontroller, ULN2003A and Stepper Motor. The Motor is
connected to the Port 2 of the microcontroller through a driver IC. The ULN2003A is a current
driver IC. It is used to drive the current of the stepper motor as it requires more than 60mA
current. It is an array of Darlington pairs. It consists of seven pairs of Darlington arrays with
common emitter. The IC consists of 16 pins in which 7 are input pins, 7 are output pins and
remaining are VCC and Ground. The first four input pins are connected to the microcontroller. In
the same way, four output pins are connected to the stepper motor.

Stepper motor has 6 pins. In these six pins, 2 pins are connected to the supply of 12V and the
remaining are connected to the output of the stepper motor. Stepper motor rotates at a given
step angle. Each step in rotation is a fraction of full cycle.
The stepper motors will have stator and rotor. Rotor has permanent magnet and stator has coil.
The basic stepper motor has 4 coils with 90 degrees rotation step. These four coils are activated
in the cyclic order. The figure shown above gives the direction of rotation of the shaft of the
stepper motor. There are different methods to drive a stepper motor. Some of these are
explained below.
 Full Step Drive (1.80/Step): In this method two coils are energized at a time. Thus, here
two opposite coils are excited at a time.
 Half Step Drive (0.90/Step): in this method coils are energized alternatively. Thus, it
rotates with half step angle. In this method, two coils can be energized at a time or single
coil can be energized. Thus, it increases the number of rotations per cycle.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Table5.8.1: Full-Step: 4-Step Sequence
Winding Winding Winding Winding Counter-
Step Clockwise
Clockwise A B C D
1 1 0 0 1
2 1 1 0 0
3 0 1 1 0
4 0 0 1 1

Table 5.8.2: Half-Step: 8-Step Sequence

Winding Winding Winding Winding Counter-
Clockwise Step Clockwise
A B C D
1 1 0 0 1
2 1 0 0 0
3 1 1 0 0
4 0 1 0 0
5 0 1 1 0
6 0 0 1 0
7 0 0 1 1
8 0 0 0 1

Table 5.8.3: Wave drive 4-Step sequence

5.16.2: Stepper motor controller circuit advantages:

 It consumes less power.
 It requires low operating voltage.

5.16.3: Stepper Motor Applications:

 Robotics
 Dot matrix printers
 Mechatronics
 Disk drives
 Position Control etc.

5.16.4: Stepper motor controller

Fig.5.35: Block diagram of a stepper motor controller system.

A stepper motor controller (SMC) is an interfacing circuit which is used in between the stepper
motor & the load, which is to be controlled. A SMC based 8051 microcontrollers to control the

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
rotation of a DC stepper motor in clockwise and anti-clockwise directions is shown in the figure
below. The controller is simple and easy to construct, and can be used in many applications
including machine control and robotics for controlling the axial rotation.

Example:
 Sketch the schematic for interfacing a stepper motor to 8051
Solution:

Fig.5.36: Circuit diagram of stepper motor control system

Example:
 Write the schematic, algorithm and a program to interface a stepper motor to 8051 and
to rotate the motor in clock wise direction using normal 4 step sequence.
Solution:

Fig. 5.37: Circuit diagram of stepper motor control system

Table.5.9: Full-Step: 4-Step Sequence
Winding Winding Winding Winding Counter-
Clockwise Step Clockwise
A B C D
1 1 0 0 1
2 1 1 0 0
3 0 1 1 0
4 0 0 1 1

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
 To generate the full-step 4-step sequence, the initial values to be used for clockwise are
66H, 33H, 99H and CCH.
 To generate the full-step 4-step sequence, the initial values to be used for counter-
clockwise are CCH, 99H, 33H and 66H.

Algorithm

1.For clockwise direction, load the sequence 66H into P1

2.Call 100 ms delay
3.Load the sequence 33H into P1
4.Call 100 ms delay
5.Load the sequence 99H into P1
6.Call 100 ms delay
7.Load the sequence CCH into P1
8.Call 100 ms delay
9.Repeat from step 1
Assembly language interfacing programming
Method 1 Method 2

ORG 00H ORG 00H

BACK: MOV A,#66H BACK: MOV P1, #66H

MOV P1,A ACALL DELAY

RR A MOV P1, #33H

ACALL DELAY ACALL DELAY

MOV P1, #99H

SJMP BACK ACALL DELAY

MOV P1, #CCH

DELAY: MOV R0,#255 ACALL DELAY

UP1: MOV R1,#255

UP2: DJNZ R1,UP2 SJMP BACK

DJNZ R0,UP1

RET DELAY: MOV R0,#255

END UP1: MOV R1,#255

UP2: DJNZ R1,UP2

DJNZ R0,UP1

RET

END

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Example:
 Write the schematic, algorithm and a program to interface a stepper motor to 8051 and
to rotate the motor in anti-clock wise direction using wave drive sequence

Solution:

Fig.5.38: Circuit diagram of stepper motor control system

Table 5.10: Wave drive 4-Step sequence

 To generate the wave-drive 4-step sequence, the initial values to be used for clockwise
are 8H, 4H, 2H and 1H.
 To generate the wave-drive 4-step sequence, the initial values to be used for counter-
clockwise are 1H, 2H, 4H and 8H.

Algorithm
1. For counter-clockwise direction load the sequence 01H into P1
2. Call 100 ms delay
3. Load the sequence 02H into P1
4. Call 100 ms delay
5. Load the sequence 04H into P1
6. Call 100 ms delay
7. Load the sequence 08H into P1
8. Call 100 ms delay
9. Repeat from step 1

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Method 1 Method 2

ORG 00H ORG 00H

BACK: MOV A,#01H BACK: MOV P1, #01H

MOV P1,A ACALL DELAY

RL A MOV P1, #02H

ACALL DELAY ACALL DELAY

MOV P1, #04H

SJMP BACK ACALL DELAY

MOV P1, #08H

DELAY: MOV R0,#255 ACALL DELAY

UP1: MOV R1,#255

UP2: DJNZ R1,UP2 SJMP BACK

DJNZ R0,UP1

RET DELAY: MOV R0,#255

END UP1: MOV R1,#255

UP2: DJNZ R1,UP2

DJNZ R0,UP1

RET

END

Example:
A switch is connected to pin P2.7. Write a ALP program to monitor the status of SW and
perform the following:
i. If SW = 0, the stepper motor moves clockwise.
ii. If SW = 1, the stepper motor moves counterclockwise.

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

Fig.5.38: Circuit diagram of stepper motor control system

 To generate the full-step 4-step sequence, the initial values to be used for clockwise are
66H, 33H, 99H and CCH.
 To generate the full-step 4-step sequence, the initial values to be used for counter-
clockwise are CCH, 99H, 33H and 66H.

Algorithm
1. If SW = 0, rotate the motor in clockwise direction
2. Load the sequence 66H into P1
3. Call 100 ms delay
4. Load the sequence 33H into P1
5. Call 100 ms delay
6. Load the sequence 99H into P1
7. Call 100 ms delay
8. Load the sequence CCH into P1
9. Call 100 ms delay
10. Else (i.e. if SW =1)
11. Rotate motor in counter clockwise direction i.e. load the sequence CCH into P1
12. Call 100 ms delay
13. Load the sequence 99H into P1
14. Call 100 ms delay
15. Load the sequence 33H into P1
16. Call 100 ms delay
17. Load the sequence 66H into P1
18. Call 100 ms delay
19. Repeat from step 1

Assembly language interfacing programming

Method 1 Method 2

ORG 00H ORG 00H

SETB P2.7 SETB P2.7

MOV A, #66H

BACK: JNB P2.7, CLOCKWISE

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 Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
NEXT: JNB P2.7, CLOCKWISE

RL A MOV P1, #CCH

MOV P1, A ACALL DELAY

ACALL DELAY MOV P1, #99H

SJMP NEXT ACALL DELAY

MOV P1, #33H

CLOCKWISE: RR A ACALL DELAY

MOV P1, A MOV P1, #66H

ACALL DELAY ACALL DELAY

SJMP NEXT

SJMP BACK

DELAY: MOV R0, #255

UP2: MOV R1, #255 CLOCKWISE:

UP1: DJNB R1, UP1 MOV P1, #66H

DJNB R0, UP2 ACALL DELAY

RET MOV P1, #33H

END ACALL DELAY

MOV P1, #99H

ACALL DELAY

MOV P1, #CCH

ACALL DELAY

SJMP BACK

DELAY: MOV R0,#255

UP1: MOV R1,#255

UP2: DJNZ R1,UP2

DJNZ R0,UP1

RET

END

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Example:
Write a program to rotate a motor 800 in the clockwise direction. The motor has a step
angle of 20. Use the 4-step sequence.

Fig.5.38: Circuit diagram of stepper motor control system

Number of steps to rotate the motor for 800 is

Algorithm
1. Initialize a counter with 40 steps
2. Load the sequence 66H into P1
3. Call delay
4. For clockwise direction rotate the phase sequence right
5. Decrement counter (R0) and repeat from step 1 until counter is zero
6. If counter is zero i.e. R0=0, Stop.

Assembly language interfacing programming

ORG 00H
MOV A, #66H
MOV R0, #40
UP: RR A
MOV P1, A
ACALL DELAY
DJNZ R0, UP

DELAY: MOV R2, #255

UP2: MOV R1, #255
UP1: DJNB R1, UP1
DJNB R2, UP2
RET
END

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Example:
Write a program to rotate a motor 800 in the clockwise direction. The motor has a step
angle of 20. Use the 4-step sequence.

Fig.5.39: Circuit diagram of stepper motor control system

Algorithm
1. Initialize a counter with 40 steps
2. Load the sequence 66H into P1
3. Call delay
4. For clockwise direction rotate the phase sequence right
5. Decrement counter (R0) and repeat from step 1 until counter is zero
6. If counter is zero i.e. R0=0, Stop.

Assembly language interfacing programming

ORG 00H
MOV A, #66H
MOV R0, #40
UP: RR A
MOV P1, A
ACALL DELAY
DJNZ R0, UP
SJMP EXIT

DELAY: MOV R2, #255

UP2: MOV R1, #255
UP1: DJNB R1, UP1
DJNB R2, UP2
RET
EXIT:
END

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051
Example:
Write a program to rotate a motor in the clockwise direction.
ORG 000H
START: MOV R0, #04 ; Initialize R0 with 4
RPT: MOV DPTR, #0100H ; Load DPTR with the address 0100H
CLR A ; Clear accumulator A
MOVC A, @A+DPTR ; Move the value from the code memory to A
MOV P1, A ; Output the value to Port 1
ACALL DELAY ; Call the delay subroutine
INC DPTR ; Increment DPTR to point to the next value
DJNZ R0, RPT ; Decrement R0 and jump to RPT if not zero
SJMP START ; Jump back to START
DELAY: ; Delay subroutine
MOV R2, #10 ; Initialize outer loop count for delay
OUTER_LOOP: MOV R3, #50 ; Initialize inner loop count for delay
INNER_LOOP: NOP ; No operation (adjust as needed for timing)
NOP
DJNZ R3, INNER_LOOP ; Decrement R3 and jump if not zero
DJNZ R2, OUTER_LOOP ; Decrement R2 and jump if not zero
RET

ORG 𝟎𝟏𝟎𝟎𝐇 ; Address for data

DB 𝟖, 𝟒, 𝟐, 𝟏 ; Data values
END

Example:
Write a program to rotate a motor in the counter clockwise direction.
ORG 000H
START: MOV R0, #04 ; Initialize R0 with 4
RPT: MOV DPTR, #0100H ; Load DPTR with the address 0100H
CLR A ; Clear accumulator A
MOVC A, @A+DPTR ; Move the value from the code memory to A
MOV P1, A ; Output the value to Port 1
ACALL DELAY ; Call the delay subroutine
INC DPTR ; Increment DPTR to point to the next value
DJNZ R0, RPT ; Decrement R0 and jump to RPT if not zero

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Microprocessor & Microcontroller Unit-5: Assembly Programming & Instruction of 8051

SJMP START ; Jump back to START

DELAY: ; Delay subroutine
MOV R2, #10 ; Initialize outer loop count for delay
OUTER_LOOP: MOV R3, #50 ; Initialize inner loop count for delay
INNER_LOOP: NOP ; No operation (adjust as needed for timing)
NOP
DJNZ R3, INNER_LOOP ; Decrement R3 and jump if not zero
DJNZ R2, OUTER_LOOP ; Decrement R2 and jump if not zero
RET

ORG 𝟎𝟏𝟎𝟎𝐇 ; Address for data

DB 𝟏, 𝟐, 𝟒, 𝟖 ; Data values
END

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Microprocessor & Microcontroller Annexure-1: 8085 Programming

Annexure-1: 8085 Programming

LEVEL-1
1. Addition of Two 8-Bit Numbers

Objective: Add two 8-bit numbers stored in memory.

MVI A, 05H ; Load 5H into Accumulator A

MVI B, 07H ; Load 7H into Register B

ADD B ;A=A+B

STA 4000H ; Store result in memory address 4000H

HLT ; Halt the program

Expected Result: The sum of 5H and 7H is stored in memory location 4000H.

2. Subtraction of Two 8-Bit Numbers

Objective: Subtract an 8-bit number from another.

MVI A, 0AH ; Load 0AH into Accumulator A

MVI B, 05H ; Load 5H into Register B

SUB B ;A=A-B

STA 4001H ; Store result in memory address 4001H

HLT ; Halt the program

Expected Result: The difference of 0AH and 5H is stored in memory location 4001H.

3. Multiplication of Two 8-Bit Numbers (Repeated Addition)

Objective: Multiply two 8-bit numbers using repeated addition.

MVI B, 03H ; Load multiplier (3H) into Register B

MVI C, 04H ; Load multiplicand (4H) into Register C

MVI A, 00H ; Initialize result A to 0

LOOP: ADD C ; A = A + C

DCR B ; Decrement B by 1

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
JNZ LOOP ; If B is not zero, repeat

STA 4002H ; Store result in memory address 4002H

HLT ; Halt the program

Expected Result: The product of 3H and 4H is stored in memory location 4002H.

4. Find the Largest of Two 8-Bit Numbers

Objective: Compare two 8-bit numbers and store the larger number in a specific
memory location.

MVI A, 0AH ; Load first number (0AH) into Accumulator A

MVI B, 07H ; Load second number (07H) into Register B

CMP B ; Compare A with B

JZ EQUAL ; If A = B, jump to EQUAL

JC SMALLER ; If A < B, jump to SMALLER

STA 4003H ; If A > B, store A in memory 4003H

JMP END ; Jump to end

SMALLER: MOV A, B ; Move B into A

STA 4003H ; Store B in memory 4003H

JMP END

EQUAL: STA 4003H ; Store A in memory 4003H (if they are equal)

END: HLT ; Halt the program

Expected Result: The larger of the two numbers (0AH and 07H) is stored in memory
location 4003H.

5. Addition of Two 16-Bit Numbers

Objective: Add two 16-bit numbers stored in memory.

LXI H, 4000H ; Load HL with address 4000H (contains first number)

MOV A, M ; Move low byte of the first number to A

INX H ; Increment HL to point to the high byte

MOV B, M ; Move high byte of the first number to B

LXI H, 4002H ; Load HL with address 4002H (contains second number)

ADD M ; Add low byte of second number to A

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
MOV C, A ; Store result low byte in C

INX H ; Increment HL to high byte

ADC M ; Add high byte of second number and carry to B

MOV D, A ; Store result high byte in D

SHLD 4004H ; Store result in 4004H (D in 4005H and C in 4004H)

HLT ; Halt the program

Expected Result: The sum of the two 16-bit numbers stored in 4000H-4001H and
4002H-4003H is saved in 4004H-4005H.

6. Move a Block of Data

Objective: Copy a block of data from one memory location to another.

LXI H, 4500H ; Load source address 4500H in HL register

LXI D, 4600H ; Load destination address 4600H in DE register

MVI C, 05H ; Number of bytes to move

LOOP: MOV A, M ; Move data from HL to Accumulator

STAX D ; Store data in DE location

INX H ; Increment source pointer

INX D ; Increment destination pointer

DCR C ; Decrement counter

JNZ LOOP ; If counter not zero, repeat

HLT ; Halt the program

Expected Result: A block of 5 bytes starting from 4500H is copied to 4600H.

7. Sum of Array Elements

Objective: Calculate the sum of 5 numbers stored in memory.

LXI H, 4700H ; Load starting address of the array in HL

MVI C, 05H ; Set counter to 5

MVI A, 00H ; Initialize sum to 0

LOOP: ADD M ; Add each element to A

INX H ; Move to the next element

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
DCR C ; Decrement counter

JNZ LOOP ; Repeat if counter is not zero

STA 4800H ; Store sum at memory location 4800H

HLT ; Halt the program

Expected Result: The sum of the five numbers is stored in memory location 4800H.

8. Check if a Number is Even or Odd

Objective: Check if a number is even or odd and store the result.

MVI A, 08H ; Load number (8H) into Accumulator

ANI 01H ; AND with 01H to check the least significant bit

JZ EVEN ; If result is zero, jump to EVEN

MVI A, 01H ; If result is non-zero, load 01H (odd flag) in A

STA 4900H ; Store result in 4900H

JMP END

EVEN: MVI A, 00H ; Load 00H (even flag) in A

STA 4900H ; Store result in 4900H

END: HLT ; Halt the program

Expected Result: 00H is stored at 4900H if the number is even, 01H if it is odd.

LEVEL-2
9. 8085 programs to arrange given numbers in ascending order

HEX
Address Labels Mnemonics Comments
Codes

LXI H,
8000 21, 40, 80 START Pointer to the IN-BUFFER
8040H

The D register is used as a flag

8003 16, 00 MVI D, 00H
register

8005 4E MOV C, M Initialize reg. C with data count

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HEX
Address Labels Mnemonics Comments
Codes

8006 0D DCR C Set Reg. C for comparison count

8007 23 INX H Pointing to the next location

8008 7E CHECK MOV A, M Get the number

8009 23 INX H Go to next location

Compare the contents of the

800A BE CMP M current memory location with
the contents of the accumulator

DA, 14, If (A) < second byte, do not

800B JC NEXTBYT
80 exchange

800E 46 MOV B, M Get second byte for exchange

Store first byte in second

800F 77 MOV M, A
location

8010 2B DCX H Point to first location

Store second byte in first

8011 70 MOV M, B
location

8012 23 INX H Get ready for next comparison

Load 1 in D as a remainder for

8013 16, 01 MVI D, 01H
exchange

8015 0D NEXTBYT DCR C Decrement comparison count

If comparison count not 0, go

8016 C2, 08, 80 JNZ CHECK
back

8019 7A MOV A, D Get flag bit in A

801A 0F RRC Place flag bit D0in carry

DA, 00,
801B JC START If flag is 1, exchange occurred
80

801E 76 HLT Terminate the program

10. Program to divide 2 8-bit numbers.

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ADDRESS MNEMONICS COMMENT

2000 LXI H, 2050

2003 MOV B, M B<-M

2004 MVI C, 00 C<-00H

2006 INX H

2007 MOV A, M A<-M

2008 CMP B

2009 JC 2011 check for carry

200C SUB B A<-A-B

200D INR C C<-C+1

200E JMP 2008

2011 STA 3050 3050<-A

2014 MOV A, C A<-C

2015 STA 3051 3051<-A

2018 HLT terminate the program

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
11. Flashing LED connected to port 1 of the 8051 Microcontroller

Level Mnemonics Comments

LOOP: CLR P1.0 Clear Port P1.0 Bit

ACALL DELAY Call Delay

SETB P1.0 Set Port P1.0 Bit

ACALL DELAY Call Delay

SJMP LOOP Jump back to Loop

DELAY NOP Delay Program

LOOPB: MOV R2, #200

LOOPA: MOV R3, #250

NOP

NOP

DJNZ R3, LOOPA

DJNZ R2, LOOPB

RET

END

12. To generate 10 kHz square wave using 8051.

Program using Timer 0 to create a 1kHz square wave on P1.0

Level Mnemonics Comments

MOV TMOD, #02H 8 bit auto reload mode

MOV TH0, #-50 -50 reload value in TH0

SETB TR0 start timer

LOOP: JNB TF0, LOOP wait for overflow flag

CLR TF0 Clear timer overflow flag

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Microprocessor & Microcontroller Annexure-1: 8085 Programming

CPL P1.0 toggle port bit

SJMP LOOP repeat

END

The program above creates a square wave on P1.0 with a high-time of 50 μs and a low-
time of 50 μs. Since the interval is less than 256 μs, timer mode 2 can be used. An overflow
every 50 μs requires a TH0 reload value of 50 counts less than 00H, or -50. The program
uses a complement bit instruction (CPL) rather than SETB and CLR. Between each
complement operation, a delay of 1/2 the desired period (50 μs) is programmed using
Timer 0 in 8-bit auto-reload mode. The reload value is specified using decimal notation
as - 50, rather than using hexadecimal notation. The assembler performs the necessary
conversion. Note that the timer overflow flag (TF0) is explicitly cleared in software after
each overflow.

13. Write a program to show the use of INT0 and INT1 of 8051.

Level Mnemonics Comments

ORG 0000H

LJMP MAIN Bypass Interrupt Vector table

ISR for hardware Interrupt INT1 to turn on LED

ORG 0013H

SETB P1.3 Turn on LED

MOV R3, #255 Load Counter

BACK: DJNZ R3, BACK Keep LED on for a while

CLR P1.3 Turn off LED

RETI Return form ISR

Main Program for Initialization

ORG 30H

MAIN: MOV IE, Enable External INTI

#10000100B

HERE: SJMP HERE Stay here until Interrupted

END

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Microprocessor & Microcontroller Annexure-1: 8085 Programming

Practice Problems
1. Write a Program to Convert Hexadecimal to ASCII Code and ASCII Code to
Hexadecimal

Hint:

a. Hexadecimal to ASCII code conversion

ALGORITHM:

Step 1. Load the given data in A - register and move to B - register

Step 2. Mask the upper nibble of the Hexadecimal number in A - register

Step 3. Call subroutine to get ASCII of lower nibble

Step 4. Store it in memory

Step 5. Move B - register to A - register and mask the lower nibble

Step 6. Rotate the upper nibble to lower nibble position

Step 7. Call subroutine to get ASCII of upper nibble

Step 8. Store it in memory

Step 9. Terminate the program.

TEST CASE:

Inputs – HEX data - E4H in memory location 5000

Output –

34H in memory location 5001(ASCII Code for 4)

45H in memory location 5002(ASCII Code for E)

b. ASCII to Hexadecimal conversion

ALGORITHM:

Step 1. Input the content of 2050 in accumulator.

Step 2. Subtract 30H from accumulator.

Step 3. Compare the content of accumulator with 0AH.

Step 4. If content of accumulator is less than 0A then goto step 6 else goto step 5.

Step 5. Subtract 07H from accumulator.

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
Step 6. Store content of accumulator to memory location 3050.

Step 7. Terminate the program.

Note: Make the program yourself and check the output.

INTERFACING
1. INTERFACING OF 8085 WITH 8253

The Intel 8253 and 8254 are Programmable Interval Timers designed for
microprocessors to perform timing and counting functions using three 16-bit registers.
Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a
counter, a 16-bit count is loaded in its register. On command, it begins to decrement the
count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.

In this experiment the timer 1 is used in the MODE 3 mode.

Step 1- Connect the card to the kit through 50 pin cable. Ensure that the pin-1 of the card
is connected to the pin-1 of the Kit Bus connector.

Step 2- Connect +5V and GND to the kit through power supply. Switch ON the supply and
press RESET.

Step 3- Enter the program by using EXMEM command

Step 4- Execute the program using <GO> command

Step 5- Observe the results on the oscilloscope.

PROGRAM:

ADDRESS OP CODE LABEL MNEMONICS REMARKS

2000 3E 76 START MVI A,76 Timer 1 is selected in

Mode 3, 16 bit binary
counter

2002 D3 4B OUT 4B

2004 3E 0A MVI A,0A Load 0A as LSB first

2006 D3 49 OUT 49

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Microprocessor & Microcontroller Annexure-1: 8085 Programming

2008 3E 00 MVI A,00 Load 00 as MSB

200A D3 49 OUT 49

2. Interfacing of DAC with 8085

To interface DAC with 8085 to demonstrate the generation of square, saw tooth and
triangular wave.

ALGORITHM:

The D/A converter interface is provided on the kit in mapped mode. The DAC 0800 used
here is an 8-bit DAC and has A0 as the I/O address. The chip provides output of 0 to 8
volts. The DAC output is available at Pin No 2 of 26 pin FRC connector J7.

The staircase, square wave or triangular outputs can be generated using the chip.

Steps for generating Square Wave:

STEP 1- Initialize A=00

STEP 2-Put the contents on output port having address A0 (I/O address on which DAC
is connected)

STEP 3- Put Delay D1

STEP 4- Initialize A=FF

STEP 5-Put the contents on output port having address A0( I/O address on which DAC
is connected)

STEP 6- Put Delay D1

STEP 7- Jump on step 1

In the similar way students can write the programs for SAWTOOTH and TRIANGULAR
waveform simply by initializing the accumulator, adjusting the contents of it and
transferring the contents on port address A0.

Steps for generating Triangular Wave:

STEP 1- Initialize A=00

STEP 2- INR A

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Microprocessor & Microcontroller Annexure-1: 8085 Programming
STEP 3-Put the contents on output port having address A0 (I/O address on which DAC
is connected)

STEP 4- Compare with peak value FF H

STPE 5- If not equal to FF then Jump to step 2

STEP 6- DCR A

STEP 7- Put the contents on output port having address A0 (I/O address on which DAC
is connected)

STEP 8- Compare with 00H.

STEP 9- If not equal to 00 H then Jump to step 6.

STEP 10- Jump STEP-2

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Annexure-2: 8051 Instruction Set

8051 Data Type

 The 8051 microcontrollers have only one data type. It is 8-bits, and the size of each
register is also 8 bits.
 The programmer has to break down data larger than 8 bits (1 Byte) to be processed by
the CPU.
 The data types used by the 8051 can be positive or negative.

Assembler Directives
 The assembler directives are the statements that directs the assembler what to do during
assembling.
 They reserve memory space for data, define constants, and tell assembler where to
assemble program in a memory.
 They are also referred as pseudo instructions statements as they are effective only during
the assembly of the program but they do not generate any machine code.

The 8051 has 4 assembler directives:

1. ORG (origin)
2. DB (Define data)
3. END
4. EQU (Equate)

ORG (origin)
 The ORG directive is used to indicate the beginning of the address.
 The number that comes after ORG can be either in hex or in decimal.
 If the number is not followed by H, it is decimal and the assembler will convert it to
hexadecimal.
 Some assemblers use “. ORG” (dot ORG) instead of “ORG” for the origin directive.
Example: ORG 1000H

DB (Define data)
 It is used to define the 8-bit data and most widely used data directive in the assembler.
 When DB is used to define data, the numbers can be in decimal, binary, hex, or ASCII
formats. For decimal, the “D” after the decimal number is optional, “B” for binary and “H”
for hexadecimal.
 To indicate ASCII, simply place the characters in single quotes or double quotes. The
assembler will assign the ASCII code for the numbers or characters automatically.
 The DB directive is the only directive that can be used to define ASCII strings larger than
two characters; therefore, it should be used for all ASCII data definitions.
Examples:
ORG 1000H
DATA1: DB 40 ; DECIMAL NUMBER
DATA2: DB 00100111B ; BINARY NUMBER
DATA3: DB 1Fh ; HEXADECIMAL NUMBER
DATA4: DB "DIPLOMA" ; ASCII CHARACTER
DATA5: DB "2016" ; ASCII NUMBER
END
EQU
 EQU is used to define a constant without occupying a memory location.
 The EQU directive does not set aside storage for a data item but associates a constant
value with a data label.
 When the label appears in the program, its constant value will be substituted for the label.

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
 Assume that there is a constant used in many different places in the program, and the
programmer wants to change its value throughout. By the use of EQU, one can change it
once and the assembler will change all of its occurrences.
Example:
ORG 1000H
COUNT EQU 40H
MOV A, #COUNT ; COPY 40 INTO A

END
 EQU indicates to the assembler the end of the source (asm) file.
 The END directive is the last line of an 8051 program, meaning that in the source code
anything after the END directive is ignored by the assembler.
 Some assemblers use “. END” (“dot END”) instead of “END”.
Example:
ORG 1000H
COUNT EQU 40H
MOV A, #COUNT ; COPY 40 INTO A
END

Structure of Assembly Language

An assembly language instruction consists of a mnemonic, followed by one or two operands. An
assembly language instruction consists of four fields:
[label:] mnemonic [operands] [;comment]
Example:
Again: MOV A, R0 ; Copy the content of R0 into A register

NOTE:
Brackets indicate that a field is optional, and not all lines have them. Brackets should not be
typed in the instructions.

INSTRUCTION SET
 Based on the operations performed, the instruction set of 8051 are classified as
1. Arithmetic instructions
2. Logical instructions
3. Data transfer instructions
4. Boolean instructions
5. Program branching instructions.

 Each instruction has two parts: operation code and operands. The operands may be one
or more i.e. operation code operand 1, operand 2
Example: MOV A, B
 The following nomenclatures for register, data, address and variables are used while
write instructions.
Table 2.1.1: Nomenclatures for register, data, address and variables are used while write
instructions.
A Accumulator
B "B" register
C Carry bit
Rn Register R0 - R7 of the currently selected register bank
Direct 8-bit internal direct address for data. The data could be in lower 128bytes of
RAM (00 - 7FH) or it could be in the special function register (80 - FFH).
@Ri 8-bit external or internal RAM address available in register R0 or R1. This is
used for indirect addressing mode.
#data8 Immediate 8-bit data available in the instruction.
#data16 Immediate 16-bit data available in the instruction.

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Addr11 11-bit destination address for short absolute jump. Used by instructions AJMP &
ACALL. Jump range is 2 kbyte (one page).
Addr16 16-bit destination address for long call or long jump.
Rel 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all
conditional jumps.
bit Directly addressed bit in internal RAM or SFR

Arithmetic Instructions
Syntax Flags affected Bytes Cycles
ADD A, #data CY, OV & AC 2 1
Operation (A) (A) + 8-bit data
Description Adds the 8-bit immediate data with accumulator contents and result is
stored in accumulator.
Example ADD A, #04H
Before Execution After Execution
A = 05H A = 09H

Syntax Flags affected Bytes Cycles

ADD A, Rn CY, OV & AC 1 1
Operation (A) (A) + (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Adds the contents of register Rn with accumulator contents and result is
stored in accumulator.
Example ADD A, R1
Before Execution After Execution
A = 05H & R1 = 04H A = 09H

Syntax Flags affected Bytes Cycles

ADD A, direct CY, OV & AC 2 1
Operation (A) (A) + (direct address) where direct is the address.
Description Adds the content of direct address with accumulator contents and result is
stored in accumulator.
Example ADD A, 50H
Before Execution After Execution
A = 05H & 50H = 04H A = 09H

Syntax Flags affected Bytes Cycles

ADD A, @Ri CY, OV & AC 1 1
Operation (A) (A) + ((Ri)) where i = 0 & 1 i.e. R0 & R1.
Description Adds the contents of indirect RAM address with accumulator contents and
result is stored in accumulator.
Example ADD A, @R0
Before Execution After Execution
A = 05H, R0 = 50H & 50H = 04H A = 09H i.e. A = (A) + (50H)

Syntax Flags affected Bytes Cycles

ADDC A, #data CY, OV & AC 2 1
Operation (A) (A) + (C) + 8-bit data
Description Adds the 8-bit immediate data, the carry flag and the accumulator contents,
result is stored in accumulator.
Example ADDC A, #04H
Before Execution After Execution
A = 05H, CY=0 A = 09H
A = 05H, CY=1 A = 0AH

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Syntax Flags affected Bytes Cycles
ADDC A, Rn CY, OV & AC 1 1
Operation (A) (A) + (C) + (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Adds the contents of register Rn, the carry flag and the accumulator
contents, result is stored in accumulator.
Example ADDC A, Rn where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Before Execution After Execution
A = 05H, CY=0 & Rn = 04H A = 09H
A = 05H, CY=1 & Rn = 04H A = 0AH

Syntax Flags affected Bytes Cycles

ADDC A, direct CY, OV & AC 2 1
Operation (A) (A) + (C) + (direct address)
Description Adds the contents of direct address, the carry flag and the accumulator
contents, result is stored in accumulator.
Example ADDC A, 50H
Before Execution After Execution
A = 05H, CY=0 & 50H = 04H A = 09H
A = 05H, CY=1 & 50H = 04H A = 0AH

Syntax Flags affected Bytes Cycles

ADDC A, @Ri CY, OV & AC 1 1
Operation (A) (A) + (C) + ((Ri)) where i = 0 & 1 i.e. R0 & R1.
Description Adds the contents of direct address, the carry flag and the accumulator
contents, result is stored in accumulator.
Example ADDC A, @R1
Before Execution After Execution
A = 05H, CY=0, R1=50H & 50H = 04H A = 09H
A = 05H, CY=1, R1=50H & 50H = 04H A = 0AH

Syntax Flags affected Bytes Cycles

SUBB A,#data CY, OV & AC 2 1
Operation (A) (A) - #-bit data
Description Subtract the 8-bit immediate data with accumulator contents and result is
stored in accumulator.
Example SUBB A, #04H
Before Execution After Execution
A = 05H A = 01H

Syntax Flags affected Bytes Cycles

SUBB A, Rn CY, OV & AC 1 1
Operation (A) (A) - (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Subtract the contents of register Rn with accumulator contents and result is
stored in accumulator.
Example SUBB A, R0
Before Execution After Execution
A = 05H, R0 = 04H A = 01H

Syntax Flags affected Bytes Cycles

SUBB A, direct CY, OV & AC 2 1
Operation (A) (A) - (direct address)
Description Subtract the contents of direct address with accumulator contents and
result is stored in accumulator.
Example SUBB A, 50H

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Before Execution After Execution
A = 05H, 50H = 04H A = 01H

Syntax Flags affected Bytes Cycles

SUBB A, @Ri CY, OV & AC 1 1
Operation (A) (A) - ((Ri))
Description Subtract the contents of indirect RAM address with accumulator contents
and result is stored in accumulator.
Example SUBB A, @R1
Before Execution After Execution
A = 05H, R1 = 50H & 50H = 04H A = 01H

Syntax Flags affected Bytes Cycles

INC A NONE 1 1
Operation (A) (A) + 1
Description Increment the content of accumulator by 1.
Example INC A
Before Execution After Execution
A = 05H A = 06H

Syntax Flags affected Bytes Cycles

INC Rn NONE 1 1
Operation (Rn) (Rn) + 1
Description Increment the content of register Rn by 1.
Example INC R0
Before Execution After Execution
R0 = 05H R0 = 06H

Syntax Flags affected Bytes Cycles

INC direct NONE 2 1
Operation (direct) (direct) + 1
Description Increment the content of direct address by 1.
Example INC 50H
Before Execution After Execution
50H = 05H 50H = 06H

Syntax Flags affected Bytes Cycles

INC @Ri NONE 1 1
Operation ((Ri)) ((Ri)) + 1
Description Increment the content of indirect RAM address by 1.
Example INC @R0
Before Execution After Execution
R0=50H, 50H = 05H R0 = 06H

Syntax Flags affected Bytes Cycles

DEC A NONE 1 1
Operation (A) (A) - 1
Description Decrement the content of Accumulator by 1
Example DEC A
Before Execution After Execution
A = 05H A = 04H

Syntax Flags affected Bytes Cycles

DEC Rn NONE 1 1

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Operation (Rn) (Rn) - 1
Description Decrement the content of register Rn by 1
Example DEC R0
Before Execution After Execution
R0 = 05H R0 = 04H

Syntax Flags affected Bytes Cycles

DEC direct NONE 2 1
Operation (direct) (direct) - 1
Description Decrement the content of direct address by 1
Example DEC 50H
Before Execution After Execution
50H = 05H 50H = 04H

Syntax Flags affected Bytes Cycles

DEC @Ri NONE 1 1
Operation ((Ri)) ((R1)) - 1
Description Decrement the content of indirect address by 1
Example DEC @R0
Before Execution After Execution
R0=50H & 50H = 05H 50H = 04H

Syntax Flags affected Bytes Cycles

INC DPTR NONE 1 2
Operation (DPTR) (DPTR) + 1
Description Increment the content of 16-bit register DPTR address by 1
Example INC DPTR
Before Execution After Execution
DPTR = 1255H i.e. DH =12H, DL = 55H DPTR = 1256H i.e. DH =12H, DL = 56H

Syntax Flags affected Bytes Cycles

MUL AB CY & OV 1 4
Operation (B)15- 8 (A)7-0 AxB
Description Multiply the Contents of Accumulator with the contents of register B.
Lower byte of the result in Accumulator and higher byte of the result in
Register B.
Example MUL AB
Before Execution After Execution
A = 05H & B = 03H 0015H i.e. A = 15H & B = 00H
A = FFH & B = 02H 01FEH i.e. A = FEH & B = 01H

Syntax Flags affected Bytes Cycles

DIV AB CY 1 4
Operation Quotient in A & Remainder in B A/B
Description Divide the Contents of Accumulator with the contents of register B.
Quotient of the result is stored in Accumulator & remainder of the result is
stored in Register B.
Example DIV AB
Before Execution After Execution
A = FBH (251d) & B = 12H (18d) A = 0DH & B = 11H
Quotient = 0DH & Remainder = 11H

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Syntax Flags affected Bytes Cycles
DAA CY & AC 1 1
Operation Decimal Adjustment Accumulator.
If (A)3-0 > 9 or (AC) = 1
Then
Add +6 to (A)3-0

If (A)7-4 > 9 or (CY) = 1

Then
Add +6 to (A)7-4
Description Decimal adjustment of the accumulator according to BCD code.
The data is adjusted in the following two possible cases
i) It adds 6 to the lower 4-bits of A if it is greater than 9 or if AC=1.
ii) It adds 6 to the upper 4-bits of A if it is greater than 9 or if CY=1.
Example MOV A, #45H MOV A, #50H
ADD A, #15H ADD A, #45H
DAA DAA

Result: Result:
4 5 H 5 0 H
+ 1 5 H
+ 5 5 H

5 A H INVALID BCD
+ 6 After DAA A 5 H INVALID BCD
6 0 H Valid BCD + 6 After DAA

1 0 5 H Valid BCD

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
ARITHMETIC INSTRUCTIONS

Cycle
Flags

Byte
Mnemonics Operation
Affected
ADD A, #data 2 1 (A) (A) + 8-bit data CY, OV & AC
ADD A, Rn 1 1 (A) (A) + (Rn) CY, OV & AC
ADD A, direct 2 1 (A) (A)+ (direct address) CY, OV & AC
ADD A, @Ri 1 1 (A) (A) + ((Ri)) CY, OV & AC
ADDC A, #data 2 1 (B) (A) + (C) + 8-bit data CY, OV & AC
ADDC A, Rn 1 1 (B) (A) + (C) + (Rn) CY, OV & AC
ADDC A, direct 2 1 (A) (A) + (C) + (direct address) CY, OV & AC
ADDC A, @Ri 1 1 (A) (A) + (C) + ((Ri)) CY, OV & AC
SUBB A,#data 2 1 (A) (A) - #-bit data CY, OV & AC
SUBB A, Rn 1 1 (A) (A) - (Rn) CY, OV & AC
SUBB A, direct 2 1 (A) (A) - (direct address) CY, OV & AC
SUBB A, @Ri 1 1 (A) (A) - ((Ri)) NONE
INC A 1 1 (A) (A) + 1 NONE
INC Rn 1 1 (Rn) (Rn) + 1 NONE
INC direct 2 1 (direct) (direct) + 1 NONE
INC @Ri 1 1 ((Ri)) ((Ri)) + 1 NONE
DEC A 1 1 (A) (A) - 1 NONE
DEC Rn 1 1 (Rn) (Rn) - 1 NONE
DEC direct 2 1 (direct) (direct) - 1 NONE
DEC @Ri 1 1 ((Ri)) ((R1)) - 1 NONE
INC DPTR 1 2 (DPTR) (DPTR) + 1 NONE
MUL AB 1 4 (B)15- 8 (A)7-0 AxB CY & OV
Quotient in A & CY
DIV AB 1 4
Remainder in B A/B
Decimal Adjustment Accumulator. CY & AC
If (A)3-0 > 9 or (AC) = 1
Then
Add +6 to (A)3-0
DA A 1 1
If (A)7-4 > 9 or (CY) = 1
Then
Add +6 to (A)7-4
DATA TRANSFER INSTRUCTIONS
Syntax Flags affected Bytes Cycles
MOV A, #data NONE 2 1
Operation (A) 8-bit data
Description Moves the 8-bit immediate data to the Accumulator.
Example MOV A, #04H
Before Execution After Execution
A = XX A = 04H

Syntax Flags affected Bytes Cycles

MOV A, Rn NONE 1 1
Operation (A) (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Moves the contents of register Rn to the Accumulator.
Example MOV A, R1
Before Execution After Execution
A = XX & R1 = 05H A = 05H
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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Syntax Flags affected Bytes Cycles

MOV A, direct NONE 2 1
Operation (A) (direct) where direct is the address
Description Moves the contents of direct address to the Accumulator.
Example MOV A, 50H
Before Execution After Execution
A = XX & 50H = 04H A = 04H

Syntax Flags affected Bytes Cycles

MOV A, @Ri NONE 1 1
Operation (A) ((Ri)) where i = 0 & 1 i.e. R0 & R1.
Description Moves the contents of indirect RAM address to the Accumulator.
Example MOV A, @R0
Before Execution After Execution
A = XX, R0 = 50H & 50H = 04H A = 04H

Syntax Flags affected Bytes Cycles

MOV Rn, A NONE 1 1
Operation (Rn) (A) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Moves the contents of Accumulator to the register Rn.
Example MOV R1, A
Before Execution After Execution
R1 = XX & A = 04H R1 = 04H

Syntax Flags affected Bytes Cycles

MOV Rn, #data NONE 2 1
Operation (Rn) 8-bit data
Description Moves the 8-bit immediate data to the register Rn.
Example MOV R1, #04H
Before Execution After Execution
R1 = XX R1 = 04H

Syntax Flags affected Bytes Cycles

MOV Rn, direct NONE 2 2
Operation (Rn) (direct) where direct is the address
Description Moves the contents of direct address to the register Rn.
Example MOV R1, 50H
Before Execution After Execution
R1 = XX & 50H = 04H A = 04H

Syntax Flags affected Bytes Cycles

MOV direct, A NONE 2 1
Operation (direct) (A) where direct is the address
Description Moves the contents of Accumulator to direct address.
Example MOV 50H, A
Before Execution After Execution
50H = XX & A = 04H 50H = 04H

Syntax Flags affected Bytes Cycles

Page | 224
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
MOV direct, Rn NONE 2 2
Operation (direct) (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Moves the contents of register Rn to Accumulator.
Example MOV 50H, R1
Before Execution After Execution
R1 = 04H & 50H = XX 50H = 04H

Syntax Flags affected Bytes Cycles

MOV direct, direct NONE 3 2
Operation (direct) (direct) where direct is the address
Description Moves the contents of direct address to direct address.
Example MOV 50H, 30H
Before Execution After Execution
50H = XX & 30H = 04H 50H = 04H

Syntax Flags affected Bytes Cycles

MOV @Ri, A NONE 1 1
Operation ((Ri)) (A) where i = 0 & 1 i.e. R0 & R1.
Description Moves the contents of Accumulator to indirect RAM address.
Example MOV @R1, 50H
Before Execution After Execution
R1 =30H, 30H = XX & 50H = 04H 30H = 04H

Syntax Flags affected Bytes Cycles

MOV @Ri, #data NONE 2 1
Operation ((Ri)) 8-bit data where i = 0 & 1 i.e. R0 & R1.
Description Moves the 8-bit data to indirect RAM address.
Example MOV @R1, #04H
Before Execution After Execution
R1 =30H & 30H = XX 30H = 04H

Syntax Flags affected Bytes Cycles

MOV @Ri, direct NONE 2 2
Operation ((Ri)) (direct) where i = 0 & 1 i.e. R0 & R1.
Description Moves the contents of direct address to the register indirect RAM address.
Example MOV @R1, 50H
Before Execution After Execution
R1 =30H, 30H = XX & 50H = 04H 30H = 04H

Syntax Flags affected Bytes Cycles

MOV DPTR, #data NONE 3 2
Operation (DPTR) 16-bit data where DPTR = DPH + DPL
Description Moves the 16-bit data to the data pointer register.
Example MOV DPTR, #1234H
Before Execution After Execution
DPTR = XX DPTR = 1234H i.e. DPH = 12H & DPL = 34H

Syntax Flags affected Bytes Cycles

MOVC A,@A+DPTR NONE 1 2
Operation (A) (A + DPTR)

Page | 225
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Description The MOVC instruction moves a byte from the code or program memory to the
accumulator.
The Code Memory address from which the byte will be moved is calculated by
summing the value of the Accumulator with either DPTR.
Example MOVC A,@A+DPTR

Syntax Flags affected Bytes Cycles

MOVC A,@A+PC NONE 1 2
Operation (PC) (PC + 1)
(A) (A+PC)
Description The MOVC instruction moves a byte from the code or program memory to the
accumulator.
The Code Memory address from which the byte will be moved is calculated by
summing the value of the Accumulator with the Program Counter (PC).
The Program Counter (PC) is first incremented by 1 before being summed
with the Accumulator.
Example MOVC A,@A+PC

Syntax Flags affected Bytes Cycles

MOVX A,@Ri NONE 1 2
Operation (A) ((Ri)) where i = 0 & 1 i.e. R0 & R1
Description Moves the indirect external RAM (8-bit address) to the accumulator
Example MOVX A,@R1
Before Execution After Execution
A = XX , R1 =30H & 30H = FFH A = FFH

Syntax Flags affected Bytes Cycles

MOVX A,@DPTR NONE 1 2
Operation (A) ((DPTR))
Description Moves the external RAM (16-bit address) to the accumulator
Example MOVX A,@DPTR
Before Execution After Execution
A = XX, DPTR = 1234H & 1234H = FFH A = FFH

Syntax Flags affected Bytes Cycles

MOVX @Ri,A NONE 1 2
Operation ((Ri)) (A) where i = 0 & 1 i.e. R0 & R1
Description Moves the contents of accumulator to the indirect external RAM (8-bit
address)
Example MOVX @R0,A
Before Execution After Execution
R0 =30H, 30H = XX & A = FFH 30H = FFH

Syntax Flags affected Bytes Cycles

MOVX @DPTR,A NONE 1 2
Operation
Description Moves the contents of Accumulator to the indirect external RAM (16-bit
address)
Example MOVX @DPTR,A
Before Execution After Execution
DPTR = 1234H, 1234H = XX & A = FFH 1234H = FFH

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Syntax Flags affected Bytes Cycles

PUSH direct NONE 2 2
Operation (SP) (SP) + 1
(SP) (direct)
Description Push onto Stack
 The stack pointer is incremented by one. The content of the indicated variable
is then copied into the internal RAM location address by the stack pointer.
 The PUSH instruction supports only direct addressing mode. Therefore,
PUSH A, PUSH R0 etc. are invalid instructions.
Example 1. PUSH 0E0H ; 0E0H is the RAM address of Accumulator.
2. PUSH 0OH ; 00H is the RAM address of R0 of Bank 0.

Syntax Flags affected Bytes Cycles

POP direct NONE 2 2
Operation (direct) (SP)
(SP) (SP) - 1
Description POP from the stack.
 The POP instruction copies the byte pointed to by Stack pointer (SP) to the
location where direct address is indicated and decremented SP by 1.
 The POP instruction supports only direct addressing mode. Therefore,
Therefore, POP A, POP R0 etc. are invalid instructions.
Example POP 0E0H ; 0E0H is the RAM address of Accumulator.
POP 0OH ; 00H is the RAM address of R0 of Bank 0.

Syntax Flags affected Bytes Cycles

XCH A, Rn NONE 1 1
Operation (A) (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Exchanges the contents of register Rn with the contents of Accumulator.
Example XCH A, R1
Before Execution After Execution
A = FFH & R1 = BBH A = BBH & R1 = FFH

Syntax Flags affected Bytes Cycles

XCH A, direct NONE 2 1
Operation (A) (direct)
Description Exchanges the contents of direct address with Accumulator contents.
Example XCH A, 50H
Before Execution After Execution
A = FFH & 50H = BBH A = BBH & 50H = FFH

Syntax Flags affected Bytes Cycles

XCH A, @Ri NONE 1 1
Operation (A) ((Ri)) where i = 0 & 1 i.e. R0 & R1
Description Exchanges the contents of indirect RAM address with accumulator contents.
Example XCH A, @R0
Before Execution After Execution
A = FFH, R0 = 50H & 50H = BBH A = BBH, R0 = 50H & 50H = FFH

Syntax Flags affected Bytes Cycles

XCHD A,@Ri NONE 1 1

Page | 227
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Operation (A)3-0 ((Ri))3-0 where i = 0 & 1 i.e. R0 & R1
Description Exchanges the low-order nibble indirect RAM with the accumulator contents.
Example XCHD A,@R0
Before Execution After Execution
A = FFH, R0 = 50H & 50H = BBH A = BFH, R0 = 50H & 50H = FBH

DATA TRANSFER INSTRUCTIONS

Cycle
Flags

Byte
Mnemonics Operation
Affected
MOV A, #data 2 1 (A) 8-bit data NONE
MOV A, Rn 1 1 (A) (Rn) NONE
MOV A, direct 2 1 (A) (direct) NONE
MOV A, @Ri 1 1 (A) ((Ri)) NONE
MOV Rn, A 1 1 (Rn) (A) NONE
MOV Rn, #data 2 1 (Rn) 8-bit data NONE
MOV Rn, direct 2 2 (Rn) (direct) NONE
MOV direct, A 2 1 (direct) (A) NONE
MOV direct, Rn 2 2 (direct) (Rn) NONE
MOV direct, direct 3 2 (direct) (direct) NONE
MOV @Ri, A 1 1 ((Ri)) (A) NONE
MOV @Ri, #data 2 1 ((Ri)) 8-bit data NONE
MOV @Ri, direct 2 2 ((Ri)) (direct) NONE
MOV DPTR, #data 3 2 (DPTR) 16-bit data NONE
MOVC A,@A+DPTR 1 2 (A) (A + DPTR) NONE
1 2 (PC) (PC + 1) NONE
MOVC A,@A+PC
(B) (A+PC)
MOVX A,@Ri 1 2 (A) ((Ri)) NONE
MOVX A,@DPTR 1 2 (A) ((DPTR)) NONE
MOVX @Ri,A 1 2 ((Ri)) (A) NONE
MOVX @DPTR,A 1 2 ((DPTR)) (A) NONE
2 2 (SP) (SP) + 1 NONE
PUSH direct
(SP) (direct)
2 2 (direct) (SP) NONE
POP direct
(SP) (SP) - 1
XCH A, Rn 1 1 (B) (Rn) NONE
XCH A, direct 2 1 (B) (direct) NONE
XCH A, @Ri 1 1 (A) ((Ri)) NONE
XCHD A,@Ri 1 1 (A)3-0 ((Ri))3-0 NONE

LOGICAL INSTRUCTIONS
Syntax Flags affected Bytes Cycles
ANL A,#data NONE 2 1
Operation (A) (A) AND 8-bit data
Description AND the content of 8-bit immediate data with the content of accumulator
and result is stored in accumulator.
Example ANL A,#0FH
Before Execution After Execution
A = FFH A = 0FH

Syntax Flags affected Bytes Cycles

ANL A,Rn NONE 1 1

Page | 228
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Operation (A) (A) AND (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description AND the content of register Rn with the content of accumulator and result is
stored in accumulator.
Example ANL A,R1
Before Execution After Execution
A = FFH & R1 = 0FH A = OFH

Syntax Flags affected Bytes Cycles

ANL A,direct NONE 2 1
Operation (A) (A) AND (direct address) where direct is the address
Description AND the content of direct address with the content of accumulator and result
is stored in accumulator.
Example ANL A,50H
Before Execution After Execution
A = FFH & 50H = 0FH A = OFH

Syntax Flags affected Bytes Cycles

ANL A,@Ri NONE 1 1
Operation (A) (A) AND (Ri)) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description AND the content of indirect address with the content of accumulator and
result is stored in accumulator.
Example ANL A,@R1
Before Execution After Execution
A = FFH, R1 = 50H & 50H = F0H A = F0H

Syntax Flags affected Bytes Cycles

ANL direct,A NONE 2 1
Operation (direct) (direct) AND (A)
Description AND the content of accumulator with the content of direct address and result
is stored in direct address.
Example ANL 50H,A
Before Execution After Execution
50H = FFH & A = 0FH 50H = 0FH

Syntax Flags affected Bytes Cycles

ANL direct,#data NONE 3 2
Operation (direct) (direct) AND 8-bit data
Description AND the content of 8-bit immediate data with the content of direct address
and result is stored in direct address.
Example ANL 50H,#0FH
Before Execution After Execution
50H= AAH 50H= 0AH

Syntax Flags affected Bytes Cycles

ORL A,#data NONE 2 1
Operation (A) (A) OR 8-bit data
Description OR the content of Accumulator with the 8-bit immediate data and result is
stored in accumulator.
Example ORL A,#00H
Before Execution After Execution
A = 75H & R0 = 00H A = 75H

Page | 229
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Syntax Flags affected Bytes Cycles

ORL A,Rn NONE 1 1
Operation (A) (A) OR (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description OR the content of register Rn with the content of accumulator and result is
stored in accumulator.
Example ORL A,R0
Before Execution After Execution
A = 75H & R0 = 00H A = 75H

Syntax Flags affected Bytes Cycles

ORL A,direct NONE 2 1
Operation (A) (A) OR (direct) where direct is the address
Description OR the content of direct address with the content of accumulator and result is
stored in accumulator.
Example ORL A,50H
Before Execution After Execution
A = 75H & 50H = FFH A=FFH

Syntax Flags affected Bytes Cycles

ORL A,@Ri NONE 1 1
Operation (A) (A) OR ((Ri)) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description OR the content of indirect address with the content of accumulator and result
is stored in accumulator.
Example ORL A,@R0
Before Execution After Execution
A = FFH, R1 = 50H & 50H = 00H A = FFH

Syntax Flags affected Bytes Cycles

ORL direct,A NONE 2 1
Operation (A) (direct) OR (A) where direct is the address
Description OR the content of accumulator with the content of direct address and result is
stored in direct address.
Example ORL 50H,A
Before Execution After Execution
A = FFH & 50H = FFH A = FFH

Syntax Flags affected Bytes Cycles

ORL direct,#data NONE 3 2
Operation (direct) (direct) OR 8 - bit data
Description OR the content of 8-bit immediate data with the content of direct address and
result is stored in direct address.
Example ORL 20H,#50H
Before Execution After Execution
20H = 32H & 8-bit data (50H) 20H = 72H

Syntax Flags affected Bytes Cycles

XRL A,#data NONE 2 1
Operation (A) (A) EX-OR 8-bit data
Description Exclusive OR the 8-bit immediate data with accumulator content and result
is stored in accumulator.

Page | 230
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Example XRL A,#09H
Before Execution After Execution
A = 39H & 8-bit data = 09H A = 30H

Syntax Flags affected Bytes Cycles

XRL A,Rn NONE 1 1
Operation (A) (A) EX-OR (Rn) where n = 0,1,2,3,4,5,6,7 i.e. R0 to R7
Description Exclusive OR the content of register Rn with accumulator content and result
is stored in accumulator.
Example XRL A,R1
Before Execution After Execution
A = 39H & R1 = 09H A = 30H

Syntax Flags affected Bytes Cycles

XRL A,direct NONE 2 1
Operation (A) (A) EX-OR (direct address) where direct is the address
Description Exclusive OR the content of direct address with accumulator contents and
result is stored in accumulator.
Example XRL A,50H
Before Execution After Execution
A = 39H & 50H = 09H A = 30H

Syntax Flags affected Bytes Cycles

XRL A,@Ri NONE 1 1
Operation (A) (A) EX-OR ((Ri)) where i = 0 & 1 i.e. R0 & R1
Description Exclusive OR the content of indirect RAM address with accumulator content
and result is stored in accumulator.
Example XRL A,@R0
Before Execution After Execution
A = 39H, R0 = 50H & 50H = 09H A = 30H

Syntax Flags affected Bytes Cycles

XRL direct,A NONE 2 1
Operation (A) (direct) EX-OR (A)
Description Exclusive OR the content of direct address with accumulator contents and
result is stored in direct address.
Example XRL 50H,A
Before Execution After Execution
50H = 39H & A = 09H 50H = 30H

Syntax Flags affected Bytes Cycles

XRL direct,#data NONE 3 2
Operation (A) (direct) EX-OR 8-bit data
Description Exclusive OR the content of direct address with 8-bit data and result is
stored in direct address.
Example XRL 50H,#09H
Before Execution After Execution
50H = 39H & A = 09H 50H = 30H

Syntax Flags affected Bytes Cycles

CLR A NONE 1 1

Page | 231
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Operation Clear Accumulator
(A) 0
Description The content of Accumulator is cleared (A=00H). All the bits of the accumulator
are set to 0.
Example CLR A
Before Execution After Execution
A = FFH A = 00H

Syntax Flags affected Bytes Cycles

CPL A NONE 1 1
Operation Complement Accumulator

Description The content of Accumulator is Complemented. The result is 1s complement of

the accumulator i.e. 0s become 1s & 1s become 0s.
Example CPL A
Before Execution After Execution
A = 00H A = FFH

Syntax Flags affected Bytes Cycles

SWAP A NONE 1 1
Operation SWAP nibbles within the Accumulator
(A) [ (A)7- 4 (A)3-0 ]
Description The SWAP instruction interchanges the lower nibble (A)3-0 with the upper
nibble (A)7-4 within the Accumulator.
Example SWAP A
Before Execution After Execution
A = AFH A = FAH

Syntax Flags affected Bytes Cycles

RL A NONE 1 1
Operation Rotate Accumulator Left
An+1 An where n = 0 to 6
A0 A7
Description The RL A instruction rotates the eight bits in the accumulator left one bit
position. The bit 7 of the accumulator is rotated into bit 0, bit 0 into bit 1, bit 1
into bit 2, and so on.

Example RL A
Before Execution After Execution
A = C2 H A = 85H

Syntax Flags affected Bytes Cycles

RLC A CY 1 1
Operation Rotate Accumulator Left through the Carry Flag.
An+1 An where n = 0 to 6
A0 C
C A7

Page | 232
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Description The 8-bits in the accumulator & the carry flag are together rotated 1-bit to the
left. The bit-7 moves into the Carry flag. The original state of the carry flag
moves into the bit-0 position.

Example RLC A
Before Execution After Execution
A = C2 H & CY = 0 A = 84H & CY =1

Syntax Flags affected Bytes Cycles

RR A NONE 1 1
Operation Rotate Accumulator Right through the carry flag.
An An+1 where n = 0 to 6
A7 A0
Description The 8-bits in the accumulator are rotated 1-bit to the right i.e. bit-0 is rotated
into the bit-7 position.

Example RR A
Before Execution After Execution
A = C2 H A = 61H

Syntax Flags affected Bytes Cycles

RRC A CY 1 1
Operation Rotate Accumulator Right through the Carry Flag.
An An+1 where n = 0 to 6
A7 C
C A0
Description The 8-bits in the accumulator & the carry flag are together rotated 1-bit to the
right. Bit-0 moves into the Carry flag. The original state of the carry flag moves
into the bit-7 position.

Example RRC A
Before Execution After Execution
A = C2 H & CY = 0 A = 61H & CY = 0

Page | 233
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
LOGICAL INSTRUCTIONS

Cycle
Flags

Byte
Mnemonics Operation
Affected
ANL A,#data 2 1 (A) (A) AND 8-bit data NONE
ANL A,Rn 1 1 (A) (A) AND (Rn) NONE
ANL A,direct 2 1 (A) (A) AND (direct address) NONE
ANL A,@Ri 1 1 (A) (A) AND (Ri)) NONE
ANL direct,A 2 1 (direct) (direct) AND (A) NONE
ANL direct,#data 3 2 (direct) (direct) AND 8-bit data NONE
ORL A,#data 2 1 (A) (A) OR 8-bit data NONE
ORL A,Rn 1 1 (A) (A) OR (Rn) NONE
ORL A,direct 2 1 (A) (A) OR (direct) NONE
ORL A,@Ri 1 1 (A) (A) OR ((Ri)) NONE
ORL direct,A 2 1 (A) (direct) OR (A) NONE
ORL direct,#data 3 2 (direct) (direct) OR 8 - bit data NONE
XRL A,#data 2 1 (A) (A) EX-OR 8-bit data NONE
XRL A,Rn 1 1 (B) (A) EX-OR (Rn) NONE
XRL A,direct 2 1 (A) (A) EX-OR (direct address) NONE
XRL A,@Ri 1 1 (A) (A) EX-OR ((Ri)) NONE
XRL direct,A 2 1 (A) (direct) EX-OR (A) NONE
CLR A 1 1 (A) 0 NONE
CPL A 1 1 NONE

SWAP A 1 1 (B) [ (A)7- 4 (A)3-0 ] NONE

1 1 Rotate Accumulator Left NONE
RL A An+1 An where n = 0 to 6
A0 A7
1 1 Rotate Accumulator Left through the CY
Carry Flag.
RLC A An+1 An where n = 0 to 6
A0 C
C A7
1 1 Rotate Accumulator Right through NONE
the carry flag.
RR A
An An+1 where n = 0 to 6
A7 A0
1 1 Rotate Accumulator Right through CY
the Carry Flag.
RRC A An An+1 where n = 0 to 6
A7 C
C A0

Boolean Instructions
Syntax Flags affected Bytes Cycles
CLR C CY 1 1
Operation (CY) 0
Description Clear the carry flag bit.
Example CLR C
Before Execution After Execution
CY = 1 CY = 0

Page | 234
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Syntax Flags affected Bytes Cycles

CLR bit NONE 2 1
Operation (bit) 0
Description Clear the specified bit.
Example CLR P0.0
Before Execution After Execution
P0.0 = X P0.0 = 0

Syntax Flags affected Bytes Cycles

SETB C CY 1 1
Operation (CY) 1
Description SET the carry flag bit.
Example SETB C
Before Execution After Execution
CY = X CY = 1

Syntax Flags affected Bytes Cycles

SETB bit NONE 2 1
Operation (bit) 1
Description SET the specified bit.
Example SETB ACC.1
Before Execution After Execution
ACC.1 = X ACC.1 = 1

Syntax Flags affected Bytes Cycles

CPL C CY 1 1
Operation (CY) NOT(CY)
Description Complement the carry flag bit.
Example CPL C
Before Execution After Execution
CY = 0 CY = 1

Syntax Flags affected Bytes Cycles

CPL bit NONE 2 1
Operation (bit) NOT(bit)
Description Complement the specified bit.
Example CPL ACC.5
Before Execution After Execution
ACC.5 = 1 ACC.5 = 0

Syntax Flags affected Bytes Cycles

ANL C,bit CY 2 2
Operation (C) (C) AND (bit)
Description AND the content of carry flag bit with a source bit and the result is placed in
carry flag.
Example ANL C, P1.7
Before Execution After Execution
CY = 1 & P1.7 = 1 CY = 1

Page | 235
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set

Syntax Flags affected Bytes Cycles

ANL C,/bit CY 2 2
Operation (C) (C) AND [ NOT(bit) ]
Description AND the content of carry flag bit with a complement of source bit and the
result is placed in carry flag.
Example ANL C,/ACC.7
Before Execution After Execution
CY = 1 & ACC.7 = 0 CY = 1

Syntax Flags affected Bytes Cycles

ORL C,bit CY 2 2
Operation (C) (C) OR (bit)
Description OR the content of carry flag bit with a source bit and the result is placed in
carry flag.
Example ORL C,P0.0
Before Execution After Execution
CY = 0 & P0.0 = 1 CY = 1

Syntax Flags affected Bytes Cycles

ORL C,/bit CY 2 2
Operation (C) (C) OR [ NOT(bit) ]
Description OR the content of carry flag bit with a complement of source bit and the
result is placed in carry flag.
Example ORL C,/ACC.0
Before Execution After Execution
CY = 0 & ACC.0 = 0 CY = 1

Syntax Flags affected Bytes Cycles

MOV C,bit CY 2 1
Operation (C) (bit)
Description Move the content of source bit to carry flag.
Example MOV C,P1.7
Before Execution After Execution
CY = X & P1.7 = 1 CY = 1

Syntax Flags affected Bytes Cycles

MOV bit,C NONE 2 2
Operation (bit) (C)
Description Move the content of carry flag to destination bit.
Example MOV ACC.0,C
Before Execution After Execution
ACC.0 = X & CY = 1 ACC.0 = 1

Page | 236
Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Boolean Instructions

Cycle
Flags

Byte
Mnemonics Operation
Affected
CLR C 1 1 (CY) 0 CY
CLR bit 1 1 (bit) 0 NONE
SETB C 1 1 (CY) 1 CY
SETB bit 2 1 (bit) 1 NONE
CPL C 1 1 (CY) NOT(CY) CY
CPL bit 2 1 (bit) NOT(bit) NONE
ANL C,bit 2 2 (C) (C) AND (bit) CY
ANL C,/bit 2 2 (C) (C) AND [ NOT(bit) ] CY
ORL C,bit 2 2 (C) (C) OR (bit) CY
ORL C,/bit 2 2 (C) (C) OR [ NOT(bit) ] CY
MOV C,bit 2 1 (C) (bit) CY
MOV bit,C 2 2 (bit) (C) NONE

Program Branching Instructions

Syntax Flags affected Bytes Cycles

ACALL addr11 NONE 2 2
Operation (PC) (PC) + 2
(SP) (SP) + 1
(SP) (PC)7-0
(SP) (SP) + 1
(SP) (PC)15-8
(PC)10-0 Page address
Description Absolute subroutine call. Transfer control to a subroutine.
 ACALL unconditionally calls a subroutine located at the indicated address.
The instruction increments the PC twice to obtain the address of the following
instruction, then pushes 16-bit result onto the stack i.e. low order byte 1st &
increment the stack pointer to store higher-order byte.
 ACALL is a 2-byte instruction, in which 5-bits are used for the opcode and the
remaining 11-bits are used for the target subroutine address.
 A 11-bit address limits the range to 2 Kbytes.

Syntax Flags affected Bytes Cycles

LCALL addr16 NONE 3 2
Operation (PC) (PC) + 3
(SP) (SP) + 1
(SP) (PC)7-0
(SP) (SP) + 1
(SP) (PC)15-8
(PC) Page address
Description  Long call. Transfer control to a subroutine. LCALL unconditionally calls a
subroutine located at the indicated address. The instruction increments the
PC thrice to obtain the address of the next instruction & then pushes 16-bit
result onto the stack i.e. low order byte 1st & increment the stack pointer to
store higher-order byte.
 LCALL is a 2-byte instruction, in which 16-bits are used for the opcode and
for the target subroutine address.
 A 16-bit address may be anywhere within the 64 Kbytes of program memory.

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Syntax Flags affected Bytes Cycles

RET NONE 1 2
Operation (PC)15-8 (SP)
(SP) (SP) - 1
(PC)7-0 (SP)
(SP) (SP) - 1
Description Returns from subroutine.
 RET instruction is used to return from a subroutine previously entered by
instruction LCALL or ACALL. The top two bytes of the stack are popped in the
program counter (PC) & program execution continues at this new address.
 After popping the top two bytes of the stack into the program counter, the
stack pointer (SP) is decremented by 2.
Example
Before Execution After Execution

Syntax Flags affected Bytes Cycles

RETI NONE 1 2
Operation (PC)15-8 (SP)
(SP) (SP) - 1
(PC)7-0 (SP)
(SP) (SP) - 1
Description Absolute subroutine call.
 RET instruction is used at the end of an Interrupt Service Routine (ISR). The
top two bytes of the stack are popped in the program counter (PC), the stack
pointer (SP) is decremented by 2.

Syntax Flags affected Bytes Cycles

AJMP addr11 NONE 2 2
Operation (PC) (PC) + 2
(PC)10-0 (A)10-0
Description Absolute subroutine call
 The AJMP instruction transfers program execution to the specified address.
 The address is formed by combining the 5 high-order bits of the address of
the following instruction (for A15-A11), the 3 high-order bits of the opcode (for
A10-A8), and the second byte of the instruction (for A7-A0).
 The destination address must be located in the same 2 Kbyte block of program
memory as the opcode following the AJMP instruction.
Example AJMP LABEL

Syntax Flags affected Bytes Cycles

LJMP addr16 NONE 3 2
Operation (PC) (PC) + 2
(PC) (PC) + rel
Description Long Jump.

The LJMP instruction transfers program execution to the specified 16-bit

address.
 Jump unconditionally to the specified address (i.e. LABEL) by loading high
order and low order bytes of the PC respectively.

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
 Its range is -32768 bytes to +32767 bytes.
 The destination may be anywhere within the 64 Kbytes of program memory.
Example LJMP LABEL

Syntax Flags affected Bytes Cycles

SJMP rel NONE 2 2
Operation (PC) (PC) + 2
(PC) (PC) + rel
Description Short Jump.
Jump unconditionally to the specified address (i.e. LABEL).
Its range is -128 bytes to+127 bytes.
Example 0091 MOV R0,#05H
0092 SJMP, NEXT
0093 MOV P1,A
0094 NEXT: INC R1
Before Execution After Execution
PC = 0092 PC = 0094

Syntax Flags affected Bytes Cycles

JC rel NONE 2 2
Operation (PC) (PC) + 2
If CY = 1
Then,
(PC) (PC) + rel
Description Jump if carry is set.
If CY = 1, jump to the address indicated otherwise proceeds (Execute) with the
next instruction.
Example 0090 SETB C
0091 JC, NEXT
0092 MOV P1,A
0093 NEXT: INC R1
Before Execution After Execution
CY = 1 & PC = 0091 PC = 0093

Syntax Flags affected Bytes Cycles

JNC rel NONE 2 2
Operation (PC) (PC) + 2
If CY = 0
Then,
(PC) (PC) + rel
Description Jump if not carry.
If CY = 0, jump to the address indicated otherwise proceeds (Execute) with the
next instruction.
Example 0090 SETB C
0091 JNC, NEXT
0092 MOV P1,A
0093 NEXT: INC R1
Before Execution After Execution
CY = 1 & PC = 0091 PC = 0092

Syntax Flags affected Bytes Cycles

JB bit,rel NONE 3 2

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Operation (PC) (PC) + 3
If (bit) = 1
Then,
(PC) (PC) + rel
Description Jump if bit set.
If the indicated bit is SET (1), jump to the address indicated otherwise
proceeds (Execute) with the next instruction.
Example 0090 SETB ACC.0
0091 JB ACC.0, NEXT
0092 MOV P1,A
0093 NEXT: INC R1
Before Execution After Execution
ACC.0 = 1 & PC = 0091 ACC.0 = 1 & PC = 0093

Syntax Flags affected Bytes Cycles

JBC bit,rel NONE 3 2
Operation (PC) (PC) + 3
If (bit) = 1
Then,
(PC) (PC) + rel
Description Jump if bit set & clear it.
If the bit = 1, then processor jump to the specified address (i.e. LABEL), at the
same time the bit is cleared to zero i.e. bit = 0.
If the bit = 0, then processor proceeds (Execute) with the next instruction.
Example 0090 SETB ACC.0
0091 JBC ACC.0, NEXT
0092 MOV P1,A
0093 NEXT: INC R1
Before Execution After Execution
ACC.0 = 1 & PC = 0091 ACC.0 = 0 & PC = 0093

Syntax Flags affected Bytes Cycles

JMP @A+DPTR NONE 1 2
Operation (PC) (A) + (DPTR)
Description Jump indirect relative to the DPTR.
Jump unconditionally to the specified address (i.e. LABEL). The target address
is provided by the total sum of Accumulator & the content of DPTR register.
This instruction is not widely used.
Example 0090 MOV A,#24H
0091 MOV DPTR,#0070H
0092 JMP @A+DPTR
0093 MOV P1,A
0094 INC R1
Before Execution After Execution
A = 24H, DPTR = 0070H & PC = 0092 PC = 0094

Syntax Flags affected Bytes Cycles

JNZ rel NONE 2 2
Operation (PC) (PC) + 2
If A ≠ 0
Then,
(PC) (PC) + rel
Description Jump if Accumulator is NOT zero.

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
If ACC ≠ 0, then processor jump to the specified address (i.e. LABEL),
If ACC = 0, then processor proceeds (Execute) with the next instruction.
Example 0090 MOV A,#05H
0091 ADD A,#03H
0092 JNZ, NEXT
0093 MOV P1,A
0094 NEXT: INC R1
Before Execution After Execution
A = 08H & PC = 0092 PC = 0094

Syntax Flags affected Bytes Cycles

JZ rel NONE 2 2
Operation (PC) (PC) + 2
If A = 0
Then,
(PC) (PC) + rel
Description Jump if Accumulator is zero.
If ACC = 0, then processor jump to the specified address (i.e. LABEL),
If ACC ≠ 0, then processor proceeds (Execute) with the next instruction.
Example 0090 MOV A,#05H
0091 ADD A,#03H
0092 JZ, NEXT
0093 MOV P1,A
0094 NEXT: INC R1
Before Execution After Execution
A = 08H & PC = 0092 PC = 0093

Syntax Flags affected Bytes Cycles

CJNE A,direct,rel CY 3 2
Operation (PC) (PC) + 3
If (A) ≠ (direct)
then
(PC) (PC) + relative address

If (A) < (direct)

then
(C) 1
else
(C) 0
Description Compare and Jump if not equal.
 The magnitudes of the source byte and destination byte are compared. If they
are not equal, it jumps to the target.

Syntax Flags affected Bytes Cycles

CJNE A,#data,rel CY 3 2
Operation (PC) (PC) + 3
If (A) ≠ data
then
(PC) (PC) + relative address

If (A) < (data)

then
(C) 1

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
else
(C) 0
Description Compare and Jump if not equal.
The magnitudes of the source byte and destination byte are compared. If they
are not equal, it jumps to the target.

Syntax Flags affected Bytes Cycles

CJNE Rn,#data,rel CY 3 2
Operation (PC) (PC) + 3
If (Rn) ≠ data
then
(PC) (PC) + relative address

If (Rn) < (data)

then
(C) 1
else
(C) 0
Description Compare and Jump if not equal.
The magnitudes of the source byte and destination byte are compared. If they
are not equal, it jumps to the target.

Syntax Flags affected Bytes Cycles

CJNE @Ri,#data,rel CY 3 2
Operation (PC) (PC) + 3
If ((Ri)) ≠ data
then
(PC) (PC) + relative address

If ((Ri)) < (data)

then
(C) 1
else
(C) 0
Description Absolute subroutine call
Example Compare and Jump if not equal.
The magnitudes of the source byte and destination byte are compared. If they
are not equal, it jumps to the target.

Syntax Flags affected Bytes Cycles

DJNZ Rn,rel NONE 2 2
Operation (PC) (PC) + 2
(Rn) (Rn) - 1
If (Rn) ≠ 0 i.e. (Rn) > 0 & (Rn) < 0
Then,
(PC) (PC) + rel
Description Decrement and Jump if not zero.
Decrement the content of Rn register & then checks the condition i.e. Rn ≠ 0.
If Rn ≠ 0, jump to the specified address (i.e. LABEL),
If Rn = 0, then processor proceeds (Execute) with the next instruction.
Example 0091 MOV R0,#05H
0092 DJNZ R0, NEXT
0093 MOV P1,A

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
0094 NEXT: INC R1
Before Execution After Execution
Rn = 05H & PC = 0092 PC = 0094

Syntax Flags affected Bytes Cycles

DJNZ direct,rel 3 2
Operation (PC) (PC) + 2
(direct) (direct) - 1
If (direct) ≠ 0 i.e. (direct) > 0 & (direct) < 0
Then,
(PC) (PC) + rel
Description Decrement and Jump if not zero.
Decrement the content of direct address & then checks the condition i.e.
(direct) ≠ 0.
If (direct) ≠ 0, jump to the specified address (i.e. LABEL),
If (direct) = 0, then processor proceeds (Execute) with the next instruction.
Example 0091 MOV R0,#05H
0092 DJNZ 50H, NEXT
0093 MOV P1,A
0094 NEXT: INC R1
Before Execution After Execution
direct = 50H, 50H = 01 & PC = 0092 PC = 0094

Syntax Flags affected Bytes Cycles

NOP NONE 1 1
Operation (PC) (PC) + 1
Description No operation
 NOP instruction performs NO OPERATION & execution continues with the
next instruction.
 It is sometimes used for timing delays to waste clock cycles.
 This instruction only updates the PC to point to the next instruction following
up.
Example 0091 MOV A,#25H
0092 ADD A,#20H
0093 NOP
0094 INC A
END
Before Execution After Execution
PC = 0093H PC = 0094H

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
Program Branching Instructions

Cycle
Flags

Byte
Mnemonics Operation
Affected
(PC) (PC) + 2
(SP) (SP) + 1
(SP) (PC)7-0
ACALL addr11 2 2 NONE
(SP) (SP) + 1
(SP) (PC)15-8
(PC)10-0 Page address
(PC) (PC) + 3
(SP) (SP) + 1
(SP) (PC)7-0
LCALL addr16 3 2 NONE
(SP) (SP) + 1
(SP) (PC)15-8
(PC) Page address
(PC)15-8 (SP)
(SP) (SP) - 1
RET 1 2 NONE
(PC)7-0 (SP)
(SP) (SP) - 1
(PC)15-8 (SP)
(SP) (SP) - 1
RETI 1 2 NONE
(PC)7-0 (SP)
(SP) (SP) - 1
(PC) (PC) + 2
AJMP addr11 2 2 NONE
(PC)10-0 (A)10-0
(PC) (PC) + 2
LJMP addr16 3 2 NONE
(PC) (PC) + rel
(PC) (PC) + 2
SJMP rel 2 2 NONE
(PC) (PC) + rel
(PC) (PC) + 2
If CY = 1
JC rel 2 2 NONE
Then,
(PC) (PC) + rel
(PC) (PC) + 2
If CY = 0
JNC rel 2 2 NONE
Then,
(PC) (PC) + rel
(PC) (PC) + 3
If (bit) = 1
JB bit,rel 3 2 NONE
Then,
(PC) (PC) + rel
(PC) (PC) + 3
If (bit) = 1
JBC bit,rel 3 2 NONE
Then,
(PC) (PC) + rel
JMP @A+DPTR 1 2 (PC) (A) + (DPTR) NONE
(PC) (PC) + 2
If A ≠ 0
JNZ rel 2 2 NONE
Then,
(PC) (PC) + rel
(PC) (PC) + 2
If A = 0
JZ rel 2 2 NONE
Then,
(PC) (PC) + rel

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Microprocessor & Microcontroller Annexure-2: 8051 Instruction Set
(PC) (PC) + 3
If (A) ≠ (direct)
then
(PC) (PC) + relative address
CJNE A,direct,rel 3 2 CY
If (A) < (direct)
then
(C) 1
else
(C) 0
(PC) (PC) + 3
If (A) ≠ data
then
(PC) (PC) + relative address
CJNE A,#data,rel 3 2 CY
If (A) < (data)
then
(C) 1
else
(C) 0
(PC) (PC) + 3
If (Rn) ≠ data
then
(PC) (PC) + relative address
CJNE Rn,#data,rel 3 2 CY
If (Rn) < (data)
then
(C) 1
else
(C) 0
(PC) (PC) + 3
If ((Ri)) ≠ data
then
(PC) (PC) + relative address
CJNE @Ri,#data,rel 3 2 CY
If ((Ri)) < (data)
then
(C) 1
else
(C) 0
(PC) (PC) + 2
(Rn) (Rn) - 1
DJNZ Rn,rel 2 2 If (Rn) ≠ 0 i.e. (Rn) > 0 & (Rn) < 0 NONE
Then,
(PC) (PC) + rel
(PC) (PC) + 2
(direct) (direct) - 1
If (direct) ≠ 0 i.e. (direct) > 0 &
DJNZ direct,rel 3 2 NONE
(direct) < 0
Then,
(PC) (PC) + rel
NOP 1 1 (PC) (PC) + 1 NONE

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