1) Explain RISC design philosophy with comparison of CISC.

Here’s a comparison of RISC vs. CISC:

Feature RISC CISC

Instruction Set Limited, simpler instructions Large, complex instructions
Faster, as each instruction typically Slower, as some instructions may
Execution Speed
takes a single cycle take multiple cycles
Simpler hardware due to fewer More complex hardware to
Processor Design
instructions support a large set of instructions
More instructions are needed for a Fewer instructions per task,
Memory Usage
task, so more memory is accessed reducing memory access
 Feature RISC CISC
Generally more power-efficient Often less power-efficient due to
Power Efficiency
because of simpler operations complex operations
Common in mobile devices and Found in older PCs and larger
Use Case
embedded systems systems
Example
ARM, MIPS x86
Architectures

2) Explain ARM philosophy.

3) With neat sketch explain ARM based Embedded system hardware components.
4) Write a short note on AMBA bus protocol.
5) Explain memory controllers and Interrupt controllers.
6) Explain the memory hierarchy in an embedded system with necessary sketch.
7) Explain the embedded system software in brief.
8) Explain the ARM core data flow model mode model with neat diagram.

Data Flow Model

The Data Flow Model in ARM processors shows how data is managed within the core:

1. Registers: ARM has a set of fast-access storage locations called registers. When data is
needed for calculations, it's loaded into these registers.
2. ALU (Arithmetic Logic Unit): The ALU performs arithmetic (like addition, subtraction) and
logical operations (like AND, OR). Data in registers is processed by the ALU.
3. Load/Store Operations: ARM uses a load/store architecture, meaning data must be loaded
into registers before operations can be done. After calculations, data is either stored back in
memory or used in further operations.
4. Pipelines: ARM processors use a pipeline system that breaks down instructions into smaller
steps, so multiple instructions can be processed simultaneously, increasing speed.

Mode Model

The Mode Model refers to different states or modes the ARM processor can operate in,
depending on tasks and conditions:

1. User Mode: Normal mode where applications run.

2. System Mode: A privileged mode used by the operating system to control the system.
3. Interrupt Modes: These modes are activated when specific interrupts occur:
o FIQ (Fast Interrupt Request) Mode: Used for handling high-priority interrupts
quickly.
o IRQ (Interrupt Request) Mode: Handles standard interrupts from devices.
4. Supervisor Mode: Used when the system is reset or an error occurs, allowing the OS to
regain control safely.
Sketch the bit structure of cpsr and explain conditional flags and T,I,F bits.

1. N, Z, C, V: These are the conditional flags.

2. T, I, F: These bits control specific modes and interrupt settings.

Explanation of Conditional Flags and T, I, F Bits

Conditional Flags

The conditional flags indicate results from operations and affect conditional execution:

• N (Negative) - Bit 31: Set to 1 if the result of the last operation was negative.
• Z (Zero) - Bit 30: Set to 1 if the result was zero.
• C (Carry) - Bit 29: Set to 1 if there was a carry out (overflow) from the last addition or a
borrow in subtraction.
• V (Overflow) - Bit 28: Set to 1 if there was an arithmetic overflow, meaning the result was
too large for the number format.

These flags help the processor decide if certain instructions should execute, based on the
results of previous operations.

T, I, F Bits

These bits control the mode of execution and interrupts:

• T (Thumb Mode) - Bit 5: Set to 1 if the processor is in Thumb mode, where it executes a
compact 16-bit instruction set for higher efficiency.
• I (IRQ Disable) - Bit 7: When set to 1, it disables IRQ (Interrupt Request), preventing lower-
priority interrupts from interrupting the CPU.
• F (FIQ Disable) - Bit 6: When set to 1, it disables FIQ (Fast Interrupt Request), stopping high-
priority, fast interrupts.

11) What is meant by pipeline? Explain three stage pipeline.

In ARM Embedded Systems, a pipeline is a technique used to improve processing speed by

breaking down instructions into smaller stages, allowing multiple instructions to be processed
simultaneously. This is similar to an assembly line, where each stage of the pipeline
completes part of the instruction.

Three-Stage Pipeline in ARM

In a three-stage pipeline, each instruction goes through three main stages:

 1. Fetch (F): In this stage, the instruction is fetched (retrieved) from memory.
2. Decode (D): The fetched instruction is then decoded to understand what operation it needs
to perform.
3. Execute (E): Finally, the instruction is executed, and the result is processed.

While one instruction is in the Fetch stage, the next instruction can be in the Decode stage,
and a third instruction can be in the Execute stage. This overlapping of stages helps the
processor work faster, as it can handle multiple instructions at once without waiting for each
instruction to complete before starting the next.

12) Describe Exceptions, Interrupts and the Vector table.

When an exception or interrupt occurs, the processor sets the pc to a specific

memory address. The address is within a special address range called the vector
table. The entries in the vector table are instructions that branch to specific routines
designed to handle a particular exception or interrupt.
The memory map address 0x00000000 is reserved for the vector table, a set of 32-
bit words. On some processors the vector table can be optionally located at a higher
address in memory (starting at the offset 0xffff0000). Operating systems such as
Linux and Microsoft's embedded products can take advantage of this feature.
When an exception or interrupt occurs, the processor suspends normal execution
and starts loading instructions from the exception vector table (see Table 2.6). Each
vector table entry contains a form of branch instruction pointing to the start of a
specific routine:
13) Explain 3 different types of ARM core extensions.

ARM processors have core extensions that add specific features or functions to improve
performance, flexibility, or capabilities. Here are three main types of ARM core extensions:

1. Jazelle Extension:
o The Jazelle extension enables Java bytecode execution directly on the
hardware.
o This extension makes running Java programs faster and more efficient,
especially useful in mobile and embedded systems where Java is common.
o By processing Java code directly, Jazelle reduces the need for extra software
layers, saving power and memory.
2. Thumb Extension:
o The Thumb extension provides a compact 16-bit instruction set (instead of
the standard 32-bit instructions).
o This reduces the code size, saving memory space and improving efficiency,
especially in memory-limited environments.
o Thumb instructions are faster to fetch and execute in systems with limited
resources, making it ideal for embedded applications.
3. NEON Extension:
o The NEON extension is a Single Instruction, Multiple Data (SIMD) engine,
optimized for multimedia processing.
o It allows the processor to handle multiple data points simultaneously,
improving performance for tasks like image processing, audio processing, and
graphics.
o NEON is particularly useful in devices needing high-performance graphics
and multimedia capabilities, like smartphones and tablets.
14) Explain barrel shifter and ALU in ARM core with diagram.
15) What are data processing instructions.

Here are the main types of data processing instructions:

1. Arithmetic Instructions: These instructions handle math operations:

o ADD, SUB: Add or subtract numbers.
o MUL: Multiply numbers.
o DIV: Divide numbers (on processors with division support).
2. Logical Instructions: These perform logical operations, often used in decision-
making:
o AND, OR, NOT: Basic logical operations on bits.
o XOR: Exclusive OR, used to compare bits in a unique way.
3. Shift and Rotate Instructions: These move bits left or right within a data value:
o LSL (Logical Shift Left) and LSR (Logical Shift Right): Shift bits left or
right, commonly used in multiplication or division by powers of 2.
o ROR (Rotate Right): Rotates bits to the right, allowing circular movement of
bits.
4. Comparison Instructions: These compare two values and set status flags based on
the result:
o CMP (Compare): Compares two values to see if one is greater, equal, or less
than the other.
o CMN (Compare Negative): Compares one value to the negative of another.
16) Explain MOV, EQR, BIC, CMP and MLA instructions with syntax

1. MOV (Move)

• Purpose: Copies a value from one register or an immediate value into another register.
• Syntax: MOV Rd, Operand
o Rd: Destination register.
o Operand: Source register or immediate value.
• Example: MOV R0, #5 → Moves the value 5 into register R0.

2. EOR (Exclusive OR)

• Purpose: Performs a bitwise exclusive OR (XOR) operation between two values.

• Syntax: EOR Rd, Rn, Operand
o Rd: Destination register.
o Rn: First source register.
o Operand: Second source (can be a register or immediate value).
• Example: EOR R0, R1, #3 → Performs an XOR between R1 and 3, storing the result in R0.

3. BIC (Bit Clear)

• Purpose: Clears specific bits in a register by performing a bitwise AND with the inverse of the
operand.
• Syntax: BIC Rd, Rn, Operand
o Rd: Destination register.
o Rn: First source register.
o Operand: Value to be inverted and ANDed with Rn.
• Example: BIC R0, R1, #0xF0 → Clears the bits in R1 that match 0xF0 and stores the
result in R0.

4. CMP (Compare)

• Purpose: Compares two values by subtracting the operand from the first register and sets
flags based on the result (but does not store the result).
• Syntax: CMP Rn, Operand
o Rn: Register containing the first value.
o Operand: Second value to compare (register or immediate).
• Example: CMP R0, #10 → Compares R0 with 10, setting flags like Zero if R0 equals 10.

5. MLA (Multiply Accumulate)

• Purpose: Multiplies two values and adds the result to a third value.
• Syntax: MLA Rd, Rn, Rm, Ra
o Rd: Destination register.
o Rn: First multiplier.
o Rm: Second multiplier.
o Ra: Accumulator register (value added to the result of multiplication).
• Example: MLA R0, R1, R2, R3 → Multiplies R1 and R2, then adds R3 to the result,
storing it in R0
 17) Explain LSL and ROR operators with example.

1. LSL (Logical Shift Left)

• Purpose: Shifts all bits in a value to the left by a specified number of positions. Each shift to
the left doubles the value (similar to multiplying by 2).
• Syntax: LSL Rd, Rn, #shift
o Rd: Destination register.
o Rn: Source register.
o #shift: Number of positions to shift left.
• Example: If R0 contains 00000010 (binary for 2), then:

LSL R1, R0, #1 ; Shifts R0 left by 1 bit

o After the operation, R1 will contain 00000100 (binary for 4), as shifting left by 1 bit
doubled the value.

2. ROR (Rotate Right)

• Purpose: Rotates all bits in a value to the right by a specified number of positions. The bits
that move off the right side are reintroduced on the left side, effectively “rotating” the bits.
• Syntax: ROR Rd, Rn, #rotate
o Rd: Destination register.
o Rn: Source register.
o #rotate: Number of positions to rotate right.
• Example: If R0 contains 10000001 (binary for 129), then:

ROR R1, R0, #1 ; Rotates R0 right by 1 bit

o After the operation, R1 will contain 11000000 (binary for 192), because the 1 on
the far right moved to the far left position.

18) Explain ASR and RRX operators with example

1. ASR (Arithmetic Shift Right)

• Purpose: Shifts all bits in a value to the right by a specified number of positions, while
preserving the sign of the number. The most significant (leftmost) bit (sign bit) is retained for
each shift, making ASR suitable for signed numbers.
• Syntax: ASR Rd, Rn, #shift
o Rd: Destination register.
o Rn: Source register.
o #shift: Number of positions to shift right.
• Example: If R0 contains 11110000 (binary for -16 in two’s complement notation), then:

ASR R1, R0, #2 ; Shifts R0 right by 2 bits

 o After the operation, R1 will contain 11111100 (binary for -4), as the sign bit (1) is
extended to preserve the negative value. This is equivalent to dividing by 4 with sign
preservation.

2. RRX (Rotate Right with Extend)

• Purpose: Rotates all bits in a value to the right by one position, with the rightmost bit
moving into the carry flag and the carry flag moving into the leftmost bit. This operation is
useful for extending rotations or handling large bit shifts.
• Syntax: RRX Rd, Rn
o Rd: Destination register.
o Rn: Source register.
• Example: If R0 contains 01100001 (binary for 97) and the carry flag (C) is 1, then:

RRX R1, R0 ; Rotates R0 right by 1 bit with the carry flag

o After the operation, R1 will contain 10110000, and the last bit (1) from R0 moves
into the carry flag.